COMMUNICATIONS NETWORKS

Technical Field

The present disclosure relates to clock synchronization in packet communication networks, in general, and in particular to method and apparatus for obtaining phase and frequency offsets for synchronizing clocks.

Background

Ethernet has been proposed for the 5G fronthaul transport network between the baseband unit (BBU) pools and the remote radio heads (RRHs). The advantages of adopting an Ethernet transport include the low cost of equipment, the use of a shared infrastructure with statistical multiplexing, as well as the ease of operations, administration and maintenance (OAM). Additionally, for 5G to support key technologies such as massive multiple-input and multiple- output (MIMO) and Coordinated Multipoint (CoMP), the Common Public Radio Interface (CPRI) and eCPRI transport network should provide for high bitrates with very low latency and jitter.

Achieving clock synchronization between communicating nodes in a large system is a challenge. The complexity of this challenge increases if the clocks are not exchanged between the nodes which usually leads to de-synchronizing. This is the case when devices (e.g., network nodes) communicate through Ethernet - there is no exchange of clocks between nodes. Instead, synchronization of clocks between Ethernet connected devices is achieved using Ethernet communication through a preamble part of the Ethernet packet.

One of the techniques for synchronising Ethernet connected nodes is called Precision Time Protocol (PTP) and is used to detect and correct the clock synchronization error in Ethernet network. PTP was first defined in IEEE 1588-2002 standard and later the IEEE 1588-2008 standard defined an improved version of the PTP protocol (also referred to as PTP v2). The IEEE 1588-2008 protocol provides improved accuracy over the 2002 version. The PTP implementation uses the Ethernet packet preambles for transmitting timestamps. PTP reduces the clock synchronization error to hundreds of nanoseconds, but in some applications in 5G even more accurate synchronization is required. Hence, an important requirement is that the clock synchronization error is kept to a minimum. This error corresponds to the clock phase and frequency offsets between two clocks in two Ethernet communicating nodes.

Summary

It is the object of the disclosed solution to obviate at least some of the above disadvantages and provide an improved method and apparatus for obtaining phase and frequency offsets for synchronizing clocks.

Accordingly, the disclosed solution seeks to preferably mitigate, alleviate or eliminate one or more of the disadvantages mentioned above singly or in any combination.

According to a first aspect there is provided a method of obtaining phase and frequency offsets for synchronising a slave clock at a slave node with a master clock at a master node in a packet communications network. The method performed at the master node comprises transmitting signals to and receiving signals from the slave node, wherein the signals carry periodic markers at a physical layer. The method further comprises calculating a plurality of values indicative of round-trip time based on detection at the master node of first markers in a first signal transmitted from the master node to the slave node and detection at the master node of second markers in a second signal received from the slave node and applying regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.

According to a second aspect there is provided a method of obtaining phase and frequency offsets for synchronising a slave clock at a slave node with a master clock at a master node in a packet communications network. The method performed at the slave node comprises transmitting signals to and receiving signals from the master node, wherein the signals carry periodic markers at a physical layer and calculating a plurality of values indicative of round-trip time based on detection at the slave node of second markers in a second signal transmitted from the slave node to the master node and detection at the slave node of first markers in a first signal received from the master node. The method further comprises applying regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.

According to a third aspect there is provided an apparatus for obtaining phase and frequency offsets for synchronising a slave clock at a slave node with a master clock at a master node in a packet communications network. The apparatus comprising a processing circuitry and a memory. The memory contains instructions executable by the processing circuitry such that the apparatus is operative to transmit signals to and receiving signals from the slave node, wherein the signals carry periodic markers at a physical layer. The apparatus is further operative to calculate a plurality of values indicative of round-trip time based on detection at the master node of first markers in a first signal transmitted from the master node to the slave node and detection at the master node of second markers in a second signal received from the slave node and apply regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.

According to a fourth aspect there is provided an apparatus for obtaining phase and frequency offsets for synchronising a slave clock at a slave node with a master clock at a master node in a packet communications network. The apparatus comprises a processing circuitry and a memory. The memory contains instructions executable by the processing circuitry such that the apparatus is operative to transmit signals to and receiving signals from the master node, wherein the signals carry periodic markers at a physical layer. The apparatus is also operative to calculate a plurality of values indicative of round-trip time based on detection at the slave node of second markers in a second signal transmitted from the slave node to the master node and detection at the slave node of first markers in a first signal received from the master node and to apply regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock. According to a fifth aspect there is provided a packet communications network comprising a master node and a slave node. The packet communications network further comprises an apparatus for obtaining phase and frequency offsets for synchronising a slave clock at the slave node with a master clock at the master node. The apparatus comprises a processing circuitry and a memory. The memory contains instructions executable by the processing circuitry such that the apparatus is operative to transmit signals to and receiving signals from the slave node, wherein the signals carry periodic markers at a physical layer. The apparatus is further operative to calculate a plurality of values indicative of round-trip time based on detection at the master node of first markers in a first signal transmitted from the master node to the slave node and detection at the master node of second markers in a second signal received from the slave node. The apparatus is further operative to apply regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.

According to a sixth aspect there is provided a packet communications network comprising a master node and a slave node. The packet communications network further comprises an apparatus for obtaining phase and frequency offsets for synchronising a slave clock at a slave node with a master clock at a master node. The apparatus comprises a processing circuitry and a memory. The memory contains instructions executable by the processing circuitry such that the apparatus is operative to transmit signals to and receiving signals from the master node, wherein the signals carry periodic markers at a physical layer. The apparatus is further operative to calculate a plurality of values indicative of round-trip time based on detection at the slave node of second markers in a second signal transmitted from the slave node to the master node and detection at the slave node of first markers in a first signal received from the master node. The apparatus is further operative to apply regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.

The disclosed solution provides the benefit of improved accuracy of clock synchronisation in packet communications network (i.e., even further reduced clock synchronisation error). Moreover, embodiments described herein require measurements to be carried out only at one node such that transmitting timestamps is not required, which results in releasing some channel resources that would be consumed by existing techniques. Further, the disclosed solution can be implemented with existing hardware without change, and combining this solution with PTP protocol does not require any complex changes to the system.

Brief description of the drawings

The disclosed solution will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings in which:

FIG. 1A and FIG. IB are diagrams illustrating master and slave nodes operating in one embodiment;

FIG. 2A is a diagram illustrating clock skew;

FIG. 2B is a diagram illustrating phase and frequency offset;

FIG. 3 is a flowchart illustrating a method of obtaining phase and frequency offsets for synchronizing a slave clock with a master clock in a packet communications network in one embodiment;

FIG. 4 is a flowchart illustrating a method of obtaining phase and frequency offsets for synchronizing a slave clock with a master clock in a packet communications network in another embodiment;

FIG. 5 and FIG. 6 are diagrams illustrating principles of RTT protocol in one embodiment;

FIG. 7 to FIG. 9 illustrate measurements of values indicative of round-trip time in one embodiment;

FIG. 10 and FIG. 11 illustrate details of Reed-Solomon Forward Error Correction sublayer;

FIG. 12 to FIG. 14 illustrate hierarchy of clocks and synchronization in a communications network; FIG. 15 is a diagram illustrating an apparatus for obtaining phase and frequency offsets for synchronizing a slave clock with a master clock in a packet communications network in one embodiment. Detailed description

In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the disclosed solution. However, it will be apparent to those skilled in the art that the disclosed solution may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the disclosed solution with unnecessary details.

Reference throughout the specification to“one embodiment” or“an embodiment” means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the disclosed solution. Thus, the phrases“in one embodiment” or“in an embodiment” do not necessarily refer to the same embodiment but rather to some embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. Ethernet is used for exchange of data between devices and can also be used for connecting devices to the Internet. As mentioned earlier it has also been proposed for the 5G fronthaul transport network. Ethernet communication speeds or throughput can be up to 25 Gbps. In Ethernet-based communication, only transmit (TX) and receive (RX) data lines are exchanged between communicating nodes as illustrated in Figures 1A and IB. The Ethernet node 1 transmitter (TX) to Ethernet node 2 receiver (RX) forms Link 1 and the Ethernet Node 2 TX to Ethernet Node 1 RX forms Link 2. Each of the nodes have their individual clock and no exchange of clock information takes place. This may lead to clocks at the respective nodes drifting apart and eventually to clock de-synchronization. There are two types of clock offset: clock skew (also known as clock phase offset) and clock jitter (also known as clock frequency offset). In the case of clock phase offset, both clocks have the same frequency but the phase of one clock is shifted as compared to the other as illustrated in Figure 2A. A phase offset is usually caused by problems during synchronization. Figure 2B illustrates clock frequency offset, in which the frequencies (or, equivalently, the periods T1 and T2) of the two clocks differ. Clock frequency offset is often caused by improper clock generator circuitry, noise, or interference.

Embodiments of the present disclosure determine the clock synchronization error (i.e., phase and frequency offset) by determining a plurality of values indicative of round- trip time (RTT). In some embodiments, an RTT protocol may be implemented along an existing protocol (e.g., PTP) as an add-on feature. As disclosed in this document, the values indicative of round-trip time of the data exchanged between two communicating nodes are calculated. A plurality of values indicative of RTT are determined based on a large number of data transactions between the nodes to be synchronized. The gathered values indicative of RTT are processed using one of known mathematical models (applying regression analysis) to derive (approximate) the clock phase and frequency offset.

With reference to Figure 3 a method of obtaining phase and frequency offsets for synchronising a slave clock at a slave node with a master clock at a master node in a packet communications network will now be described. The method in one embodiment may be performed at the master node. When performed at the master node the method comprises transmitting signals to and receiving signals (in operation 302) from the slave node, wherein the signals carry periodic markers at a physical layer, which is also referred to as Layer 1 in the OSI (Open Systems Interconnection) model. The method then comprises calculating, 304, a plurality of values indicative of round-trip time based on detection at the master node of first markers in a first signal transmitted from the master node to the slave node and detection at the master node of second markers in a second signal received from the slave node. When the plurality of the values indicative of round- trip time are calculated the method comprises applying regression analysis, 306, to the calculated values to approximate values of phase and frequency offset of the slave clock.

Figure 4 illustrates an embodiment of the operation of calculating the plurality of values indicative of round-trip time. When the method is implemented at the master node, 102, the master node, 102, transmits a first signal, 108, (e.g., Ethernet packet if the master and slave nodes are connected using Ethernet base links) to the slave node, 104. The communication between the master, 102, and slave, 104, nodes is bidirectional, so the master node receives a second signal, 106, from the slave node. The method comprises detecting (in operation 402, yes), at the master node, 102, a first marker at a physical layer of the first signal, 106. The master node, 102, then determines (in operation 404) a first clock value, Ti, in response to detection of said first marker. This is the time when the first marker has been detected. The master node then detects (in operation 406, yes) a second marker at a physical layer of the second signal, 108, and determines (in operation 408) a second clock value, T2, in response to detection of said second marker. This is the time when the second marker has been detected. The method then goes on to calculate (in operation 410) a value indicative of round-trip time between the master node and the slave node as a difference between said second clock value and said first clock value, RTT indicative = T2 - Ti. The operations 402 - 410 are repeated multiple times in order to obtain a set of values of RTTindicative (in operation 412, no). Once there is enough of the of RTTindicative values (operation 412, yes), the method applies one of the known mathematical models to approximate phase and frequency values using for example regression analysis (operation 306).

The method in its embodiments is based on using equidistant (periodic) markers and once the markers are inserted in the signals transmitted by the nodes 102 and 104 then the method may preferably use each marker (consecutive markers). However, in alternative embodiments the method does not have to use each marker inserted for calculating the RTTindicative values. If the markers are inserted periodically the method will also work if we calculate the RTTindicative values using e.g., only every second (or third, or n-th marker) as they still will be periodic. This is why the method does not have to rely on actual round-trip value, but with the markers being periodic if the clocks at the master and slave nodes are in sync the obtained RTTindicative values will be identical and if the clocks are not in sync the RTTindicative will fluctuate. This is illustrated in Figures 5 and 6. In Figure 5 the clocks are in sync and the RTTindicative values 502, 504 and 506 are equal. In Figure 6 the clocks are not in sync and the RTTindicative values 602, 604 and 606 fluctuate. As one can see the values 502 - 506 and 602 - 606 are not exactly round-trip time, but it’s clear from the drawing that they are determined in a way similar to determining RTT values. What is important for embodiments of the method is that these values are determined based on periodic events (e.g., detection of the markers) and that a large enough set of these values is determined so that their fluctuation can be processed using one of the mathematical models based on regression analysis.

This fluctuation of RTTindicative values is illustrated in Figure 7. The top part of Figure 7 shows the periodic events used to determine the RTTindicative values and the bottom part shows a series of plots illustrating how the RTTindicative values change (fluctuate). The same is illustrated in Figure 8 where different periodic events have been chosen for calculating the RTTindicative values. Waveform 1 in Figure 8 illustrates a situation where the clocks at master, 102, and slave, 104, nodes are in sync. As one can see the RTTindicative values in the bottom plots form a straight horizontal line meaning the values were identical. In this example the master node, 102, begins transmitting at the first clock edge, whereas the slave node, 104, begins transmitting at the second. Each node transmits periodically at every 4th clock edge and as can be seen the RTTindicative (RTTindicative value is calculated from the time the master, 102, transmits a frame to the time when it receives a frame from the slave, 104) which is the same for all the intervals from 1-22. When the RTTindicative values are plotted, a straight line is produced.

Waveform 2 illustrates situation when the clocks at master, 102, and slave, 104, nodes are not in sync and the RTTindicative values produced a sawtooth waveform with fluctuating RTTindicative values. The RTTindicative values are generated the same way as shown in waveform 1 , but the plot at the bottom is different as a result of the clocks not being synchronized. As can be seen the RTTindicative values first decrease until the 21 ^st transmission and then increase at the 22 ^nd transmission generating a sawtooth waveform.

Such a sawtooth waveform is illustrated in Figure 9 with about 20000 samples collected. The number of samples collected is implementation specific. It may be predefined as a target value and the method continues calculating the RTTindicative values until the target is reached or there may be a time limit for obtaining the RTTindicative values.

In one embodiment the operation of calculating a plurality of values indicative of round-trip time is performed using consecutive first and second markers. In this embodiment an RTTindicative value is calculated after determining T1 value for a first marker and then T2 value for a second marker detected immediately after the first marker for which T 1 has been determined. In this embodiment each marker is used for calculating RTTindicative. The advantage is increased accuracy due to increased number of samples (i.e., the samples will be densely packed to form the sawtooth waveform). If only every second marker is used (or every n-th marker in general), the sawtooth waveform may not be as smooth as the one illustrated in Figure 9.

In an alternative embodiment the operation of calculating a plurality of values indicative of round-trip time is performed using every n-th first and second markers. This means that not all markers will be used for calculating RTTindicative values, but instead every second first marker and every second second marker will be used to calculate the RTTindicative values. Similarly, every third, fourth, etc marker may be used. Because the markers are periodic then every n-th market is also periodic. The advantage is reduced processing load (fewer samples in the set, slower processing).

The periodic markers are inserted into the first and second signals with a frequency determined by the clocks to be synchronised.

Preferably, said first markers and said second markers are independent of each other. This means that the markers are not inserted into the signal transmitted from one of the nodes in response to detection by said node of a marker in a received signal. Rather the markers are inserted as a result of operation of the node on the transmit line irrespective of operation of the receive line. In embodiments of the solution disclosed in this document the RTT protocol will be implemented with the existing Ethernet protocol. A value indicative of round-trip time of a single Ethernet packet in embodiments of this solution may be calculated from a Start of Frame (SoF) signal which is available during the transmission and reception of a packet. The values indicative of RTT calculated from equidistant (periodic) signals transmitted in Layer 1 may be used to augment the SoF of a single ethernet frame. The values of clock phase and frequency offset can be determined by applying a mathematical model to these values indicative of RTT. In preferred embodiments the mathematical model uses regression analysis to the calculated values to approximate values of phase and frequency offset of the slave clock.

Embodiments of the present disclosure use markers (e.g., signals) periodically inserted at the physical layer of signals exchanged between master and slave node. Although some embodiments may use periodic markers purposefully inserted for the determination of the phase and frequency offsets of the slave clock, it may be particularly advantageous to use for this purpose Layer 1 periodic markers that are already present in the communication signals exchanged between master and slave node. Therefore, in one embodiment, the method of obtaining phase and frequency offsets may use Code Word Markers (CWMs) present (e.g., inserted) in Reed-Solomon Forward Error Correction (RS-FEC, defined in clause 108 of IEEE Std 802.3-2018 standard [2]) as the first and second markers. In another embodiment, the method may use Parity Symbols (PS) as the first and second markers. The Parity Symbols are also present (e.g., inserted) in the RS- FEC.

In one embodiment the method to determine the clock’s phase and frequency offsets may be implemented in the physical (PHY) layer of the OSI model with the help of the RS-FEC sublayer. The RS-FEC sublayer, 1002, is shown in Figure 10 and illustrated in more detail in Figure 11.

At the RS-FEC sublayer operates a Codeword Marker Insertion block which inserts CWMs into transcoded blocks before they go to Reed-Solomon encoder. These CWMs form the first 257-bits of every 1024th RS-FEC codeword. In the case of 25 Gbps Ethernet, the time between the beginning of successive codeword makers is 209.709919 microsecond (ps) or 4.768492 kilohertz (kHz). Hence, the CWMs are present in the signal transmitted between the master, 102, and slave, 104, nodes and they are equidistant (periodic). The Codeword Markers are very useful for the receiver, since the codeword marker synchronization block uses these alignment markers to obtain lock to the incoming bit stream and ensure codeword alignment. The CWM insertion and removal function of RS-FEC sublayer is part of the PHY layer. The same considerations are applicable to so called rapid CWM which are together with CWM defined in IEEE 802.3by - 2018 standard, clauses 108.5.2.4 (insertion) and 108.5.3.4 (removal).

In operation, when a packet is transmitted from the master node, 102, a CWM is detected on the transmitting channel (first marker) and a Start of Frame for Transmitter (SoF_TX) signal is asserted for one clock period in the master node, 102. Whereas, when a CWM is detected on the receiving channel (second marker) a Start of Frame for Receiver (SoF_RX) signal is asserted for one clock period in the master node, 102, this is shown in Figures 1A and IB. The time difference between the assertion of the two signals forms the value indicative of round-trip time value of an Ethernet packet between the master, 102, and slave, 104, nodes.

In an alternative embodiment Parity Symbols used by the RS-FEC sublayer may be used as the periodic first and second markers. A Reed-Solomon Encoder block operates on the RS-FEC sublayer, 1002, and converts 514 information symbols to a codeword containing 528 symbols by appending parity symbols. The codeword consists of 514 information symbols and 14 Parity Symbols (PS). Each symbol is made up of 10- bits. In case of the Reed-Solomon Decoder, the PS is used for correctly decoding the received codeword to extract the information symbols and correcting them if necessary. For 25 Gbps Ethernet, the time between the beginning of successive PS is 204.794843 nanosecond (ns) or 4.882935463 megahertz (MHz). Hence, the Parity Symbols are present in the signal transmitted between the master, 102, and slave, 104, nodes and they are equidistant (periodic). The PS help in error detection and correction in the received codeword. In the case of parity symbols, when a PS is detected in the transmit channel (a first marker) a Detect Parity_Transmit (DP_TX) signal is asserted for one clock period. When a PS is detected in the receive channel (second marker) a Detect Parity Receive (DP_RX) signal is asserted for one clock period, this is shown in Figures 1A and IB. Next, similar to the implementation with CWM, the time difference between the assertion of the two signals is calculated and it is the value indicative of round-trip time value of an Ethernet packet between the master, 102, and slave, 104, nodes.

Because PS and CWM are repeated at a fixed unit interval (periodically), a measurement of values indicative of round-trip time of an Ethernet packet can be made more effective as it only needs to detect the CWM or PS markers at fixed locations in the transmit and receive lanes.

A third clock, which is faster than the master, 110, and slave, 112, clocks at the two nodes is used to check when the signals are asserted (SoF_TX and SoF_RX or DP TX and DP RX).

When the RTTindicative values are collected they need to be further processed to get the clock phase and frequency offset. As mentioned earlier, one of the known mathematical models can be used to determine these values. To accomplish this task three algorithms were considered as described in [1]: Unwrapped Least Squares (ULS), Periodogram and Correlation Peaks (PCPs), and Weighted Least Squares (WLS).

On a system level, this solution can be implemented with the existing designs. In the existing designs, clocks are distributed through a network of clocks representing a hierarchy as seen in the Figure 12. At the top of the hierarchy is the Grand Master (GM) clock, this clock is always synchronized and does not have any clock phase and frequency offset. Immediately following the GM is the Boundary Clock (BC) at one step below in the hierarchy, which synchronizes with the GM clock. And finally, at the bottom of the hierarchy is the Ordinary Clock (OC), which synchronizes with the BC. Figure 12 displays only one BC between the GM and the OC but, there may be multiple BCs between them with each BC at a lower-level in the hierarchy synchronizing with the immediate higher-level BC.

In the existing designs, the BC synchronizes to the GM clock and the OC synchronizes to the BC through the implementation of the PTP. The RTT protocol described in this document may be implemented along with the existing PTP in the following scenarios to improve the system level clock synchronization:

• The RTT protocol may be implemented between the BC and the OC as shown in Figure 13. This allows the OC to further synchronize its clock with the BC as compared to only when the PTP is executed. This will help the OC to have a tighter clock synchronization with the BC.

• The RTT protocol may be also implemented between the GM clock and the BC, and between the BC and the OC, as seen in Figure 14. In the first step the BC will be synchronized with the GM clock by implementation of the PTP and RTT protocols, thus ensuring the BC is tightly synchronized with the GM clock. Next, the OC is synchronized with the BC through implementation of the PTP and RTT protocols, which will ensure that the OC is tightly synchronized with the BC. This leads to the OC being tightly synchronized with the GM clock.

Once the values of phase and frequency offset are approximated at the master node these values may be communicated to the slave node, 104, for synchronizing the slave clock, 112.

In one embodiment the GM clock, operating as a master clock, may align the Tx markers it sends with an external timing source that provides precise time information. In one embodiment this may be a global navigation satellite system (GNSS) which provides location and precise time information, for example Global Positioning System (GPS), Galileo, GLONASS or BeiDou. The GM clock may derive its timing signal from a GNSS source and may then send downstream the Tx markers with timing based on the GNSS derived timing. In this way the slave clocks (Boundary Clock and further Boundary Clocks and Ordinary Clocks) in the packet communications network will be synchronised using the RTT protocol to the GM and its external timing source (GNSS) by synchronising their downstream Tx ports with their upstream Rx ports as shown in Figure 14.

The method in its embodiments has been described above from the perspective of the master node, 102. In other words, the operations of the method are performed at the master node. In alternative embodiments the method can equally be performed at the slave node 104. When the method performed is performed at the slave node, 104, the method comprises transmitting signals to and receiving signals from the master node, 102 (in operation 302), wherein the signals carry periodic markers at a physical layer. The method also comprises calculating (in operation 304) a plurality of values indicative of round-trip time based on detection at the slave node, 104, of second markers in a second signal transmitted from the slave node, 104, to the master node, 102, and detection at the slave node, 104, of first markers in a first signal received from the master node, 102. Finally, the method comprises applying regression analysis (in operation 306) to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.

Preferably, the operation of calculating the plurality of values indicative of round- trip time comprises detecting at the slave node, 104, a second marker at a physical layer of the second signal, said second signal being for transmission from the slave node to the master node. In the following operation the method comprises determining, a third clock value in response to detection of said second marker. Then the method comprises detecting at the slave node, 104, a first marker at a physical layer of the first signal, said first signal being received from the master node and determining a fourth clock value in response to detection of said first marker. In the next step a value indicative of round-trip time between the slave node and the master node is calculated as a difference between said fourth clock value and said third clock value. The above operations are repeated to calculate a plurality of values indicative of round-trip time for a plurality of said first and second markers. Although a flowchart illustrating details of implementing the method at the slave node is not included it is clear from the above description that it would clearly correspond to the one presented in Figure 4.

All remaining embodiments applicable to implementation of the method at the master node are equally applicable to implementation at the slave node.

Once the values of phase and frequency offset are approximated at the slave node, 104, the may be used for synchronizing the slave clock, 112, without transmitting them over the network.

Figure 15 illustrates one embodiment of an apparatus, 150, 102 or 104, which implements the method of obtaining phase and frequency offsets for synchronising a slave clock at a slave node with a master clock at a master node in a packet communications network described earlier. The apparatus, 150, 102 or 104, comprises a processing circuitry, 1502, and a memory, 1504. The memory, 1504, contains instructions executable by the processing circuitry, 1502, such that the apparatus, 150, 102 or 104, is operative to transmit signals to and receiving signals from the slave node, wherein the signals carry periodic markers at a physical layer. The apparatus, 150, 102 or 104, is also operative to calculate a plurality of values indicative of round-trip time based on detection at the master node, 102, of first markers in a first signal transmitted from the master node, 102, to the slave node, 104, and detection at the master node, 102, of second markers in a second signal received from the slave node, 104, and apply regression analysis to the calculated values indicative of round-trip time to approximate values of phase and frequency offset of the slave clock.

The apparatus, 150, 102 or 104, may include a processing circuitry (one or more than one processor), 1502, coupled to an interface, 1506, and to the memory 1504. The apparatus, 150, 102 or 104, may comprise more than one interface. For example, one interface may be an Ethernet interface for connecting to the slave node, 104, and another interface may be provided for a network operator to perform management operations on the apparatus 150, 102 or 104. By way of example, the interface 1506, the processor(s) 1502, and the memory 1504 may be connected in series as illustrated in Figure 15. Alternatively, these components 1502, 1504 and 1506 may be coupled to an internal bus system of the apparatus, 150, 102 or 104. The memory 1504 may include a Read-Only- Memory (ROM), e.g., a flash ROM, a Random Access Memory (RAM), e.g., a Dynamic RAM (DRAM) or Static RAM (SRAM), a mass storage, e.g., a hard disk or solid state disk, or the like. The memory, 1504, may include software, 1512, and/or control parameters, 1514. The memory, 1504, may include suitably configured program code to be executed by the processor(s), 1502, so as to implement the above-described method as explained above.

In one embodiment the apparatus, 150, may be implemented as a separate unit, 150, connected to the master node, 102, as illustrated in Figure 1A. Alternatively, the apparatus may be integrated as part of the master node, 102, as illustrated in Figure IB. In the embodiment illustrated in Figure IB the apparatus 105 may be a software function or a hardware component of the master node, 102.

As discussed above, the method of obtaining phase and frequency offsets for synchronising a slave clock, 112, with a master clock, 110, may be equally implemented at the slave node 104. Similarly, the apparatus, 150, may be implemented as a separate unit, 150, connected to the slave node, 104. Alternatively, the apparatus, 150, may be integrated as part of the slave node, 104. When integrated as part of the slave node, 104 the apparatus 105 may be a software function or a hardware component of the slave node, 104.

It is to be understood that the structures as illustrated in Figure 15 are merely schematic and that the apparatus, 150, 102 or 104, may actually include further components which, for the sake of clarity, have not been illustrated, e.g., further interfaces or processors. Also, it is to be understood that the memory, 1504, may include further program code for implementing other and/or known functionalities.

According to some embodiments, also a computer program may be provided for implementing functionalities of the apparatus, 150, 102 or 104, e.g., in the form of a physical medium storing the program code and/or other data to be stored in the memory 1504, or by making the program code available for download or by streaming.

It is also to be understood that the apparatus, 150, 102 or 104, may be provided as a virtual apparatus. In one embodiment, the apparatus, 150, 102 or 104, may be provided in distributed resources, such as in cloud resources. When provided as virtual apparatus, it will be appreciated that the memory, 1504, processing circuitry, 1502, and physical interface(s), 1506, may be provided as functional elements. The functional elements may be distributed in a logical network and not necessarily be directly physically connected. It is also to be understood that the apparatus, 150, 102 or 104, may be provided as single- node devices, or as a multi-node system.

The apparatus, 150, 102 or 104, is further configured to carry all the other embodiments of the methods described above.

The methods of the present disclosure may be implemented in hardware, or as software modules running on one or more processors. The methods may also be carried out according to the instructions of a computer program, and the present disclosure also provides a computer readable medium having stored thereon a program for carrying out any of the methods described herein. A computer program embodying the disclosure may be stored on a computer readable medium, or it could, for example, be in the form of a signal such as a downloadable data signal provided from an Internet website, or it could be in any other form.

References:

[1] S. Dwivedi, A. De Angelis, D. Zachariah and P. Handel, "Joint Ranging and Clock Parameter Estimation by Wireless Round Trip Time Measurements," in IEEE Journal on Selected Areas in Communications, vol. 33, no. 11, pp. 2379-2390, Nov. 2015. [2] IEEE Standard for Ethernet," in IEEE Std 802.3-2018 (Revision of IEEE Std 802.3- 2015), voL, no., pp.1-5600, 31 Aug. 2018