FIELD OF THE INVENTION

The present application relates generally to clock synchronization and, more specifically, to clock

synchronization in shared baseband deployments.

BACKGROUND OF THE INVENTION

Network operators upgrading their networks from 2G/3G networks to 4G networks; want a network evolution solution which permits the leveraging of a portion of their installed baseband equipment. In some cases this means that multi- standard mixed mode radios are used to support efficient in- band combining to ease the service transition from 2G/3G equipment to 4G equipment. Emerging deployments of shared radio solutions for base stations operating on multiple standards face particular challenges in relation to

operating on a common clock synchronization. Each standard usually run from its own clocking domain.

When the timing or synchronization reference is

temporarily lost, a network's ability to maintain time and sync stability becomes critical to ensure continued optimal network performance. The time period that a network is able to maintain time and sync stability without a reference is called the holdover time.

Precise synchronization is especially critical in mobile networks for the successful call signal handoff and proper transmission between base stations, as well as for the transport of real-time services. If individual base stations drift outside the specified frequencies, mobile handoff performance decays, calls interfere, and calls cannot be made, resulting in high dropped-call rates and impaired data services. In the event that timing or

synchronization reference is temporarily lost, a network's ability to maintain time or "holdover" becomes critical to ensure optimal network performance.

These synchronization issues are further dilapidating in shared baseband deployments since holdover requirements are not standard; they vary depending on the system type, complexity, and operator's requirements. In shared baseband deployments, two heterogeneous systems with independent synchronization inputs are expected to produce outputs which are synchronized to one another, typically so that they can be combined together without loss of data. Existing clock synchronization solutions provide limited holdover

capabilities in the case where one or both of the systems lose their synchronization inputs, leading to the outputs becoming unsynchronized with each other.

For these reasons, traditional synchronization has limited capabilities in situations as described above.

SUMMARY OF THE INVENTION

The present invention is directed to alleviating the problems of the prior art .

The present invention overcomes the problems of the prior art by providing a method of synchronization wherein synchronization is provided from one system to the other by recovering a clock from one system's output, then using that synchronization to regenerate a synchronization source for the other system. This allows synchronization between systems to be maintained even in the case where the input synchronization source is lost. In addition, if the timing source of one system starts to drift with the lost of a GPS signal, the second system will drift along with it such that the timing remains consistent between the two networks.

In accordance with an embodiment of the present

invention, there is provided a method of providing timing synchronization between a first Radio Equipment Controller (REC) and a second REC operating with a multi - standard radio. A synchronization signal is received from a first synchronization source and a synchronized data output derived from the synchronization signal is generated. A first clock signal is generated from the synchronized data output. A synchronization source is then reconstructed from the first clock signal . A timing and frequency component of a second clock signal is then aligned to that of the

reconstructed synchronization source, such that the second REC can maintain timing synchronization with the first REC.

In accordance with another embodiment of the present invention, there is provided a system for providing timing synchronization between a first Radio Equipment Controller (REC) and a second REC operating with a multi - standard radio. The system comprises radio means for receiving a synchronization signal from a first synchronization source and first synchronization means for generating a

synchronized data output derived from the synchronization signal. A second synchronization means is used for

generating a first clock signal from the synchronized data output and means for reconstructing a synchronization source from said first clock signal is provided. The system further comprises means for aligning a timing and frequency component of a second clock signal to that of the

reconstructed synchronization source, such that the second REC can maintain timing synchronization with the first REC. Other aspects and features of the present invention will become apparent to those of ordinary skill in the art upon review of the following description of specific

embodiments of the invention in conjunction with the

accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram illustrating the timing principles of a 2G/3G radio;

Fig. 2 is a block diagram illustrating the timing principles of an 4G radio;

Fig. 3 is a block diagram illustrating a high level topology of a base station radio system according to the present invention;

Fig. 4 is a block diagram of an Multiplexing Unit (MU) according to the present invention;

Figs. 5a- 5g are conceptual diagrams of the flow of timing through the system for various operational scenarios.

DETAILED DESCRIPTION OF THE EMBODIMENTS In order to lighten the following description, the following acronyms will be used:

1PPS One Pulse per second

BTS Base Station

CBTS CDMA Base Station LTE REC Digital Radio Unit LTE GPS Global Positioning System

HSSL High Speed Serial Link

OCXO Oven Controlled Crystal Oscillator

PHY Physical Interface

VCXO Voltage Controlled Crystal Oscillator MU Multiplexer Unit

As indicated above, the present invention addresses the issues brought out by the aforementioned prior art.

With reference to Fig. 1, we have shown a block diagram illustrating the timing principles of a 2G/3G radio. A timing source 100, such as GPS signal creates an ES (even second) mark 101 synchronized to GPS time, along with an associated (phase-locked) clock 102. It provides these signals to the 2G/3G Data generation equipment 103, which uses them to generate the required codes with an advance with respect to this mark. The amount of this advance is determined by the delay of the radio and the optical fibre - the BaseBand Link 104 to the radio equipment 105.

With reference to Fig. 2, we have shown a block diagram illustrating the timing principles of a 4G radio. In this case, a Radio Equipment Controller (REC) 200 is connected to the Radio Equipment (RE) 201 via a Baseband link 202. The REC likewise has a time alignment requirement, although this is only for (TDD) time division duplex mode. The REC 200 receives a GPS timing reference consisting of a PPS (pulse per second) signal 203 and associated clock 204. These signals are used to generate the framing information for the Baseband link. At the radio side 201, a local timing reference is created. An offset needs to be applied to this timing reference to make it match up with the REC time. To determine this number, the REC measures the delay of the Baseband link. Also, the radio equipment tells the REC what its delay is. The REC then sends a message to the radio to tell it how much to advance it's time base, and where to find the first sample of the downlink (DL) frame in the baseband frame.

With reference to Fig. 3, we have shown a block diagram illustrating a high level topology of a multi - standard base station radio system according to the present invention.

In the embodiment of Fig. 3, the radio system is comprised of a 2G/3G REC 300 which, as an example, may continue to be serviced by a wireless operator wanting to maintain a 2G/3G network but considering expanding its network to include 4G services. The 2G/3G REC continues to receive timing signals from a GPS Time Source 301.

An interface 302, hereinafter referred to as a

multiplexer unit (MU) is provided as an interface that provides the ability to co-locate 4G traffic with 2G/3G traffic on a shared radio 303. As indicated previously, one of the requirements for this configuration is that timing must be consistent between the two networks. Since both networks use separate GPS sources for timing, there is a need for a common synchronization between the 2G/3G REC 300 and the 4G REC 306. The 2G/3G REC generates its timing source on one baseband link 304 whereas the 4G REC makes use another baseband link 305 but both are intended to share a common multi mode radio 303. As described earlier, a problem can exist when the GPS signal or sync of one source is lost or unavailable. Timing signal drift is enough to cause FIFO overflow problems. As will be explained further below, synchronization can be achieved by linking the timing between the 2G/3G REC 300 and the 4G REC 306.

In the preferred embodiments to be described further below, the MU is used to co-locate CDMA traffic with LTE traffic. It will be understood to those knowledgeable in the art that 2G/3G traffic other than CDMA can also be co- located with an LTE or other 4G traffic according to the teachings of the present invention.

The following description makes use of the terms HSSL (High Speed Serial Link) and CPRI (Common Public Radio

Interface) . Both HSSL, a proprietary communications protocol and CPRI define the interface of base stations between the Radio Equipment Controllers (REC) , to local or remote radio units, known as Radio Equipment (RE) and may also be referred to as baseband link in the following description .

With reference to Fig. 4, we have shown a block diagram of the MU 400, which is used as interface between the CDMA REC and LTE REC to synchronize the timing between the baseband units. A GPS source 401 provides an ES (even second) mark synchronized to GPS time to CDMA REC 402.

Similarly, GPS source 401 makes use of a received satellite GPS signal to generate a phase-locked clock signal. An HSSL baseband link 403 is generated using this clock. The VCXO PLL 415 is locked to the CDMA clocking and a IPPS signal is derived from the VCXO, block 413. A 1 PPS signal is output at the rate of 1 pulse per second every 1 second. This reference clock signal is fed to the HSSL PHY 404 to create an HSSL rate 405 with VCXO PLL 415 at the egress side the HSSL PHY. It is also used as the reference clock 416 on the radio side. If there is no consistent timing from the clocking signal of the baseband link 403, the actual rate which would be coming out from the fixed rate re-sampling block 406 could vary and also affect the CPRI rate 407 coming from the CPRI PHY 408 by an amount related to the difference in the timing .

At the LTE equipment side, the GPS source 409, normally connected to the LTE DEC 410 is instead connected to the MU 400, and the MU connects via link 411 to the LTE DEC 410 on the port normally used by GPS source 409 to provide the IPPS and NMEA messages directly.

The MU 400 has the ability to select the incoming pulse it wants to use from one of two possible sources, one from a synthetic PPS recovered from the HSSL baseband link 403 and one from the GPS source 409. As will be explained further below, this selection will depend on the condition of the clock source and the timing difference between the various pulses .

At the LTE DEC 410, a set of NMEA messages 412 is received from the GPS source 409 in addition to the IPPS pulse. This is accomplished by passing the NMEA messages 412 from the GPS source 409 to the LTE DEC 410 via a GPS Emulation block 413. The data in the messages passed through are cached in case the GPS fails in some way and stops sending messages. It should be noted that the system software is responsible for caching the nmea messages which are logically cached in block 413 even though Fig. 4 is more of a hardware block diagram. Even with the GPS source 409 connected to the MU 400, the MU 400 can choose to generate the IPPS to the LTE DEC 410 either from the connected GPS source 409 or using a synthetic IPPS generated from the HSSL baseband link timing 403. Although the HSSL source is preferred over the GPS source (once the phase of the HSSL source is aligned with the GPS) , if the HSSL source 403 fails, the MU will make use of the GPS timing source 409. If the HSSL timing source 403 starts to drift, the CPRI side will drift along with it since one is synchronized with the other .

In the preferred embodiment, HSSL timing 403 is

preferred, as using it allows for consistent timing between the CDMA DEC 402 and LTE DEC 410, even if the CDMA DEC 402 goes into holdover mode and drifts (the LTE DEC 410 will follow the drift) . The selected timing will be output to the radios 414 with the CPRI baseband link that carries the data for both the CDMA and LTE networks .

Notwithstanding the presence of the GPS source 409, a IPPS source at link 411 is generated artificially via a synthetic pulse generated by GPS Emulation block 413. This pulse will be based on the timing signal received from the HSSL links 403. To create the IPPS from the HSSL link, a synthetic IPPS is generated at GPS Emulation block 413 using the PLL 415 that is locked to the HSSL link 403.

The GPS Emulation block 413 provides a set of registers that can be used to measure the phase offset between the IPPS 412 of the GPS source 409 (if available) and the synthetic IPPS. The steady state behavior of the system is to derive the timing from the HSSL link 403. On startup, once the GPS source 409 connected to the MU 400 has initialized, and an HSSL link 403 is available, the system will align the phase of the HSSL-derived synthetic PPS 403 and the GPS PPS 412 and then switch over to use the synthetic PPS for timing. It will continue to do so unless a clock signal failure occurs, in which case a different timing source will be used as will be explained further below.

The recovered clock from the HSSL recovers rate and not phase. In order to recover phase, the synthetic PPS is aligned to the incoming GPS PPS. The synthetic PPS is issued based on a down-counter located in the GPS emulation block 413. This counter is timed from the VCXO that is locked to the incoming HSSL clock rate (415 in Fig. 4) .

The counter counts from 0x79dffff to 0. When the counter reaches 0x3cf0000 the synthetic pps is emitted ("PPS Output Time" ) .

When the gps 1PPS comes in, the value of the down- counter is written to the gps offset register in the GPS emulation block 413. In addition, a 1 is written to the most significant bit, and the previous most significant bit is copied to the second-most significant bit. Using this information, you can determine: a) how far off the synthetic PPS is from the GPS PPS b) if there was a PPS emitted from the GPS in the last 1.5 seconds

To adjust the synthetic PPS, there is an adjustment register that will, for one second only, change the start value of the down-counter from 0x79dffff to a larger or smaller number programmed by the software. A smaller number means the synthetic pps will come out sooner (this is expected if the GPS PPS is being emitted before the

synthetic PPS) , a larger number means it will take longer for the synthetic pps to be emitted (which is expected when the GPS PPS is being emitted after the synthetic pps) . The following steps are then performed: c) wait for PPS signal from GPS. d) before the HSSL link is available, move the synthetic PPS as close to the GPS as possible. Note the HSSL link is not up so the synthetic PPS will wander away. This is attempted 8 times. e) Wait for HSSL link to come up. f) Collect 60 measurements of the offset between the GPS and synthetic PPS pulses g) For each measurement:

i.If the register value is > 0x3cf0000 and the MSB is 0, discard. (this means there was no PPS from the GPS this second)

ii.If the register value is < 0x3cf0000 and the MSB and

SMSB are 0, discard. (this means there was no PPS from the GPS this second) .

iii . Otherwise , add the measurement to a list of measurements until 60 are available. h) Wait for HSSL link to come up.

After 60 measurements are available, discard outliers. Outliers are calculated the standard statistical way (with an exception) :

i) For measurement value M, where Ql and Q3 refer to the first and third quartile:

j ) D = 1.5* (Q3-Q1) , and,

k) If M > Q3+D or M < Ql-D, and M is not less than 7 ticks (about 50 ns) from the median, then M is deemed an outlier and discarded. Recompute mean after discarding outliers and use mean value to determine how far to move the synthetic PPS towards the GPS PPS.

To adjust the PPS:

1) If the computed mean is < 7 ticks (about 50 ns) different from the PPS output time, do nothing - the PPS is lined up and the process is complete. Otherwise:

m) If the computed mean is > PPS output time, reduce PPS counter value by (mean - 0x3cf0000) ticks. If it is < PPS output time, increase PPS counter value by (0x3cf0000 - mean) ticks.

n) If an adjustment was made, collect another 60 samples and repeat, until an adjustment is not required.

With reference to Figs. 5a-5g, we will now describe the timing flows associated with various operational states and how timing synchronization of the CDMA and LTE networks is maintained. The scenarios described are as follows: Fig. 5a, GPS source is initialized; Fig. 5b, HSSL startup; Fig. 5c, holdover timing caused by HSSL link failure; Fig. 5d, LTE REC reset; Fig. 5e LTE REC holdover; Fig. 5f CDMA REC holdover; and Fig. 5g GPS source failure.

For each of the flow diagrams, a number of timing paths will be described and these are described as follows: o) The group of paths, 600 represent clocking signals derived from the CDMA timing portion of the system. These paths feed into the synthetic PPS generation block 601 and into the CPRI clock selection block 602 for timing the CPRI links to the radios (group of paths 603) ; p) Path 605 represent timing signals from the GPS source 606 to the MU 607 on the GPS interface cable (412 Fig. 4) ; q) Path 610 carries the selected timing clock to the LTE REC 611, which is either comprised of the synthetic PPS 604 generated from the CDMA timing on paths 600 or the PPS generated from the GPS source 606 on path 605. The selected timing clock is fed into the LTE REC 611 and is used to train the OCXO 612 of the LTE REC 611; r) The group of paths 615 represent the timing clocks on the CPRI links between the LTE REC 611 and the MU 607; and s) The group of paths 603, represent the timing clocks on the CPRI links to the radios (not shown) . These clock signals are either based on the HSSL link clocking or on the

clocking from the CPRI links coming from the LTE REC 611. When the reference IPPS clock, sent to the LTE REC 611 is generated from the HSSL link (ie. Via paths 600), the timing clocks on paths 603 are also selected as based on HSSL.

When the reference IPPS clock is from the GPS source 606, the timing clocks on paths 603 will be based on the CPRI links (paths 615) from the LTE REC 611.

Referring now to Fig. 5a, we have shown the timing flow after the GPS source 606 has been initialized. In this case, there is no HSSL timing (paths 600) available from the CDMA side of the network. The GPS reference signal 605 is derived from GPS source 606 for the LTE REC 611.

Fig. 5b illustrates the timing flow as the system switches from using the GPS source reference IPPS clock signal 605 to using the HSSL-derived synthetic PPS clock signals 604. This can be thought of as part 2 of the initialization sequence. The initial procedure of switching to the synthetic IPPS 604 is to line up the synthetic IPPS with the reference IPPS clock signal 605 of the GPS source 606. Once this is done, the timing switches to the synthetic IPPS and the CPRI clock selection switches to use the HSSL-derived synthetic PPS clock signals 600 for the timing on the CPRI links 603 to the radios. If during the measurement phase the HSSL links 600 are lost, the

switchover to HSSL for timing is aborted. If the GPS source reference IPPS signal 605 is lost, the switchover to HSSL for timing is aborted also. In this case there will no longer be a IPPS signal going to the LTE REC 611, and the LTE REC 611 will be in holdover. If the LTE REC 611 resets during this switchover process, the switchover is not affected .

Fig. 5c illustrates a failure of the HSSL link 600 and in particular the timing that may occur immediately after, when the LTE REC 611 enters holdover. When the HSSL links fail, the system will switch back to either the GPS source

reference IPPS signal 605 if that signal has not drifted in relation to the lost HSSL signal timing 600, that is, the timing on the CDMA REC links 600 had remained aligned to the GPS source reference IPPS. Otherwise, the LTE REC 611 will enter holdover for a while and base its timing on its OCXO

612. This will continue until its algorithm changes the GPS source reference IPPS signal and begins to accept it.

In both cases the CPRI clock signal 603 will be based on the timing generated from the LTE REC CPRI links 615. Fig. 5d, illustrates the timing when the LTE REC 611 is reset. The reset of the LTE REC does not impact the timing of the HSSL clock signal paths 600 through to the radios. The only difference is that the NMEA messages from the GPS source 606 and the synthetic IPPS 610 sent to the LTE REC 611 do not arrive. When the LTE REC recovers, it will continue on as normal, receiving the IPPS timing from the MU and driving the CPRI link timing for the CPRI links between the LTE REC and MU.

Fig. 5e illustrates the timing flow when the LTE REC goes into holdover. This can occur when the synthetic GPS signal 610 fails at the LTE REC. Another scenario is if the HSSL clock signal 600 has drifted, then failed (as

illustrated in Fig. 6c) and the GPS source reference IPPS signal 610 is rejected thus forcing the LTE REC to go into holdover . If this occurs, the timing from the LTE REC would differ from the HSSL timing being used to drive the HSSL links. This would result in FIFO overflows and the LTE traffic would be shut down.

Fig. 5f illustrates the timing flow when the CDMA REC goes into holdover. This is detectable by monitoring the signal drift with the GPS source reference IPPS signal.

When the CDMA network recovers from holdover, the fault should be cleared - except in the scenario where CDMA was in holdover when the MU switched to HSSL for timing. In that case, the phase of the PPS going to the LTE REC will differ from the GPS signal. The phase will then need to be lined up for the recovered HSSL clock.

Fig. 5g illustrates the situation when the signal from GPS source 606 is lost. Normally, GPS failure while HSSL is being used to drive the timing is not a critical failure - the NMEA messages sent by the GPS source 606 are cached in the MU and continue to be forwarded to the LTE REC. The exception is drift. When there is no reference IPPS signal from the GPS source 606 to compare against, drift on the HSSL timing cannot be detected. This scenario may happen if, say for example, the GPS antenna, being used by the CDMA unit and the GPS source 606 connected to the MU, stops working. The GPS source 606 connected to the MU will stop emitting reference IPPS signal and the CDMA unit will go into holdover.

The present invention can be realized in hardware, or a combination of hardware and software. Any kind of computing system, or other apparatus adapted for carrying out the methods described herein, is suited to perform the functions described herein. A typical combination of hardware and software could be a specialized computer system, e.g., a router, having one or more processing elements and a

computer program stored on a storage medium that, when loaded and executed, controls the computer system such that it carries out the methods described herein. The present invention can also be embedded in a computer program

product, which comprises all the features enabling the implementation of the methods described herein, and which, when loaded in a computing system is able to carry out these methods. Storage medium refers to any volatile or nonvolatile storage device.

Computer program or application in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following a) conversion to another language, code or

notation; b) reproduction in a different material form.

Thus, one embodiment is a computer readable medium containing computer readable instruction that, when executed by a processor, cause the processor to perform functions for maintaining clock synchronization between a first and a second radio.

In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described herein above. A variety of modifications and variations are possible in light of the above teachings without departing from the scope and spirit of the invention, which is limited only by the following claims.