Title:
CLOCK TRANSFER CIRCUIT, VIDEO PROCESSING SYSTEM, AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2013/179349
Kind Code:
A1
Abstract:
A clock transfer circuit receives input data synchronized with a first clock and outputs the received input data as output data synchronized with a second clock having a different frequency. A write address control unit (23) operates in synchronization with the first clock and supplies a write address to a memory (21). A read address control circuit (24) operates in synchronization with the second clock and supplies a read address to the memory (21). A frequency comparator (30) compares the input data with the output data in the frequency of a predetermined event. Based on this comparison result, clock adjustment units (14, 15) adjust the frequency of the second clock.
More Like This:
| JP2016115154 | MASTER DEVICE AND ELECTRIC APPARATUS FOR PERFORMING SYNCHRONOUS SERIAL DATA COMMUNICATION |
| JPS63194442 | DATA TRANSMITTER |
| JPH0276334 | ELASTIC BUFFER CIRCUIT |
Inventors:
NISHIO YUUKI
Application Number:
PCT/JP2012/003596
Publication Date:
December 05, 2013
Filing Date:
May 31, 2012
Export Citation:
Assignee:
PANASONIC CORP (JP)
NISHIO YUUKI
NISHIO YUUKI
International Classes:
H04L7/00
Foreign References:
| JP2002026882A | 2002-01-25 | |||
| JPH02239736A | 1990-09-21 | |||
| JP2003087599A | 2003-03-20 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
Download PDF:
Previous Patent: INDEX GENERATING PROGRAM AND SEARCH PROGRAM
Next Patent: CONTROL METHOD AND CONTROL APPARATUS USING SAME
Next Patent: CONTROL METHOD AND CONTROL APPARATUS USING SAME