Description

Field of the invention

The present application relates to delta-sigma modulators. In particular, the present invention relates to an analogue band-path delta-sigma modulator for use in telecommunications systems.

Background of the invention

Radio communication technology and, in particular, mobile communications technology has been greatly advanced in recent years, as evident by the high performance digital mobile phones currently available.

Base transceiver stations (BTSs) are used in mobile communications technology to establish radio communication links between a mobile station, such as a mobile phone or the like, and a communications network in order to transfer communications data into telephony or other communications networks and vice versa.

A BTS usually comprises a digital radio server and a radio unit situated in a base station and antenna elements placed on a tower top equipment. A novel all digital antenna array system is described in the commonly assigned patent applications PCT/EP2007/006335 and US 60/807,512, the teachings of which are incorporated herewith by reference. The PCT/EP2007/006335 describes a radio unit that can be integrated with the antenna elements in the tower top equipment. The patent application teaches a digital transceiver that is, in sending direction, coupled via a power digital-to-analog converter (DAC) and an analogue filter element connected to an antenna dipole. In one mode, the array system is generating a signal in a three level 1.5 bit data format at 4:3 carrier frequency f _R p. The 1.5 bit data format is applied to a power amplifier for driving an antenna dipole.

State of the art delta-sigma modulators comprise an integrator (in case of a low-pass modulator) or a resonator (in case of a band-path modulator), a quantizer and a feedback loop. The feedback loop usually feeds back the output signal of the quantizer into the integrator or resonator.

A comparator is usually applied as a quantizer for quantizing the output signal from the integrator or resonator.

The quantizer is, however, clocked by an external clock signal, for example a square wave signal and compares the integrator output signal to a reference signal at time intervals determined by the clock signal. As the quantizer is clocked or triggered by the reference signal, the quantizer output signal is clocked as well. Therefore at least all subsequent electronic elements to which the quantizer output signal is applied have to be synchronous to the same reference signal.

Applying the 1.5 bit data format can increase the data throughput at a given external clock signal frequency. However, the signal-to-noise ratio and the output power is reduced.

State of the art quantizers that are triggered by external clock signals are limited by their quantizer noise and low signal output power and thus provide only a moderate signal-to-noise ratio and efficiency.

Summary of the invention

It is an object of the present invention to provide an improved delta-sigma modulator.

These and other objects of the invention are solved by an analogue band-pass delta-sigma modulator comprising a quantizer with a quantizer input and a quantizer output, a first resonator providing a first resonator output signal connected to the quantizer input, and at least one feedback loop, wherein the asynchronous quantizer is triggered by the output signal of the resonator. The asynchronous quantizer is a clock-less quantizer that is triggered by the signal to be quantized. In the delta-sigma modulator of the invention, no external clock-signal is applied to the asynchronous quantizer. The feedback loop may feed at least an output signal of the analogue band-pass delta-sigma modulator to an input of the analogue band-pass delta-

sigma modulator. The output signal of the analogue band-pass delta-sigma modulator may thus be fed to the first resonator and alternatively or additionally, to a further resonator.

The asynchronous quantizer allows the delta-sigma modulator to provide a higher output power and higher efficiency than prior art delta-sigma modulators. Moreover, no symmetry requirements are necessary for a power digital-to-analogue converter (DAC) or a filter employed at the output of the delta-sigma modulator.

The delta-sigma modulator input signal may be a radio frequency signal or a mobile telecommunications signal.

The delta-sigma modulator may be used in the field of mobile communications in a digital radio unit of a base transceiver station. The delta-sigma modulator may be used for modulating the output signal of a digital up converter (DUC). The delta-sigma modulator may be used in transmitting direction.

The delta-sigma modulator may be a continuous time delta-sigma modulator.

The delta-sigma modulator may further comprise a power amplifier (PA). The power amplifier can be a switched mode power amplifier. In this case, the analogue band-pass delta- sigma modulator may be arranged directly in front of a filter or an antenna dipole (in sending direction). No additional DAC is required.

The power amplifier may comprise an H-Bridge for controlling the voltage applied to an antenna dipole. The power amplifier may also comprise a half-bridge.

The power amplifier may also be a transistor amplifier comprising at least one transistor operating in a non-linear domain. In this case the power amplifier is designed such that at least one transistor operates in a non-linear operating region of its signal transduction curve. The transistor may thus act as a switch. More than one transistor may be employed in the power amplifier.

The resonator is used as band-pass filter of the signal. A plurality of resonators may be arranged in series. Two or three resonators may give the best signal to noise ratio but the

invention is not limited by the number of resonators used. The output signal of the last resonator of the series of resonators is applied to the asynchronous quantizer.

The feedback loop may be connected to the input of any one, to several or to all of the plurality of resonator inputs.

The feedback loop may be connected to the output of the quantizer. Thus, the output signal of the quantizer may be fed back into the one resonator. In case a plurality of resonators is used in series, the feedback loop may be branched off and connected to the input of each ones of the resonators.

The feedback loop may also be connected to the output of the power amplifier. Thus, the output signal of the power amplifier may be fed back into the resonator. Using the output signal of the power amplifier provides the advantage that non-linearities of the power amplifier, such as memory effects or the like may be eliminated.

A plurality of feedback-loops may also be employed in some embodiments. For example, a first feedback-loop may be connected to the output of the quantizer and fed back to a second resonator, while a second feedback loop is connected to the output of the power amplifier for feeding back the output signal of the power amplifier into a first resonator. Other combinations for feedback loops are obvious to person skilled in the art.

An example of a prior art method and apparatus for a signal processor is disclosed in international patent application No. WO99/05806 (assigned to Tripath Technology, Santa Clara, CA, USA). This patent application describes a signal processor having at least one integrator stage in a loop. A sampling stage is connected to the at least one integrator stage. The sample stage samples an unlock signal at a sample frequency. A qualification logic is coupled to the sampling stage and receives a pulse waveform from the qualification logic and ensures that signal transitions in the pulse waveform occur more than a first time period apart and that the pulse waveform can therefore be handled by, for example, a power switching device. A switching stage in the loop is coupled to the qualification logic. The signal processor has a feedback path from the output of the switching stage to the input of the at least one integrator stage, thereby closing the loop.

The teachings of this document also cover a computer program product comprising instructions that are enable a processor to carry up a method, as described above.

These and other aspects of the invention will be apparent from and elucidated with effects to the embodiments hereinafter.

The analogue band-pass delta-sigma modulator may further comprise one or more signal delay elements. A signal delay element may be an electronic component delaying the signal by a predetermined time or until the signal passes a certain level, such as zero crossing.

A signal delay element may be arranged after the power amplifier for delaying the output signal of the power amplifier and eventually of the feedback signal. A signal delay element may also be arranged in the feedback loop for delaying only the feedback signal.

The asynchronous quantizer may be a monoflop or monostable mulitvibrator circuit. Thus, the delta-sigma modulator may output a high level signal for a period of time after the monoflop input signal has passed a threshold value. The threshold value may be predetermined and can be a positive value. Thus, a pulse is generated at the output for a predetermined duration of time when a signal to be quantized exceeds the predetermined threshold. A pulse may also be generated when the signal falls below the predetermined threshold or a further threshold. The further threshold can be a negative value. The period of time may be a predetermined fixed period or may be adjustable. The predetermined period may be adjusted or triggered by a signal edge, such as a further zero crossing.

The asynchronous quantizer may be a hysteresis comparator such as for example a Schmitt- Trigger. In this case, the quantizer has two thresholds and two stable output states, if the signal exceeds a first threshold, the output will switch to the first output state. The output signal will stay at the first output stage until an input signal falls below a second threshold. At this point, the output will switch to a second output stage. As long as the input signal stays between the two thresholds, an output signal remains on the current output stage and does not change.

The asynchronous quantizer may also be a signal comparator, comparing the input signal to a predetermined reference signal level. The comparator will switch to the first stage, when the

signal is above the reference signal level, and will switch to the second stage, when the signal is below the reference signal level.

The first and the second output signal level may be for example 1 and 0 or, 1 and -1, respectively. The asynchronous quantizer according to the invention provides two output stages or signal levels. Therefore, the height or amplitude of every pulse can be maximized.

Using two monoflops in the quantizer with a predetermined threshold for a first monoflop and a further threshold for a second monoflop allows for three output stages and thus to obtain a 1.5 bit output signal. For example, if the quantizer input signal exceeds the predetermined threshold of the first monoflop, the output signal level may be +1, if the quantizer input signal falls below the further threshold of the second monoflop, the output signal level may be -1, and if none of the predetermined and the further threshold are passed by the quantizer input signal, the output signal may be 0.

The invention also relates to a method for analogue delta- sigma modulation comprising: receiving a delta-sigma modulation input signal; determining a first resonator input signal from the delta-sigma modulation input signal and a feedback signal; applying the first resonator input signal to a first resonator to obtain a first resonator output signal; quantizing the first resonator output signal to produce a quantizer output; using at least an output signal of the delta-sigma modulation for the feedback signal, wherein the quantizing is asynchronous, i.e. triggered by its own input signal such as the first resonator output signal.

Determining the first resonator input signal form the delta-sigma modulation input signal can comprise further signal treatment prior to of the resonator input signal prior to determining. The first resonator input signal may be determined by building a difference signal from the delta-sigma modulation input signal and the feedback signal.

The delta-sigma modulation input signal may be a radio frequency signal.

The method for analogue delta-sigma modulation may further comprise amplifying the quantizer output to produce an amplified signal. Amplifying my be performed by a switched mode amplifier.

The method for analogue delta-sigma modulation may further comprise applying the delta- sigma modulation input signal to at least a second resonator prior to application to determining the first resonator input signal. The method may also comprise determining at least a second resonator input signal from the delta-sigma modulation input signal and applying the at least second resonator input signal to the at least second resonator.

Further resonators may be used. Each resonator input signal can be determined as the difference signal from the feedback signal and the modified or non-modified delta-sigma modulation input signal.

The quantizing may be performed by outputting a pulse for a predetermined duration of time when a signal to be quantized exceeds a predetermined threshold.

The quantizing may comprise comparing a signal to be quantized to at least two threshold by means of a hysteresis.

The method may further comprise delaying one of the signals. The delayed signal may be the feedback signal or the first resonator output signal, or the quantized signal, or any other signal that is present in the sigma-delta modulation.

Description of the drawings

The features of the present invention may be better understood when reading the detailed description and the figures, wherein identical numbers identify identical or similar objects and wherein:

Fig. 1 shows base station configurations according to prior art and comprising all-digital antenna system;

Fig. 2a to 2c show different configurations of the all-digital antenna system to which the present invention may be applied;

Fig. 3a shows in detail the components of a digital radio unit for FDD radio links according to prior art;

Figs. 3b and 3c show two ways of employing a delta- sigma modulator according to the present invention with the digital radio unit of Fig. 3a;

Fig. 4a shows a prior art example how radio frequency signals are generated, Fig 4b shows how the present invention may applied in the prior art example of Fig. 4a, and Fig. 4c shows another application of the present invention.

Figs. 5a and 5b show a delta-sigma modulator according to the invention with a feedback loop connected to the output of a quantizer and a power-amplifier, respectively.

Figs. 6a and 6b show time domain signals of a delta-sigma modulator input signal, a quantizer input signal, and a quantizer output signal for a monoflop quantizer and a hysteresis comparator as quantizer, respectively.

Fig. 7 shows a simulated output spectrum of the clockless delta-sigma modulator.

Detailed description of the invention

Fig. 1 shows three different configurations of base transceiver stations (BTS) 100 that may be used in mobile communications networks. A mobile station 2 can communicate via radio links with any one of the BTS 100. A mobile station 2 is any mobile or immobile communication device that enables communication via radio links, usually at radio frequencies (RF) in the range of 800 MHz up to several GHz. Common examples for mobile stations are, but are not limited to, mobile telephones, pocket PCs, data cards etc.

The BTS 100 may be further connected to a telephony network via a mobile services switching centre or to a data network such as the Internet.

All of the BTS 100 comprise tower- top equipment 102 that is usually mounted in an elevated position, such as on tower tops, roof tops or top of masts, in order to maximize a coverage area of the BTS 100. The tower- top equipment 102 is connected to a base station 104 that may be in a housing beside or at some distance from the tower-top equipment 102.

In a first configuration (A) known in the art, a set of antennas or antenna elements 120 for receiving and sending radio signals from and to the mobile station 2 is linked with a coaxial cable 122 to a collocated radio unit 124. An analogue RF signal is received at the set of antennas or antenna elements 120 and passed to the collocated radio unit 124. In the collocated radio unit 124, the analogue radio RF signal is amplified, separated from a carrier frequency and converted into a digital signal. The digital signal is then further transferred to a digital radio server 128 from which the digital signal is passed on to a base station controller BSC (not shown) or vice versa. The length of the coaxial cable 122 affects the signal-to-noise ratios and the efficiency of the BTS 100 as well as the electrical power consumed.

As discussed above, the tower-top equipment 102 is, in many cases, located in elevated positions. The length of the coaxial cable 122 may therefore become inefficiently long.

In a second configuration (B), a remote radio unit 134 is mounted at the tower top equipment 102. In this manner a shorter coaxial cable 132 can be used to connect the antennas or antenna elements 130 to the remote radio unit 134. The remote radio unit 134 converts modulated RF signals to communications signals in digital data format according to the CPRI or OBSAI standard. The communications signals are then transferred via optical fibres 136 to a digital radio server 138 that may be essentially identical or similar to digital radio server 128.

In configurations (A) and (B), the plurality of antenna elements form an antenna 120; 130 that is connected via one coaxial cable 122; 132 to the single radio unit 124; 134. The radio unit 124; 134 must then separate the modulated RF signals received from the plurality of antenna elements in order to separate different communications links handled in parallel.

In a third configuration (C), a digital radio unit 200 is directly connected to the plurality of antenna elements 220 forming the antenna. Each one of the antenna elements 220 is thereby directly connected to the digital radio unit 200 or its components. In this embodiment no coaxial cable is required in order to couple the digital radio unit 200 to the antenna elements

220. The digital radio unit 200 converts the modulated RF signals received and transmitted via the antenna elements 220 from/to the mobile station 2 into the communications signals according to CPRI or OBSAI standard/interface. These communications signals are then transferred via optical fibres 206 to a digital radio server 208 located at base station 104. The optical fibre 206 may thereby be up to 40 km long enabling the remote location of the base station 104 with respect to the tower-top equipment 102.

The digital radio servers 128; 138; 208 may thereby be of the same type in all configurations (A), (B), and (C).

A delta-sigma modulator of the present invention is used with the digital radio unit 200 of configuration (C). The principle of the digital radio unit 200 is described in more detail in the co-pending patent application PCT/EP2007/006335, the teachings of which are incorporated herewith by reference.

Figs. 2a to 2c show different embodiments of the digital radio units 200. The digital radio unit 200 comprises at least one antenna element 220, at least one micro radio 230, and at least one C-hub 240.

In the embodiment shown in Fig. 2a, the digital radio unit 200 comprises a single antenna element 220 directly connected to one micro radio 230 and one C-hub 240. The micro radio 230 communicates with the C-hub 240 in a receiving and sending direction for example via a bi-directional serial interface between micro radio 230 and the C-hub 240 as described in detail in the commonly assigned patent applications PCT/EP2007/006335 and US 60/807,512,..

A plurality of the embodiments of Fig. 2a may be arranged and coupled in an array.

In the embodiment shown in Fig. 2b, the C-hub 240 is connected to two of the micro radios 230. Each of the micro radios 230 communicates in a sending and receiving direction with the C-hub 240. Further, each one of the micro radios 230 is connected to two of the antenna elements 220 via a so-called Wilkinson splitter 225, as is known in the art.

Fig. 2c shows another embodiment of the present invention. In this embodiment a plurality of the micro radios 230 is connected to a single one of the C-hub 240, whereby each of the micro radios 230 communicates in a sending and receiving direction with the C-hub 240. Sixteen micro radios 230 are shown in Fig. 2c but this is not limiting of the invention. In this example, each one of the micro radios 230 is connected to a single one of the antenna elements 220. Several ones of the C-hubs 240 each with eight micro radios 230 and eight antenna elements 240 may be linked together to form arrays of sixteen or more antenna elements 220.

It will be obvious to a person skilled in the art that the embodiments shown are examples only and that any number of the micro radios 230 may be connected to the C-hub 240. It is also obvious to a person skilled in the art that the number of antenna elements 220 per micro radio 230 can vary according to the needs of a particular application. In addition, a plurality of the C-hubs 240 can be coupled together (as is shown in Fig. 2c which includes two of the C-hubs 240).

Fig. 3a shows in greater detail the micro radio 230 and the C-hub 240 connected via a digital bi-directionally serial link 260 forming together the digital radio unit 200. The antenna element 220 is directly connected to the micro radio 230. The antenna element 220 may, for example, be mounted on an antenna board or another printed circuit board onto which the micro radio 230 is arranged or attached. In an alternative embodiment, the micro radio 230 may be realized directly on the printed circuit board.

The micro radio 230 shown in Fig. 3a is operated in Frequency Division Duplex (FDD) mode, thus comprising a FDD filter unit 232 at its antenna element entry which separates the modulated RF signals in an uplink direction and a downlink direction by utilizing a combination of two band-pass filters embedded in the filter unit 232.

In the uplink or receiving direction, the RF signal received via the antenna element 220 and filtered by the FDD filter unit 232 is converted into a digital band-pass signal R ₈ by the low- noise analogue-to-digital converter (ADC) 235. The ADC 235 and the digital down converter DDC 350 are clocked by a receive clock oscillator (RCLK) 237. The digital band-pass signal R ₈ is down converted into a digital base-band signal by the digital down converter (DDC) 350 integrated in a digital transceiver (DTRX) 300. The DTRX 300 is arranged at the digital port

of the micro-radio 230 from where the digital base-band signal is transferred to the C-hub 240.

The ADC 235 comprises a low-noise amplifier followed by a continuous-time delta-sigma band-pass modulator, both of which are known in the art. The continuous-time delta-sigma band-pass modulator converts the incoming RF signal into the digital band-pass signal Rs by utilizing a two or three level quantizer at a sample rate being 4 or 4/3 times the RF carrier frequency. Thus, the digital band-pass signal R ₈ comprises the representative levels +1, -1 or

+1, 0, -1 coded respectively by one or two bits. This digital signal format is termed as 'single/1.5bit' or 'bi-serial' in contrast to a 'multi-bit' format comprising more than 3 representative levels.

In the downlink or sending direction, the digital base-band signal Rs received from the C-hub 240 is input into the DTRX 300 of the micro-radio 230 where the digital base-band signal Rs is up-converted into a digital band-pass signal I _DL by a digital up-converter (DUC) 310. The digital band-pass signal I _DL is then transferred to a power digital-to-analog converter (PDAC) 234 where the digital band-pass signal I _DL is converted into the RF signal. The PDAC 234 and the DUC 310 are clocked by the transmit clock oscillator (TCLK) 236 at a sample rate being 4 or 4/3 times the RF carrier frequency. The RF signal is then passed through the FDD filter unit 232 and radiated via the antenna element 220. A separate power amplifier normally used in RF transmitters is not necessary because the power digital-to-analog converter (PDAC) 234 provides a sufficiently high-powered RF signal to be radiated via the antenna element 220.

Alternatively, the micro radio 230 may be operated in TDD mode. In TDD mode, a TDD filter unit is connected to the antenna element 220 and followed by a TDD switch which separates the RF signals in the uplink and downlink direction within the time domain. A micro radio 230 operated in TDD mode is shown in the commonly assigned patent applications PCT/EP2007/006335 and US 60/807,512.

The digital up-converter (DUC) 310 contains one time-discrete delta-sigma band-pass modulator or alternatively two time-discrete delta-sigma low-pass modulators. In both cases, the time-discrete delta-sigma band-pass modulator or the two time-discrete delta-sigma low- pass modulators perform coarse quantization by use of two or three levels only providing a single/1.5bit signal at the output. Thus, the digital band-pass signal I _DL being generated by the

digital up-converter (DUC) 310 only comprises the representative levels +1, -1 or +1, 0, -1 being respectively coded by one or two bits. Therefore, the power digital-to-analog converter (PDAC) 234 utilizes only two or three voltage levels, respectively, to represent the digital band-pass signal I _DL in the analog domain.

The transmit clock oscillator (TCLK) unit 236 and the receive clock oscillator (RCLK) unit 237 each comprise a voltage controlled oscillator (VCO) embedded in a phase-locked loop (PLL) used for synchronization purposes. Clock oscillators utilizing a VCO plus PLL are known in the art and standard components or architectures may be used.

It should be noted here that those embodiments of the invention where the samples of signals I _DL and R ₈ are represented in the two-level format can be interpreted as a special case of the embodiments of the invention utilizing the three-level format to represent the samples of signals I _DL and Rs. In both cases, two's complement arithmetic is applied. In case of the major embodiments, the representative levels +1, 0, -1 are coded by two bits where the upper bit denotes the sign-bit whilst the lower bit denotes the zero-bit being cleared (low state) when a zero-sample occurs. Thus, the major embodiments of the invention can be operated also in a special mode using the two-level format by keeping the zero-bit always at high state (nonzero).

The micro-radio 230 is connected to the C-hub 240 via a bi-directional serial link 260.

In low-cost CMOS technologies, the serialiser/deserialiser supports symbol rates up to 2.5 Giga Baud representing a gross data rate of 2.0 Giga bits per second equivalent to 250 Mega bytes per second due to code rate 0.8 of the 8B/10B channel code.

The C-hub 240 as shown in Fig. 3a comprises an amplitude and phase aligner (APA) 241 including a frame buffer and a serializer/de-serializer. The APA 241 has N ports for connecting N micro-radios 230, 231. The plurality of micro-radios 230, 231 is connected to one of the C-Hubs 240 as described with respect to Fig. 2c. In total N of the micro radios 230, 231 may be each connected to one of the ports of the N-port phase aligner 241 and the signals received and transmitted from each one of the micro radios 230, 231 are treated in parallel and/or series by the subsequent components of C-Hub 240. The additional first and next

micro-radios 231 may be identical to micro-radio 230 and are shown in greater detail in Fig. 3b.

The C-hub 240 comprises as further components a sample rate converter (SRC) 242 for adjusting the sampling frequency of the complex base-band signal to the RF carrier frequency, a frequency multiplexer/de-multiplexer (FMDX) 243, a unit 244 comprising time multiplexer/de-multiplexers (TMDX) around a hub and finally a master serializer/deserializer (SerDes) 249 plus one or more serializers/deserializers (SerDes) 248.

The TMDX and hub unit 244 performs packet data handling and distribution of data streams in the CPRI and/or OBSAI. Only those data packets which are dedicated to be received and transmitted by the connected micro-radios 230, 231 are handed over from/to the FMDX unit 243 for further processing.

The frequency multiplexer/de-multiplexer (FMDX) unit 243 comprises several digital modulators and de-modulators for simultaneously up and down converting a variety of baseband signals to/from their respective sub-carrier frequencies. The modulated RF signals can be easily combined in the frequency domain by use of a simple adder stage, thus enabling multi- carrier operation.

All of the components of the C-hub 240 are controlled by a micro-controller (μCTRL) 245 to which the components are connected via a control bus 247 and clocked by a master clock oscillator (MCLK) 246. The master clock oscillator 246 comprises a voltage controlled oscillator (VCO) embedded in a phase-locked loop (PLL) used for synchronization purposes. The master clock oscillator 246 must be synchronized to the clock frequency of a CPRI and/or OBSAI transport signal derived by the clock recovery unit within the master serializer/de-serializer (SerDes) 249. The master clock oscillator (MCLK) 246 also synchronizes the transmit clock oscillator 236 and the receive clock oscillator 237 of the micro radios 230,231.

All of the components of the C-hub 240 are commercially available components known to a person skilled in the art.

A small form-factor module (SFF) 250 comprising one or more electro-optical converters (E/O) 258 and 259 are respectively connected to the Serialiser/Deserialisers 248 and 249. The electro-optical converters 258, 259 are known in the art and are applied to convert the digital electrical signal of the Serialiser/Deserialisers 248 and 249 into an optical signal that can be transferred with known standards such as CPRI (common public radio IF) or OBSAI, i.e. via the optical fibres 136 to the digital radio server as shown in Fig. 1.

Figs. 3b and 3c show two application examples of the invention employing a delta-sigma modulator according to the present invention within the digital radio unit 200 of Fig. 3a. The C-hub 240 is not shown in detail but may be identical to that shown in Fig. 3a. It is obvious to a person skilled in the art that the delta-sigma modulator can also be used with any radio unit as shown in Figs 1 and 2 or with any other switched mode amplifier.

A delta-sigma modulator 400 may be inserted between the DUC 310 and the PDAC 234 as shown in Fig 4a. The output signal I _DL of the DUC 310 is applied to an input of the delta- sigma modulator 400. The delta-sigma modulator 400 may transform the 1.5 bit I _DL signal into a single bit signal at the output of the delta-sigma modulator 400. The single bit signal may then be applied to the PDAC 234. The other components of the micro-radio 230 may remain unchanged.

The delta-sigma modulator 400 of Fig. 3b is clock-less. No clock signal from the transmit clock oscillator (TCLK) unit 236 or the receive clock oscillator (RCLK) unit 237 is applied to the delta-sigma modulator 400. As the output signal of the delta-sigma modulator 400 is asynchronous, the PDAC 234 may not be clocked by the TCLK unit 236.

The PDAC 234 may also be integrated in a power amplifier integrated delta-sigma modulator 500 as shown in Fig. 3c. In this case, the output signal I _DL of the DUC 310 is applied to the power amplifier integrated delta-sigma modulator 500 and the output signal is directly applied to the FDD-filter unit 232 or the antenna element 220. In this case the power amplifier integrated delta-sigma modulator 500 is also clock-less. No clock signal is applied to the power amplifier integrated delta-sigma modulator 500.

Fig. 4a shows a prior art example how radio frequency signals are generated. I and Q signals are transmitted separately from a C-Hub 240, for example as described above with respect to

Fig 3a. The I-signal and the Q-signal are converted by two 14 bit digital-to-analog converters 371 and 372, respectively, and modulated to one signal in an IQ modulator 375, as known in the art. In a simple application, the IQ modulated signal may be directly applied to a linear power amplifier and to an antenna element (not shown). In the application shown in Fig 4a, the IQ modulated signal is applied as a radio frequency input signal RFin to a clocked delta- sigma modulator 390. The clocked delta-sigma modulator 390 may be a continuous time bandpath modulator as known in the art. The clocked delta-sigma modulator 390 is clocked by and external clock signal 391. The output signal of the delta-sigma modulator 390 is applied to a switched power amplifier 394, to a bandpath filter 396 and further passed to a duplex filter and the antenna element (not shown).

Fig. 4b shows how the present invention may be used for generating a radio frequency signal. Using the example shown of Fig 4a, the clocked sigma-delta modulator 390 is, according to the invention, replaced by a clockless sigma-delta modulator 500. The RF input signal RFin is thus applied to the sigma-delta modulator 500 described in detail below. A power amplifier 540 is attached to the sigma-delta modulator 500. In the example shown the power amplifier output signal is fed back via a feedback loop 550 to the sigma-delta modulator 500. As will we be shown with respect to Figs. 5a and 5b, there are several possibilities for arranging the feedback loop 450, 550 with respect to the power amplifier 440, 540 and the sigma-delta modulator 400, 500.

Fig. 4c shows another application of the sigma-delta modulator 500 with the power amplifier 540. In this case, the RF input signal RFin is provided by a digital delta-sigma modulator 380 combined with a 1.5 bit digital-to-analog converter 381 both known in the art.

Fig. 5a shows a delta-sigma modulator 400 according to the invention. The delta-sigma modulator comprises a quantizer 410 with a quantizer input signal 41 and a quantizer output signal 42. The quantizer 410 may comprise a monoflop, two monoflops, a normal comparator, or a hysteresis comparator such as a Schmitt-trigger.

An input of the quantizer 410 is connected to a first resonator 422 for band-pass filtering or band-pass integrating the quantizer input signal.

A feedback loop 450 is connected to the output of the quantizer 410 and feeds the quantizer output signal back to the first resonator 422.

A second resonator 424 may be provided for more efficient band-pass filtering, better noise shaping and consequently better a signal-to-noise ratio (SNR) and a better dynamic range. The second resonator 424 is arranged before the first resonator 422. The feedback loop may be branched and the quantizer output signal 42 is also fed to the second resonator 424 as illustrated in Fig 5a.

The feedback loop may further comprise a delay element 430 for timely delaying the quantizer output signal fed back to the first resonator 422 and the second resonator 424. The delay element 430 may also be arranged at the output 42 of the quantizer 410 (not shown).

The delta-sigma modulator may further comprise transconductance stages (GM) in the feedback loop 462, 464 and before 465 or in between 463 the first resonator 422 and the second resonator 424. One or more passive resistors may be used as a GM 462, 463, 464, 365.

The output signal of the quantizer 410 may be further applied to a power amplifier 440. The power amplifier 440 can be a switched mode power amplifier. The delta-sigma modulator including the power amplifier 440 may be used as power amplifier integrated delta-sigma modulator 500 as illustrated in Fig. 5b. The power amplifier 440 may also be additionally applied and the delta-sigma modulator including the power amplifier 440 may be used as delta-sigma modulator 234 illustrated in Fig. 3b.

Fig. 5b shows a delta-sigma modulator with a power amplifier 540 integrated inside the feedback loop 550. The power amplifier 540 can be a switched mode power amplifier. The output signal of a quantizer 510 is applied to the power amplifier 540. The output signal of the power amplifier 540 is then fed back via a GM 562 to a first resonator 522 and via a GM 564 a second resonator 524.

The first resonator 522 and the second resonator 524 are used for band-pass filtering the signal applied to the quantizer 510, as discussed above. The power amplifier 540 may also serve as a delay element. The delay of the power amplifier 540 (or power amplifier chain

including driver stages) may vary over temperatures and supply voltage and may vary between samples due to fabrication tolerances.

A delay element 530 may be optionally provided, for example between the quantizer 510 and the power amplifier 540 as shown in Fig. 5b. The delay time of the delay element 530 may be adjustable or programmable as known in the art. The delay element 530 may also be provided within the feedback loop 550.

The delay element 530 might be tuned or adjusted to compensate for the variations of the delay of the power amplifier 540 in order to keep the overall delay fixed. To this end, a phase detector 531 is provided having two inputs and one output. A first input 55 of phase detector

531 is connected to the feedback loop 550, for example and as shown in Fig. 5b before the

GM 562 such that the signal at the first input 55 corresponds to the input signal of GM. The first input 55 of phase detector 531 may also be connected to the output of the GM 562. However, a second input of phase detector 531 is connected to the output of the first resonator

522 and corresponds thus to the quantizer input signal 51. The output 53 of the phase detector

531 is connected to a control input of the delay element 530. The phase detector 531 compares the average phase of its two input signals. Depending on the detected phase difference, the delay of delay element 530 is increased or reduced. Providing the delay element 530 between the quantizer 510 and the power amplifier 540 as shown in Fig. 5b has the advantage that the signal is digital and thus has discrete values. Therefore, the signal can be easily delayed at this stage.

It is important that the feedback is applied to the first resonator 422, 522 and/or to the second resonator (424, 524) with the correct phase and delay with respect to the signals in the respective resonators.

Furthermore, a calibration might be implemented to automatically calibrate and/or adjust the delay of the delay element 530 either on power up or permanently during operation.

The power amplifier 440 illustrated in Fig 5a and the power amplifier illustrated 540 in Fig. 5b may be a single ended class-D or class-S power amplifier. The power amplifiers 440 and 540 may also be an H-bridge or a half bridge. The delta-sigma modulator of the invention can thus be used as a driver for the power amplifiers 440 and 540 or the power DAC 234 of Fig 3.

The RF input signal (RF in) may be applied to the delta- sigma modulator 400 or the power amplifier integrated delta-sigma modulator 500. The RF input signal (RF in) may be provided by the DUC 310 described with respect to Fig 3. The DUC 310 can output a high speed single bit or 1.5 bit data format at a frequency of multiple 4:3 of the carrier frequency f _R p. The clockless delta-sigma modulator 400 or the clockless power amplifier integrated delta-sigma modulator 500 may transform the RF input signal (RF in) to a single bit or 1.5 bit data format.

A single bit data format has the advantage of having only two output states. Thus, the height or amplitude of every pulse can be doubled compared to the 1.5 bit data format leading to a four-fold higher signal output power, and consequently to a higher efficiency. However, if a 1.5 bit quantizer is used that is capable of delivering twice as many pulses per time interval, such as a quantizer consisting of two monoflops, a power amplifier driven by a 1.5 bit quantizer can achieve the same output power and efficiency.

The phase of the output pulses can be controlled by the feedback loop in order to fit to the desired RF output signal. Using the clockless quantizer 410, 510, the pulses are no longer limited to 90° phase steps. Therefore, output pulses are better aligned and in phase with the desired RF output signal (RFout) leading to higher output power and to higher efficiency.

The clockless quantizer 410, 510 may be a monoflop quantizer, comprising one monoflop, or two or more monoflops. The clockless quantizer 410, 510 may also be a normal comparator or a hysteresis quantizer such a Schmitt trigger.

Fig. 6a shows a simulation of time domain signals of a delta-sigma modulator input signal Rfin, a quantizer input signal 41, and a quantizer output signal 42 for the monoflop quantizer. The monoflop quantizer has a predetermined threshold value. This is shown in the example of Fig. 6 to be equal to 1.0. When the quantizer input signal exceeds this predetermined threshold value, a pulse with a predetermined length is generated as the quantizer output signal 42 as shown in Fig. 6a. After the pulse is elapsed the quantizer output signal goes back to the idle state "0" until the quantizer input signal exceeds the predetermined threshold value for the next time.

The predetermined length of the pulse in the time domain may be adjusted once and kept constant or may be adjustable. The length of the pulse may also be triggered by external signal or by the edges or zero crossings of the quantizer input signal.

Fig. 6a shows a simulation of time domain signals of the delta-sigma modulator input signal Rf in, the quantizer input signal 41, and the quantizer output signal 42 for the hysteresis comparator as quantizer.

Turning to Fig. 6b, the hysteresis comparator has two threshold values, a first threshold value and a second threshold value. If the quantizer input signal exceeds a first threshold value, in the example shown +1.0, the quantizer output signal will switch to the first output state, in the example shown "+1.0". The quantizer output signal will stay at the first output state until the quantizer input signal falls below the second threshold value, "-1.0" in the example. At this point, the quantizer will switch the quantizer output signal to a second output state, in this example "0". While various embodiments of the present teachings have been described above, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant arts that various changes in form and detail can be made therein without departing from the scope of the invention. For example, in addition to using hardware (e.g., within or coupled to a Central Processing Unit ("CPU"), microprocessor, microcontroller, digital signal processor, processor core, System on Chip ("SOC"), or any other device), implementations may also be embodied in software (e.g., computer readable code, program code, and/or instructions disposed in any form, such as source, object or machine language) disposed, for example, in a computer usable (e.g., readable) medium configured to store the software. Such software can enable, for example, the function, fabrication, modelling, simulation, description and/or testing of the apparatus and methods described herein. For example, this can be accomplished through the use of general programming languages (e.g., C, C++), hardware description languages (HDL) including Verilog HDL, VHDL, and so on, or other available programs. Such software can be disposed in any known computer usable medium such as semiconductor, magnetic disk, or optical disc (e.g., CD-ROM, DVD-ROM, etc.). The software can also be disposed as a computer data signal embodied in a computer usable (e.g., readable) transmission medium (e.g., carrier wave or any other medium including digital, optical, or analog-based medium). Embodiments of the teachings within this document may include methods of providing the apparatus described herein by providing software describing the apparatus and subsequently

transmitting the software as a computer data signal over a communication network including the Internet and intranets.

It is understood that the apparatus and method described herein may be included in a semiconductor intellectual property core, such as a microprocessor core (e.g., embodied in

HDL) and transformed to hardware in the production of integrated circuits. Additionally, the apparatus and methods described herein may be embodied as a combination of hardware and software. Thus, the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

A standard comparator as known in the art may also be used.

Fig. 7 shows a simulated output spectrum of the clockless delta-sigma modulator in the frequency domain with a four carrier input test signal applied to the RF input. The simulation does not contain a power amplifier. It can be seen that the signal-to-intermodulation ratio or adjacent channel power ratio (ACPR) of the four test channels at a frequency of 1.990, 1,995, 2,000 and 2,005 GHz is approximately 45dB.

The signal-to-noise ratio and the efficiency may be further improved or adjusted by modifying the type and number of resonators. Further methods to improve the signal-to-noise ratio, the signal-to-intermodulation ration are known to a person skilled in the art and include zero spreading (tuning individual resonators to slightly different resonance frequencies), active Q enhancement (negative gm circuits to compensate for finite Q of resonators), and tuning the interstage gain (gm) between resonator stages.

It should be understood that the foregoing relates to exemplary embodiments of the invention and that modifications may be made without departing from the spirit and scope of the invention as set forth in the following claims.