FIELD OF THE INVENTION

[0001] The present invention relates generally to semiconductor manufacturing processes, and more particularly to processes of forming an integrated circuit structure including a piezoelectric device and a complementary metal oxide semiconductor (CMOS) device, using a CMOS fabrication process,

BACKGROUND TO THE INVENTION

[0002] Complementary metal-oxide-s niiconductor (CMOS) integrated circuits (ICs) are commonly used in electronic devices, such as computers and mobile phones, and can comprise microprocessors, memories, signal processors, filters and th like. One reason for the popularity of CMOS devices is that they generally have low power consumption and can operate at high frequencies.

1000 [ Piezoelectric devices are also important in certain electronic devices, such as mobile phones, and such devices can comprise filters and sensors. A thin-film hulk acoustic resonator (FBAR or TFBAR) is an example of a piezoelectric device, and is based on the transduction of acoustic waves. FBAR devices are often used as electronic filters. An FBAR device comprises a piezoelectric material sandwiched between two electrodes, wherein the piezoelectric material has a thickness typically ranging from several microns dow to tenths of a micron and is acoustically isolated from any surrounding medium. A surface acoustic wave (SAW) device is a farther example of a piezoelectric device, and is also based on the transduction of acoustic waves. A SAW device comprises a piezoelectric material on which an inter-digital transducer (IDT) is formed. An electrical signal is converted to mechanical energy a a surface of the piezoelectric material, and back to an electrical signal via the IDT. SAW devices are commonly used. as sensors.

10004] CMOS circuits, SAW devices, and FBAR devices are generally manufactured separately. Because FB AR and SAW devices use transduction of acoustic waves, they require an air interface at both sides of the piezoelectric material for acoustic isolation. As such, FBAR and SAW devices are not easily integrated into conventional CMOS- based semiconductor fabrication processes, which do not use piezoelectric materials,

OBJECT OF THE INVENTION

[0005] It is a preferred object of the embodiments of the present invention to provide an integrated circuit structure and/or a method of forming an integrated circuit structure material that addresses or at least ameliorates one or more of the aforementioned problems of the prior art and/or provides a useful commercial alternative.

SUMMARY OF THE INVENTION

10006] According to a first embodiment, the invention resides in a method of forming an integrated circuit structure, the method comprising:

providing a substrate having an aluminum nitride (AI ) layer and a silicon layer, wherein the silicon layer covers at least a portion of the AI layer;

forming a complementary metal oxide semiconductor (CMOS) device in the silicon layer; and

forming at least one piezoelectric device in the AI layer, whereby the integrated circuit structure includes both the at least one piezoelectric device and the CMOS device.

|0007| Preferably, the at least one piezoelectric device includes an acoustic device.

[0008] Preferably, the at least one piezoelectric device includes a SAW device. j0009| Preferably, the at least one piezoelectric dev ice includes an FBAR device.

[0010] Preferably, the at least one piezoelectric device includes both an FBAR device and a SAW device.

[0011] Preferably, the FBA device includes an electrode, and the SAW device includes an inter-digital transducer (IDT), and wherein the electrode and the inter-digital transducer are formed at least partly from a common layer of high acoustic impedance material- [0012] Preferably, the common layer of high acoustic impedance material comprises a layer of aluminium, molybdenum, tungsten and/or nickel .

[0013] Preferably, the method further comprises:

forming a first cavity adjacent the FBAR device, and

forming a second cavity adjacent the SAW device.

[0014 j Preferably, the method further comprises:

providing an aperture in the A1N layer, the aperture defining a channel betwee one of the first cavity and the second cavity and the atmosphere.

[0015] Preferably, the method further comprises:

forming a temporary protective layer over the electrode and the IDT,

[0016] Preferably, the at least one piezoelectric device further includes a second SAW device on an opposite side of the A1N layer to the SAW device.

[0017] According to a second embodiment, the invention resides an integrated circuit

structure, comprising

an aluminum nitride (AIM) layer;

a silicon layer that covers a portion of the AiN layer;

at least one CMOS device formed in the silicon layer; and

at least one piezoelectric device formed in the AIN layer.

[0018] Preferably, the at least one piezoelectric device includes an acoustic device.

[0019] Preferably, the at least one piezoelectric device includes a SAW device.

[0020] Preferably, the at least one piezoelectric device includes an FBAR device.

[0021 j Preferably, the at least one piezoeiectric device includes both art FBAR device and a SAW device.

[0022] Preferably, the FBA device includes an electrode, and the SAW device includes an inter-digital transducer (IDT), and wherein the electrode and the inter-digital transducer are formed from a common layer of high acoustic impedance material. [0023! Preferably, th e common layer of high acoust ic impedance ma terial comprises a layer of aluminium, molybdenum, tungsten and/or nickel . f0024| Preferably, the integrated circuit stmcture further includes a first cavit that is adjacent the FB.AR device, and a second cavity thai is adjacent the SAW device.

[0025] Preferably, the integrated circuit structure further comprises:

an aperture in the A1N layer, the aperture defining a channel between one of the first cavity and the second cavity and the atmosphere.

[0026] Preferably, the at least one piezoelectric device farther includes a second SAW device on an opposite side of the A1N layer to the SAW device,

[0027] Further features and advantages of the present invention will become apparent from the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

1002.8) The features and advantages of the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings, wherein:

[0029] FIG. I is a cross-sectional view of a generalized example of an integrated circuit (EC) structure that comprises an FBAR device, a SAW device and a CMOS device that are formed using a silicon-on-thtn film aluminum-nitride-on-silicon (SOTFANOS) substrate, according to an embodimen t of the present invention:

[0030] FIG. 2 is a cross-sectional view of an example of the SOTF ANOS substrate of FIG. i ;

[0031] FIG. 3 is a flow diagram of an example method of forming the SOTF ANOS substrate shown in F G. 2 , according to an embodimen t of the presen t in vention ;

[0032] FIG. 4 illustrates a cross sectional view of a bulk silicon substrate including a hydrogen implant layer, according to an embodiment of the present invention; [003 J FIG. 5 illustrates a cross sectional view of the substrate of FIG. 4 further including an AIN layer;

[0034J FIG. 6A illustrates the substrate of FIG. 5, further including a removable temporary substrate;

[0035] FIG. 6B illustrates the substrate of FIG, 6A _t wherein the removable temporary substrate is weakly bonded to the AI layer;

[0036J FIG. 7 illustrates the substrate of FIG. 6B, with a portion of the bulk silicon layer partially removed;

[0037J FIG. 8 illustrates the substrate of FIG. 7, with the portion of the bulk silicon layer completely removed;

|0038) FIG. 8A(i) and FIG. SA(ii) show a flow diagram illustrating example CMOS fabrication process steps used to form an 1C structure according to an embodiment of the present invention, where FIGS. 9 through FIG. 31 illustrate the structure after each of these process steps;

(0039) FIG. 9 iilustrates a substrate comprising the SOTFANOS substrate of FIG. 2, on which alignment marks are formed, according to an embodiment of the present invention;

(0040) FIG. 10 illustrates the substrate of FIG. 9, further comprising a pad oxide layer and a silicon nitride layer;

(0041) FIG. 1 3 , illustrates the substrate of FIG. 10, on which patterned photoresist layer is formed on a portion of the silicon nitride layer;

(0042) FIG. 12 illustrates the substrate of FIG. .1 1. wherein portions of the silicon nitride layer and the pad oxide layer have been removed;

[0043J FIG. 13 illustrates the substrate of FIG. 12, wherein an exposed portion of a silicon layer is oxidized; [0044] FIG. 14 illustrates the substrate of FIG. 1 3, wherein a silicon dioxide layer and a silicon nitride layer are stripped off of the substrate, at a portion where a CMOS device is to be formed, for example by plasma etching; 0045] FIG. 15 illustrates the substrate of FIG. 14 wherein a sacrificial oxide layer as removed and a gate oxide layer is formed;

[0Q46J FIG, 16 illustrates the substrate of FIG. 1.5, further including a polysilicon layer, a silicide layer and a cap oxide layer;

[0047] FIG. 17 illustrates the substrate of FIG. 16, wherein the cap oxide layer, the silicide layer, the polysilicon layer, and the gate o ide layer are etched, according to a gate mask pattern;

[0048] FIG. I S illustrates the substrate of FIG. 17, on which a blanket dielectric layer is formed; j0049{ FIG. 19 illustrates the substrate of FIG. I S, on which acoustic openings have been etched;

[0050J FIG. 20 illustrates the substrate of FIG. 19, further including a blanket layer of higli acoustic impedance material of, for example, aluminium, molybdenum, tungsten and/or nickel;

[0051] FIG. 21 illustrates the substrate of FIG. 20, wherein portions of the blanket layer have been removed to define an FBAR electrode and an IDT;

[0052] FIG. 22 illustrates the substrate of FIG. 21 , further including contact holes;

[O053J FIG. 23 illustrates the substrate of FIG. 22, further comprising a metallic layer;

[0054] FIG. 24 illustrates die substrate of FIG. 23, further including a passivation layer;

|0055{ FIG. 25 illustrates the substrate of FIG. 24, further including a handle wafer;

[0056] FIG. 26 illustrates the substrate of FIG, 25, wherein the temporary substrate has been removed; [0057] FIG. 27 illustrates the substrate of FIG. 26, further including a blanket layer of high acoustic impedance material;

[0058] FIG. 28 illustrates the substrate of FIG. 27, wherein a portion of the blanket l ayer of high acoustic impedance material has been removed to form a second. FBAR. electrode and a another IDT;

[005 j FIG. 29 illustrates the substrate of FIG. 28, wherein a portion of the A1N layer has been removed to form an opening;

10060] FIG. 30 illustrates the substrate of FIG. 29, further including connection pads;

|0061 [ FIG. 31 illustrates the substrate of FIG. 30, wherein portions of the AIN layer have been etched adjacent an FBAR device and a saw device;

|0062J FIG. 32 is a flow diagram illustrating example CMOS fabrication process steps used to form an IC structure according to another embodiment of the present invention, where FIGS. 33 through FIG. 46 illustrate the structure after each of these process steps;

[0063] FIG. 33 illustrates the substrate of FIG . 21 , further including a protective layer which fills the acoustic openings above the FBAR electrode and first IDT;

[0064] FIG. 34 illustrates the substrate of FIG. 2 I B, .further including contact holes;

|0065J FIG. 35 illustrates the substrate of FIG. 22A. further comprising a metallic layer;

[0066] FIG. 36 illustrates the substrate of FIG. 23 A, further comprising an inter-layer dielectric and a silicon nitride layer;

[0067] FIG. 37 illustrates the substrate of FIG. 23B further comprising trenches in the interlayer dielectric, silicon nitride layer and protective layer around the FBAR electrode aid the IDT;

|0068j FIG. 38 illustrates the substrate of FIG. 23C further including a blanket layer of silicon nitride which fills the trenches;

100691 FIG, 39 illustrates the substrate of FIG. 24A, further including a handle wafer; [0070J FIG. 40 illustrates the substrate of FIG. 25 A, wherein the temporary substrate has been remo ved;

[00 1 J FIG. 1 illustrates the substrate of F IG. 26A, further including a blanket layer of high acoustic impedance material;

[0072] FIG. 42 illustrates the substrate of FIG, 27 A, wherein a portion of the blanket layer of high acoustic impedance material has been removed to form a second FBA electrode and another IDT;

|0073j FIG. 43 illustrates the substrate of FIG. 28A, wherein a portion of the A1 layer has been removed to form an opening;

[0074 J FIG. 44 illustrates the substrate of FIG. 29 A, further including connection pads;

|0O75) FIG. 45 illustrates the substrate of FIG . 30A, wherein portions of the AIN layer have been etched adjacent an FBAR device and a saw device;

[0076J FIG. 46 illustrates the substrate of FIG. 3 LA, wherein the protective layer under each of the FBAR device and the SAW device etched away to form a cavity; and

(0077) FIG. 47 is a flow diagram of an example of a raethod of integrating a CMOS device, an FBAR device and a SAW device using the SOTFANOS substrate.

[Q078J Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

(0079) The components in the drawings have been represented where appropriate by conventional symbols, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the ait having the benefit of the description herein. DETAILED DESCRIPTION OF THE INVENTION

[0080] A process of forming an integrated circuit (IC) structure including a piezoelectric device and a complementary metal oxide semiconductor (CMOS) device is provided, using a CMOS fabrication process. The CMOS fabrication process uses a silicon-on-thin film aluminum-nitride on. silicon (SOTFANOS) substrate. More specifically, the SOTFANOS substrate comprises a relatively thick silicon layer atop a thin layer of aluminum nitride (AIM) on a temporary silicon substrate. The SOTFANOS substrate is bonded to a removable temporary substrate that facilitates the handling of the SOTFANOS substrate during the CMOS fabrication process. The aluminum nitride (AIN) layer has low electrical conductivity (i.e., it is an electrical insulator), high thermal conductivity, and good piezoelectric properties,

[0081 { Because the aluminum nitride layer of the SOTF ANOS substrate has piezoelectric properties, the SOTFANOS substrate is suitable for forming piezoelectric devices, such as FBA and SAW devices. As will be readily understood by a person of ordinary skill in the art, the methods described herein can be used to form a variety of piezoelectric devices, including acoustic sensors and transducers. Other examples of suitable piezoelectric devices include filters, other types of sensors and other types of transducers.

[0082] The use of the SOTFANOS substrate supports the use of a CMOS fabrication process wherein both CMOS devices and the piezoelectric devices are formed using a common SOTFANOS substrate. For example, CMOS devices can be formed starting with the silicon layer of die SOTFANOS substrate, while piezoelectric devices such as FBAR and SAW devices can be formed using the AI layer of the same SOTFANOS substrate.

[0083] An aspect of the disclosure includes an IC structure that includes a CMOS device formed in the silicon layer and a piezoelectric device, such a an FBAR or SAW device, formed in the AIN layer of the same SOTFANOS substrate.

(0084J More particularly, a piezoelectric device can be formed by (1 ) removing a portion of the silicon layer of the SOTFANOS substrate to expose the AIN layer; and (2) providing an electrode on the exposed AIN layer. The electrode can, for example, be an electrode of an electrode pair, in the case of an FBAR device, or pail of an inter-digital transducer (IDT) in the case of a SAW device. The electrodes and piezoelectric material of the piezoelectric device are maintained in atmosphere so that vibration of the piezoelectric device is not inhibited, thereby substantially achieving acoustical isolation from the surrounding medium.

[0085] According to certain embodiments, an IDT of a SAW device is formed at the same time as an electrode of an FBAR device, and on a same side of the A1.N layer.

[0086] Because of the high heat dissipation that the AIM layer of the SOTFANOS substrate permits, the SOTFANOS substrate provides greater thermal management capability than do conventional substrates, which have poor thermal conductivity. Therefore, CMOS and piezoelectric devices can be integrated into a single integrated circuit using the SOTFANOS substrate. This is because the SOTFANOS substrate provides both, high thermal conductivity and piezoelectric properties.

[0087] Accordingly, a method of integrating CMOS devices and piezoelectric devices, such as SAW devices and FBAR devices, using the SOTFANOS substrate is provided that reduces the complexity and cost of implementing both CMOS technology and piezoelectric technology as compared with using conventional substrates and methods. Further, the implementation of S AW and/or FBAR devices using a CMOS manufacturing process enables these SAW/FBAR devices to be formed with operating frequencies of up to about 40 GHz, which far exceeds that of conventional discrete SAW/FBAR devices, whose maximum operating frequency is limited to about 10 GHz.

[0088] FIG. 1 is a cross-sectional view of an iC structure 100 that comprises an FBAR device 105, a SAW device 1 10 and a CMOS device 1 15, formed using a SOTFANOS substrate 120. The SOTFANOS substrate 120 comprises an aluminum nitride (A1N) layer 125, a silicon (Si) layer 1.30 and a temporary substrate 135. The A IN layer 125 has low electrical conductivity, high thermal conducti ity, and good piezoelectric properties, which is well-suited for forming FBAR devices 105 and SAW devices 1 10, which are examples of piezoelectric devices. At the same time, the silicon layer 130 is well-suited as a starting layer of a CMOS fabrication process. More details of the SOTFANOS substrate 120 are described below with reference to FIG. 2. [0089! The temporary substrate 135 is a bulk substrate that is formed, for example, of silicon, metal, quartz, or other materials depending on the application. The FBAR device 105, the SAW device 1 10 and the CMOS device 1 15 are formed on the SOTFANOS substrate 120 using a CMOS fabrication process, as described further below.

[0090] The FBAR device 105 is formed by removing a portion of the silicon layer 130 of the SOTFANOS substrate 120 to expose a portion of the A1N layer 125. A first electrode 140 is pro vided on one side (i.e., the exposed side) of the AIN layer 125 and a second electrode 140 on the reverse side of the A1N layer 125 that is in a cavity 145 of the temporary substrate 135. Similarly, the SAW device 1 10 is formed by removing a portion of the silicon layer 130 of the SOTFANOS substrate 120 to expose a portion of the AIM layer 125. An IDT 150 is pro vided on the reverse side of the AIN layer 125 that is in a cavity 145 of the temporary substrate 135. Optionally, a second IDT can also be provided on the exposed side of the AIN film 125 above the IDT 150.

|00911 Because a cavity 145 is provided between the FBAR device 105 and the temporary substrate 135, and a cavity 145 is provided between the first IDT 1 0 of the SAW device 110 and the temporary substrate 135, the FBAR device 105 and the SAW device 1 .10 are acoustically isolated from any surrounding medium.

|0092| Because the FBAR device 105 and the SAW device 1 10 are fabricated using a CMOS manufacturing process, the FBAR device 105 and the SAW device 1 10 can have an operating frequency of up to about 40 GHz. The frequency limit of the CMOS process is determined by a geometry of the transistors, which is known in the art. For example, conventional 0.25 -micron processes have an upper operating frequency limit of about 15 GHz. However, deep sub-micron processes, e.g., 65-nanometer processes, can have an operating frequency that exceeds 60 GHz. Discrete FBAR devices and SAW devices of the prior art generally have a maximum operating frequency of about 5 GHz.

10093 J As will be readily understood by a person skilled in the ait, the IC structure 100 can be easily extended to include a plurality of CMOS devices 1 15, a plurality of FBAR devices 105 and/or a plurality of SAW devices 110. Similarly, the teachings of the present disclosure can be readily adapted by a person of ordinary skill in the art to integrate one or more other piezoelectric devices on. the IC structure 100, i addition to or as an alternative to the FBA de vice 105 and/or the SAW device 10.

[0094] FIG. 2 is a cross-sectional view of an example of the SOTFANOS substrate 120, which has piezoelectric properties. The SOTFANOS substrate 120 comprises the A N layer 125 and the silicon layer 130, mounted atop the temporary substrate 135, The temporary substrate 135 is a bulk substrate that is formed, for example, of silicon, metal quartz, or other materials, depending on the application.

[0095] The AIN layer 125 has a thickness of up to several microns in some examples, and from about 250 njm to about 3 μηΐ in other examples. The AI layer 125 serves as a piezoelectric material that is needed to form piezoelectne devices, such as the FBAR device 105 and the SAW device 1 JO, while the silicon layer 130 serves as a starting layer for forming a CMOS circuitry. Therefore, the silicon layer 130 is a thin layer of silicon. For example, the thickness of the silicon layer 130 is from about 75 nm to about 1 10 am, in one example, or about 100 rtm in another example. However, as will be understood by a person of ordinary skill i the art, the thicknesses of the silicon layer 130 and the AIN layer 125 can vary- depending on the application.

1 0.96] The temporary substrate 135 serves as a base substrate and, therefore, is suitably thick to perform this function. The thickness of the temporar substrate 135 can vary depending on a diameter of the SOTFANOS substrate 120. Namely, the larger the diameter, the thicker the temporary substrate 135. If the diameter of the SOTFANOS substrate 120 is about 150 mm, then the thickness of the temporary substrate 135 is from about. 600 μηι to about 700 fim in one example, or about 675 μτη in another example.

[00.97] According to certain embodiments, the bond between the AI layer 125 and the temporary substrate 35 is weak, which allows the temporary substrate 135 of the SOTFANOS substrate 120 to be separated from the AIN layer 125 and removed as needed in the CMOS rabri catio process. According to other embodiments, the temporary substrate 135 is removed after high temperature CMOS processing. For example, the temporary substrate 135 can be bonded to the AIN layer 125 by hydrophil tc bonding with interface oxides and then removed later by a Microelec romechanical Systems (MEMS) undercut etch through holes in the temporary substrate 135.

[0098] in one example, the SOTFANOS substrate 120 is based on the substrate disclosed in International Publication WO/2013/067572, published May 16, 2013, entitled "A semiconducior-on-insulator structure and process for producing same," which appl ication is incorporated herei by reference. More details of a method of forming the SOTFANOS substrate 120, which includes the weak bond between the A! layer 125 and the temporary substrate 135, are now described with reference to FIG. 3 to FIG. 8,

[0099] FIG. 3 illustrates a flow diagram of an example method 300 of forming the SOTFANOS substrate 120 of FIG. 2. FIG. 4 through FIG. 8 illustrate a process of forming the SOTFANOS substrate 120 according to the method 300 o FIG. 3, hi one example, the method 300 is based on the method described with reference to the aforementioned International Publication WO/20! 3/067572, The method 300 includes the steps below.

[00100] At a step 310, hydrogen is implanted into a bulk silicon substrate. For example and referring now to FIG. 4, a bulk Si substrate 410 is ion implanted with a gaseous hydrogen species 510 to form a buried implant layer 514. In one example, about 140 keV H ions are implanted to an area! density of about 6 x 10 ¹⁶ cm'. The implant layer 514 has a depth D, which is the depth to which the species are implanted into the bulk Si substtate 410. in one example, the depth D of the implant layer 514 is from about 1. pm to about 1.2 μηα. An implant boundary 518 indicates the boundary of the implant layer 514 that is deepest into die bulk Si substrate 410.

[00101] At a step 314, an aluminum nitride layer is formed on the bulk silicon substrate after the hydrogen is implanted. For example and referring now to FIG. 5, the A N layer 125 is formed o the bulk Si substrate 410 after the gaseous hydrogen species 510 is implanted. The AIN layer 125 has a thickness of from about 250 nm to about 3 ηι. In general, the thickness of the AIN layer 125 will be selected to provide sufficient thermal conductance to enable semiconductor devices formed using the SOTFANOS substrate 120 to be operated at a desired power as well as at the operating frequency of any piezoelectric devices, such as the FBAR device 105 and the SAW device .1.10. Accordingly, the AIN layer 125 in other embodiments may be thicker. Typically, the thickness of the AIN layer 125 does not exceed about 3um, but thicknesses of several microns can be required for certai high-power applications. The AIN layer 125 can be grown on die bulk. Si substrate 410 by molecular beam epitaxy (MBE), reactive sputtering, metal-organic chemical vapor deposition (MOCVD), or hydride vapor-phase epitaxy (HVPE) using standard methods known to those skilled in the art.

|00102] At a step 3 8, a temporar substrate 135 is weakly bonded to an exposed side of the aluminum nitride layer on the bulk silicon substrate. For example and referring now to FIG. 6 A and FIG. 6B, the AIN layer 125 , which lias been grown on the bulk Si substrate 410, is weakly bonded to the temporary substrate 135. in so doing, a substrate stack is formed.

[00103] In one example, the temporary substrate 135 is a standard silicon wafer having a polished surface with a surface roughness of < 1 ivm, root mean squared (RMS). The bonding between AIN and Si is generally rather poor; however, in the context of the described embodiments, this is desirable because the bonding between the AIN layer 125 and the temporary substrate 135 is to be reversed when used in a CMOS manufacturing process, an example of which is described below. In any case, the strength of the bonding is increased by heating the substrate stack at a low temperature ibr a short period (e.g., about I 20°C for 2 hours) and then raising the temperature for a longer period (e.g., about 300 ^o C for 10 hours) to further improve the bonding strength. However, it will be apparent to those skilled in the art that other combinations of temperature and time can be readily determined to provide a suitable bond strength that is sufficient to maintain the bonding during processing up until the AIN layer 125 and the temporary substrate 135 are separated, in one example, a hydrophilic bond is formed using SiQ? at the interface between the AIN film 125 and the substrate 135 to assist, the bonding.

[00104] At a step 322, the substrate stack is heat treated to induce a fault plane at a boundary between the implanted hydrogen and the bulk silicon substrate, such as the implant boundary 51 8. For example and referring again to FIG. 6 A and 6B, the substrate stack, which comprises the temporary substrate 135, the AI layer 125, and the bulk Si substrate 41.0, is heat treated at a temperature sufficient to induce a fault plane at the implant boundary 518 so that a majority portion of the bulk Si substrate 410 can be subsequently split away and removed. In one example, the substrate stack is heated to a temperature of about 400° to 600°C for about 15 minutes.

[00105] At a step 326, a majorit portion of the bulk silicon substrate is separated at the fault plane and removed, leaving a thin layer of silicon behind on the aluminum nitride layer. For example and referring now to FIG. 7, a majority portion of the bulk Si substrate 410 is split at the fault plan that has formed at the implant boundary 5 8 and removed, leaving behind the sihcon layer 130 o the A1.N layer 125, as shown i FIG. 8. At this point in the process, the silicon layer 130 has a rough surface and will require further processing. After the non-bonded portion of the bulk Si substrate 410 ( which can be re-used) has been removed, the remaining structure is annealed at a temperature of up to 1 ,100°C for about 1 hour to anneal any residual damage to the silicon layer 130 caused by the implanted hydrogen and to remove the hydrogen from the silico layer 130.

(00106] At a step 330, tire silicon layer is processed to provide a desired thickness and planarity that is suitable for the CMOS fabrication process. As known by those skilled in the art, "ion-cut" processes leave a rough surface on the remaining silicon layer. For example and referring now to FIG. 8, the surface of the silicon layer 130 is subjected to a chemical mechanical polish/planarization (CMP) process to reduce die thickness of the silicon layer 130 to, for example, from about 75 nm to about 1 10 urn, depending on process parameters, thereby forming the SOTFANOS substrate 120 shown in FIG. 2. The SOTFA OS substrate 120 has a smooth, device-quality semiconductor thin film (i.e., the silicon layer 130) on the AlN layer 1.25. The SOTFANOS substrate 120 is now ready for use in any CMOS fabrication process.

(00107] FIG. 8A(i) and FIG. 8A(ii) show a flow diagram illustrating example CMOS fabrication process steps used to form an IC structure according to an embodiment of the present invention. These process steps are described in further detail with reference to FIG. 9 through FIG. 3 1 , which illustrate the structure after each process step. The figure that is relevant to each process step is identified in each bo of the flow diagram. [00108] The steps of the CMOS fabrication process shown, in FIG. 8A(i) through FIG. 31 collectivel constitute an example of a CMOS fabricatio process that utilizes a SOTFANOS substrate, such as tbe SOTFANOS substrate 120, as a starting substrate. However, the method is not limited to the CMOS fabrication process steps shown in FIG. 8A(i) through FIG. 3 1. Any CMOS fabrication process of any CMOS manufacturer may be used to form any arrangement of piezoelectric devices, such as FBAR. devices 105 and SAW devices 110, and CMOS devices, such as the CMOS device 1.1.5, on the SOTFANOS substrate 120.

[00109] FIG. 9 illustrates a substrate, comprising the SOTFANOS substrate 120, after process step 802 has been performed. At process step 802, alignment marks 905 are formed on the substrate. The alignment marks 905 are used to align the substrate during the CMOS fabrication process. The integrity of the alignment marks 905 is thus maintained through the entire CMOS fabrication process.

100110 j The alignment marks 905 are formed by etch ing a portion of the sil icon layer 130 and a corresponding portion of th AIM layer 125. I particular, a photoresist layer can be formed on the silicon layer 130, defining portions of the silicon layer 130 and the A1N layer 125 in which the alignments marks 905 are to be formed. The silicon layer 130 and the AiN layer 125 are then etched to form the alignments marks 905. after which the photoresist layer is removed. jOOl 111 FIG. 10 illustrates the substrate of FIG. 9, after process step 804 has been performed. A process step 804, a deposition step is performed on the substiate. Firstly a stress relief silicon dioxide layer in the form of a pad oxide layer 1005 is grown on the silicon layer 130, followed by a silicon nitride layer 10.10 on top of the pad oxide layer 1005. These layers will be subsequently patterned and etched using an active area mask.

[001 12] The pad oxide layer 1005 is formed by first cleaning the substrate using a hydrofluoric acid solution at a concentration of 50:1 for 30 seconds. The substrate is then oxidized by beating the substrate to about 900°C, in order to achieve a pad oxide layer 1005 that is about 1 l .ni thick. [00113] Tbe silicon nitride layer 1.010 is formed using a Ν¾ and dichiorosilane (DCS) solution at about 800°C. The silicon nitride layer 1010 is generally about 145nm thick.

[00114] FIG. 11 illustrates the substrate of FIG. 10, after process step 806 has been performed. At process step 806, a patterned photoresist, layer 1 105 is formed, on. a portion of the silicon nitride layer 1010, The patterned photoresist layer 1 105 is formed using a photolithography process, which is well known in the art, using an active area mask pattern that is exposed and developed in a photolithography tool. The portion on which the patterned photoresist layer 1 105 is formed corresponds to a portion of the substrate on which a CMOS device is to be formed.

100115] FIG. 12 illustrates the substrate of FIG. 1 1 , after process step 808 has been performed. At process step 808, portions of the silicon nitride layer 1010 and the pad oxide layer 1.005 are- removed. This removal is performed by using an etching process, such as a plasma etching process, to etch away the silicon nitride layer 1010 and the pad oxide layer 1005 that is left, exposed through the patterned photoresist layer 1 105. In doing so, a portion of the silicon layer 130 is exposed.

[00116{ The substrate is then cleaned using a hydrofluoric acid solution at a concentration of 100:1 for 30 seconds,

[00117] FIG. 13 illustrates the substrate of FIG. .12, after process step 810 has been performed. At process step 810, the exposed portion of the silicon layer 130 is oxidized. The oxidation can. for example, be performed using a wet oxidation process, which converts the exposed portion of the silicon layer 130 to silicon dioxide, thereby forming a field oxide layer 1205. Tire process of converting silicon to silicon dioxide causes a thickness of the resulting field oxide layer 1205 to increase to about double that of the original silicon layer 130, for example to about 200 ntn.

[001.18] Therefore, the resulting field oxide layer 1205 is etched back to a desired thickness of, for example, about 145 urn. This etching and oxidation step results in. for example, a silicon layer 130, which is still about 100 nra thick surrounded by the field oxide layer 1205 that is, for example, about 145 nm thick and formed on the AIN layer 125. One of the purposes of the field oxide layer 1205 is to protect a surface of the AIN i s layer 125 daring subsequent CMOS fabrication process steps. The field oxide layer 1205 is advantageously etched back using a buffered oxide etch at a volume ratio of 7:1.

[001.19] In addition to oxidization and etching of a portion of the silicon layer 130, the patterned photoresist layer 1 105 is stripped away. The patterned photoresist layer 1105 is advantageously stripped away using a sulfuric acid - hydrogen peroxide mixture (SPM).

[00120] Various CMOS fabrication process steps disclosed herein may utilize the well- known photolithography process of photoresist coating, exposing, and developing, such as that described herein. However, for the sake of simplicity, the well-known photolithography process that occurs during certain steps of the CMOS fabrication process described below may not be shown or mentioned explicitly. However, a person of ordinary skill in the art will readily appreciate that such steps may occur.

[001211 FIG. 14 illustrates the substrate of FIG. 13, after process step 8.12 has been performed. At process step 812, the pad oxide layer 1005 and the silicon nitride layer 1010 are stripped off of the substrate, at a portion where the CMOS device is to be located, tor example by plasma etching. Then, a fresh layer of silicon dioxide in the form of a sacrificial oxide layer 1405 is deposited on the substrate where the CMOS device is to be located.

[00122] In particular, an edge control photoresist step with an N+ mask is performed, followed by an edge control implant step, on an area of the substrate corresponding to where the CMOS device is to be located, while masking other areas of the substrate. The photoresist layer can then be stripped using an SPM, followed by an edge control anneal step and a nitride strip step, as is well understood in the art.

[00.123] Finally, oxidation can be performed by first stripping the pad oxide layer 1005 and the silicon nitride layer 10.10 using 50:1. HF for about 120s, followed by wet oxidation at about 800C to form the sacrificial oxide layer 1405 layer that is approximately 1 3 nra thick.

[00124] As will be readily understood by a person of ordinary skill i the art, several ion- implantation steps not described can also occur, in particular steps that relate to the formation of the CMOS device. Such steps are, however, specific to the particular CMOS device being formed and outside of the scope of the present disclosure, and are thus not described herein.

[00125] FIG. 15 illustrates the substrate of FIG. 14, after process step 814 has been performed At process step 814, the sacrificial oxide layer 1405 is removed and a gate oxide layer 1505 i formed. The gate oxide layer 1505 is very thin, for example about 82 A thick. As will be readily understood by the skilled addressee, the gate oxide layer 1505 is not drawn to scale for the sake of clarity due to the large difference in thickness between the gate oxide layer 1505 and other layers.

|00126] The gate oxide layer 1 505 i formed by first stripping the sacrificial oxide layer 1405 using SPM-50:! HF for about 120s, followed by a wet oxidation step at about 800C.

[00127] As will be readily understood by the skilled addressee, several masking and ion- implantation steps also occur, but are not shown for the purpose of clarity. For example, a photolithography process can be used to form a mask pattern in a layer of photoresist, after which an implant process is performed. These steps can be used to create various doped regions that form the CMOS device. These steps can include regular n-channel transistor (EN) threshold implantation, regular p-channel transistor (PN) threshold implantation, low n-channel transistor (NL) threshold implantation, and low p-channel transistor (PL) threshold implantation.

[00128] FIG. 16 illustrates the substrate of FIG. 15, alter process step 816 has been performed. At process step 8.1.6, a poiysilicon layer 1.605, a silicide layer 1610 and a cap oxide layer 1615 are formed on the substrate, in particular, the poiysilicon layer 1605 is formed over substantially the entire surface of the substrate, and is, for example, about 250 niB thick. This is the first step of forming a poiysilicon gate of the CMOS device. This is followed by several masking and ion-implantation steps not described, but well understood by those of ordinary skill in the art to form P channel and N channel CMOS devices. [00129] The silicide layer 1610 can, for example, comprise tungsten siticide (WSi), titanium silicide (TiSi), cobalt silicide ^' (CoSi2) or nickel silicide (NiSi), and is formed on the polysilicon layer 1605. The silicide layer 1610 can, for example, be about 150nm thick. The cap oxide layer 1615 is then formed, for example using a plasma-enhanced chemical vapor deposition (PECVD). The cap oxide layer 1 615 can, for example, comprise silicon dioxide that is about 170nm thick.

[00130] FIG. 17 illustrates the substrate of FIG. 16, after process step 818 has been performed. At process step 818, the cap oxide layer 1 615, the silicide layer 1610, the polysilicon layer 1 605, and the gate oxide layer 1 505 are etched, according to a gate mask pattern.

[00131] In particular, photolithography process can be used to form the gate mask partem, and the cap oxide layer 161 5, the silicide layer 1 610, the polysilicon layer 1605, and the gate oxide layer 1 505 can be etched using, for example, plasma etching. A reoxidation step is the performed to form a reoxidation layer 1705. The reoxidation layer 1 705 can be about is about l lnm thick and be formed using dry oxidation at about 850C.

[00132] FIG. 18 illustrates the substrate of FIG. 17, after process step 820 has been performed. At process step 820, a blanket dielectric layer is formed on the substrate.

[00133] As will be readily understood by the skilled addressee, several steps relating to formation of the CMOS device are also generally present, but are not described with reference to FIG. 18 for the sake of clarity. Such steps can, for example, relate to the formation of lightly doped drain (LDD) spacers at the gate structure of the CMOS device. In such case, a purpose of the oxide spacers can be to inhibit diffusion of any source and drain implant under the gate structure during any subsequent implant steps.

[00134] The blanket dielectric layer is formed over substantially the entire surface of the substtate and comprises an undoped dielectric layer 1805, that is formed over the surface of the substrate, followed by boron phospho-silicate glass (BPSG) inter-level dielectric (ELD) oxide layers 1810 that are in total about 1 μχη thick. The dielectric layers are formed,, for example, using a PECVD process. The undoped dielectric layer 1805 can, for example, comprise a non-doped silicate glass (NSG) layer that is about 200nm th ick. The BPSG ILD can be formed by depositing multiple BPSG ILD oxide layers .1810 on the undoped dielectric layer 1805, for example two BPSG ILD oxide layers 1810 each approximately 450nm thick.

[00135] FIG. 19 illustrates the substrate of FIG. 18, after process step 822 has been performed. At process step 822, acoustic openings 1 05 are etched in the substrate. In particular, photolithography and etching process in which the undoped dielectric layer 1805 and the BPSG ILD oxide layers 1810 are etched to provide the openings 1.905 that expose portions of the A1N layer 125 to be used for the FBAR device and the S AW device.

[00136] In particular, a photoresist layer is provided on a portion of the substrate, about which an etch process is used to remove the undoped dielectric layer 1805 and the BPSG ILD oxide layers 1810, The photoresist layer is then removed using an SPM, as described above.

[00137] FIG. 20 illustrates the substrate of FIG. 19, after process ste 824 has been perfonned. At process step 824, a blanket layer of high acoustic impedance material 2005 is formed on the substrate. The layer of high acoustic impedance material 2005 comprises, for example, molybdenum, aluminum, tungsten and/or nickel For example, a molybdenum layer 2005 that is, for example, about I μηι thick is formed over substantially the entire surface of the substrate including the openings 1 05. The molybdenum layer 2005 is formed, for example, using a sputtering or evaporation process. The molybdenum layer 2005 may be formed as one single layer or by depositing multiple layers that total the desired thickness. jOOl 38| As will be readil understood by the skilled addressee, the substrate can be stripped of oxidation prior to additio of die molybdenum layer 2005, for example using a 100; I OF solution for about 30s.

[00139] FIG. 21 illustrates the substrate of FIG. 20, after process step 826 has been performed. At process step 826, portions of the layer of high acoustic impedance material 2005 are removed. For example, the substrate undergoes a photolithography and etching process in which the molybdenum layer 2005 is etched to define an FBAR electrode 2105, which forms part, of the FBAR device. The same photolithography and etch step is used to define an IDT 21 10 that forms part of the SAW device.

[00140] The etching used to form the FBAR electrode 2105 and the IDT 21 10 can be performed using a photoresist layer in the form of a mask, followed by etching, and subsequent stripping of the photoresist layer.

[00141] FIG. 22 illustrates th substrate of FIG. 21, after process step 828 has been performed. At process step 828, contact holes 2205 are formed in the substrate. In particular, the substrate undergoes a photolithography and etching process, similar to that described above, to form the contact holes 2205. The contact holes 2205 extend towards the AI layer 125.

[00142] FIG. 23 illustrates the substrate of FIG. 22, after process step 830 has been performed. At process step 830, a metallic layer 2305 is formed on the substrate. In particular, an aluminum layer 2305 is formed over the surface of the substrate, followed by a metal pattern and etch to form an interconnection between portions of the substrate. Individual steps are not shown here for simplicity, but can include pre-sputter etching, using for example a 50:1 H.F solution for 30s, followed by various metal sputter steps, etching and cleaning. For example, the aluminum layer 2305 can have a thickness of about 1 μτη and while only a single metal layer is shown in FIG. 23 and FIG. 23a, the metallic layer 2305 can be formed of several layers. As an illustrative example, 6 layers can be used.

[00143] FIG. 24 illustrates the substrate of FIG. 23, after process step 832 has been performed. At process step 832, a passivation layer 2405 is formed on the substrate, hi particular, the substrate undergoes a blanket deposition of passivation material over substantially an entire surface of the substrate. For example, the passivation layer 2405, which is, for example, about 1200 nm thick, is formed over substantially an entire surface of the substrate. The passivation layer 2405 can be formed by a combination of two layers of material. For example, the passivation layer 2405 can include a layer of phospho-silicate glass (PSG) 2410 that is, for example, about 500 nm thick and optionally, depending on the application, a layer of silicon nitride 2415 that is, for example, about 700 nm thick. The passivation layer 2405 can be formed, for example, using a PECVD process, discussed above. Electrical wiring between CMOS devices is implemented under the passivation layer 2405 and at this stage of the process the CMOS device is substantially complete.

[00144] The passivation layer 2405 is then removed above the IDT 21 10 and the FBAR electrode 2105. This can be achieved by placing a photoresist layer on a portio of the substrate, etching away the passivation layer, followed by removal of the photoresist layer, in a similar manner to that discussed above.

[00145] FIG. 25 illustrates the substrate of FIG. 24, after process step 834 has been performed. At process step 834, a handle wafer 2505 is bonded to the passivation layer 2405. In particular, the passivation layer 2405 is planarized by, for example, a chemical mechanical polishing (CMP) process. Then, the handle wafer 2505 is bonded to the passivation layer 2405 by, for example, a fusion bonding process. The handle wafer 2505 forms cavities 2510 around the FBAR electrode 2105 and tire IDT 2110 as shown in FIG. 25.

[00146] FIG. 26 illustrates the substrate of FIG. 25, after process step 836 has been performed. At process step 836, the temporary substrate 135 is removed. For the sake of clarity, the substrate is shown inverted in FIG. 26 and in subsequent figures.

1 1471 In particular, the temporary substrate 135 is removed from the AIN layer 125. in one example, the temporary substrate 135 is removed from the A1N layer 125 by being pried off with a knife-edge. This is possible due to the weak bond between the temporary substrate 135 and the AIN layer 125. In another example the temporary substrate 135 is removed from the AIN layer 125 by undercutting the A1IS1 / Si bond formed by silicon dioxide via fluorine plasma etch through etched holes in the temporary substrate. In another example, for instance, where a hydrophilic bond is Ibnned using SiOj at the interface between the AIN film 125 and the substrate 135, the temporary substrate 135 can be removed by baekgrinding the substrate 135 down to approx. 50μηι thick and then chemically etch the remaining silicon down to the SiO? layer on top of the AIN layer 125. [00148] FIG. 27 illustrates the substrate of FIG. 26, after process step 838 has been performed. At process step 838, a blanket layer of high acoustic impedance material 2705 is formed on the substrate. In particular; a molybdenum layer 2705 is formed over substantially the entire surface of the exposed AIN layer 125. The molybdenum layer 2705 is formed, for example, using a sputtering process or an evaporation process. As will be readily understood by a person of ordinary skill in the art, the blanket tayer of high acoustic impedance material can comprise any of man suitable high acoustic impedance materials, including for exam e aluminium, tungsten and/or nickel.

[00149] FIG. 28 illustrates th substrate of FIG. 27, after process step 840 has been performed _* At process step 840, a portion of the blanket layer of high acoustic impedance material 2705 is removed to form a second FBAR electrode 2105 and optionally another IDT 21 1 , In particular, the substrate undergoes a photolithography and etching process in which the molybdenum layer 2705 is etched to define the second FBAR electrode 2105. Formation of the second FBAR electrode 2105 completes the FBAR device. A SAW dev ice 21 10 is also completed at this stage and if required the other IDT 21 10 is formed,

[00150] FIG. 29 illustrates the substrate of FIG. 28. after process step 842 has been performed. At process step 842, a portion of the AIN layer is remo ved to form an opening 2905. In particular, the substrate undergoes a photolithography and etching process in which the opening 2905 is formed through the AI layer 125 to the layers tinder the AlN layer 125. This is formed in one example by plasma etching,

(00151 { FIG. 30 illustrates the substrate of FIG. 29, after process step 844 has been performed. At process step 844, connection pads are formed, in particular, at process step 844, a metallization layer 3005 is formed on the substrate, which in one example comprises aluminum. The metallization layer 3005 is then patterned and etched to form connection pads and interconnects, After the metallization layer 3005 is etched and any photoresist layer is stripped, a blanket phosphosilicate glass (PSG) layer 3010 is formed. A silicon nitride passivation layer 3015 is then formed, for example via plasm enhanced chemical vapor deposition. The PSG layer 3010 and the silicon nitride passivation layer 3015 are then patterned and etched to define openings of the SAW device 21.10, the FBAR device 2105 and the connection pads.

[00152 J FIG. 31 illustrates the substrate of FIG. 30, after process step 846 has been performed. At process step 846, portions of the AJN layer 125 are etched adjacent the FBAR device and the SAW device, in particular, the substrate undergoes a photolithography and etching process in which the AJN layer 125 is patterned and etched to form release holes 3105 _» which mechanically isolate the FBAR device and the SAW device from each other, and from th surrounding structure. The release holes 3105 provide partial isolatio which can improve a quality factor of the FBAR device and the SAW device. In preferred embodiments, the device shown i FIG. 31 is considered to be an end device.

100153 j FIG. 32 is a flow diagram illustrating example CMOS fabrication process steps used to form an JC structure according to another embodiment of the present in vention . These process steps are described in farther detail with reference to FIG. 33 through FIG. 46, which illustrate the structure after each process step. The figure that is relevant to each process step is identified in each box of the flow diagram. Initially, process steps 802 to 826 are performed. These process steps were previously described with reference to FIGS. 9 to 21 .

[00154] FIG. 33 illustrates the substrate of FIG. 21 , after process step 860 has been performed. At process step 860, a protective layer 2.120 is deposited in the acoustic openings 1905 to fill the areas above the FBAR device 2105 and the SAW device 21 10. The protective layer 2120 is then subjected to chemical-mechanical-polishing (CMP) to platiarize the protective layer 2320 in line with the surface formed by the BPSG 1LD oxide layers 1810. The proteciive layer 2120 is preferably a layer of plasma enhanced chemical vapor deposition (PECVD) boro-phospho-silicate glass (BPSG). The protective layer 2120 protects the A1N layer 125, the FBAR device 2105 and the SAW device 21 10 during the remainder of the process. [00155J FIG. 34 illustrates the substrate of F G. 33, after process step 862 has been performed. At process step 862, contact holes 2205 are formed in the substrate as per process step 828. The contact holes 2205 extend towards the Al ^' N layer 125.

[00156] FIG. 35 illustrates the substrate of FIG. 34, after process step 864 has been performed At process step 864, a .metallic layer 2305 is formed on the substrate as per process step 830. The metallic layer 2305 can be formed of one layer or several layers and can have a thickness of about Ι ηι.

[00157] FIG. 36 illustrates the substrate of FIG. 35, after process step 866 has been performed. At process step 866, an inter-layer dielectric (ILD) 2310 is formed on the substrate then a silicon nitride layer 2320 is formed on the substrate. The ILD 2310 is used as a protection layer and the silicon nitride layer 2320 is used as a hard-mask layer for subsequent trench etching. For example, the ILD is a layer of phospho-silicate glass (PSG) 2310 and can have a thickness of 4μιη that is subsequently C Ped and ptanarized to a thickness of 2μηχ For example, the silicon nitride layer 2320 can have a thickness of 200nm to 500nm.

[00158] FIG. 37 illustrates the substrate of FIG. 36, after process step 868 has been performed. At process step 868, trenches 2330 are formed in the substrate. The trenches 2330 form barriers around the FBA device 2105 and SAW device 21 1 .

(00159) FIG. 38 illustrates the substrate of FIG. 37, after process step 870 has been performed. At process step 870, a silicon nitride layer 2340 is formed on the substrate. In particular, the substrate undergoes a blanket deposition of silicon nitride material over substantially an entire surface of the substrate to fill the trenches 2330 and increase the thickness of the silicon nitride layer 2320. The silicon nitride layer 2340 essentially surrounds the acoustic devices 2105 and 2110 and forms an etch-stop when etching the cavit at the end of the process. The silicon nitride layer 2340 also provides a barrier to stop any contaminants that ma enter the cavity potentially migrating to the active transistors and any other active device in the CMOS process. The silicon nitride layer 2340 can have a thickness from, for example, 300nm to 700nm. The silicon nitride layer 2320 and the silicon nitride layer 2340 form a passivation layer 2405. [00160] FIG. 39 illustrates the substrate of FIG. 38, after process step 872 has been performed. At process step 872, a handle wafer 2505 is bonded to the passivation layer 2405 as per process step 834.

[00161 J FIG. 40 illustrates the substrate of FIG. 39, after process step 874 has been performed At process step 874, the temporaiy substrate 135 is removed as per process step 836. In particular, the temporary substrate 135 is removed from the A1N layer 1.25. For the sake of clarity, the substrate is shown inverted in FIG. 40 and in subsequent figures.

[00162] FIG. 41 illustrates th substrate of FIG. 40, after process step 876 has been performed. At process step 876, a blanket layer of high acoustic impedance material 2705 is formed on the substrate as per process step 838. In particular, the blanket laye 2705 is formed over substantially the entire surface of the exposed A1N layer 325.

[00163] FIG. 42 illustrates the substrate of FIG. 41, after process step 878 has been performed. At process step 878, a portion of the blanket layer of high acoustic impedance material 2705 is removed to form a second FBAR electrode 2105 and optionally another IDT 21 10 as per process step 840. Formation of the second FBAR electrode 2105 completes the FBAR device. A SAW device 21.10 is also completed at this stage and if required the other IDT 21 10 is formed.

[00164] FIG. 43 illustrates the substrate of FIG. 42, after process step 880 has been performed. At process step 8 SO, a portion of the A1N layer is removed to form an opening 2905 as per process step 842.

(00165J FIG. 44 illustrates the substrate of FIG. 43, after process step 882 has been performed. At process step 882, connection pads are formed as per process step 844.

[00166| FIG. 45 illustrates the substrate of FIG. 44, after process step 884 has been performed. At process step 884, portions of the A1N layer 125 are etched adjacent the FBAR device and the SAW device as per process step 846. The release holes 3105 formed by the etched portions provide access to the protective layer 21.20. [00167] FIG. 46 illustrates the substrate of FIG. 45, after process step 886 has been performed. At process step 886, the protective layer 2120 under each of the FBAR device 2105 and the SAW device 21.1.0 is etched away to form, cavities 31 10. The etching process can, for example, be a deep reactive-ion etcher (DR3E) using XeF? chemistry. The cavities 3110, and the release holes 3105 formed in process step 884, provide partial isolation which can improve a quality factor of the FBAR. device and the SAW device. In preferred embodiments, the device shown in F G. 46 is considered to be an end device. A skilled addressee will appreciate that FIG. 31 and FIG. 46 show essentially the same end device formed via different process steps.

|00168{ FIG. 47 is a flow diagram of an example of a method 4700 of integrating a CMOS device and a piezoelectric device, such as an FBAR device and/or a SAW device, using a SOTFANOS substrate, which is a. low electrical conductivity, high thermal conductivity, and piezoelectric substrate. The method 4700 comprises the steps below.

|00169| At a step 4710, a SOTFANOS substrate such as the SOTFANOS substrate 120 of FIG. 2, which is a low electrical conductivity, high thermal conductivity; and piezoelectric substrate, is provided as the starting substrate of any CMOS fabrication process of any CMOS manufacturer.

100] 70} At a step 4720, a CMOS device is formed o a silicon layer of th SOTFANOS substrate. The CMOS device can comprise any suitable arrangement of active or passive devices, o both, and is formed starting with, for example, a silicon layer of the SOTFANOS substrate and using any CMOS fabrication process of any CMOS manufacturer.

[001.71] At step 4730, a piezoelectric device, such as an FBAR device or a SAW device, is formed starting with an A1N layer of the same SOTFANOS substrate and using the same CMOS fabrication process. FIG, 8A(i) through FIG. 46 describe two examples of forming a CMOS device (e.g., an n.-type FET), an FBAR device and a SAW device on the same SOTFANOS substrate.

[00172} As a result, a CMOS article (e.g., an integrated circuit) and a piezoelectric device is formed on a SOTFANOS substrate, such as the SOTFANOS substrate 120 of FIG. 2, wherein the CMOS article provides high heat dissipation because of the SOTFANOS substrate 120, which is a high thermal conductivity SOI substrate that has piezoelectric properties. The CMOS article and piezoelectric device formed on the SOTFANOS substrat ca include CMOS integrated circuits or devices that are higher power or have higher performance than is otherwise possible on conventional SOI substrates. This is because of the high heat dissipation that is possible through the AIN layer of the SOTFANOS substrate. Accordingly, the CMOS article (e.g., an integrated circuit) and the piezoelectric device are provided with increased thermal management capability as compared with CMOS integrated circuits that are fabricated on conventional SOI substrates, which have poor thermal conductivity and poor piezoelectric properties.

[00173] Accordingly, the method 4700 is an example of a process of forming a CMOS device and a piezoelectric device on a low electrical conductivity, high thermal conductivity, and piezoelectric substrate using a CMOS fabrication process, which reduces the complexity and cost of implementing both CMOS technology, and piezoelectric technology, such as SAW and FBAR technology, as compared with usin conventional substrates and methods.

[00174] The mobile telephone is an example of an application that may benefit from the CMOS integrated circuit in combination with an FBAR device and or a SAW device formed on a SOTFANOS substrate. In a conventional mobile telephone, one or more FBAR devices and or SAW devices are typically installed, wherein each FBAR device and or SAW dev ice is a discrete component that is manufactured and installed separately from other CMOS integrated circuit devices present in the mobile telephone. By enabling piezoelectric devices such as FBAR devices and or SAW devices to be formed together with CMOS integrated circuit devices enables a significant reduction in cost and complexity to the mobile telephone manufacturing process when compared with separately manufacturing such devices. Additionally, FBAR devices and SAW devices are able to more efficiently utilize valuable real estate within a mobile telephone as compared with methods of the prior art. Using the method of integrating CMOS devices, SAW devices and FBAR devices o a single SOTFANOS substrate, the one or more FBAR devices and or SAW devices may be integrated together with CMOS integrated circuit devices on a common SOTFANOS substrate i a mobile telephone, thereby significantly reducing cost, complexity, and size,

[00175] In this specification, adjectives such as first and second, and the like may be used solely to distinguish one element or action from another element or action without necessarily requiring or implying any actual such relationship or order. Where the context permits _* reference to an integer or a component or step (or the like) is not to be interpreted as being limited to only one of that integer, component, or step, but rattier could be one or more of that integer, component, or step etc.

[00176] The above description of various embodiments of the present invention is provided for purposes of description to one of ordinary skill in the related art. it is not intended to be exhaustive or to limit the invention to a single disclosed embodiment. As mentioned above, numerous alternatives and variations to the present invention will be apparent to those skilled in the art of the above teaching. Accordingly, while some alternative embodiments have been discussed specifically, other embodiments will be apparent or relatively easil developed by those of ordinary skill in the art The invention is intended to embrace all alternatives, modifications, and variations of the present invention that have been discussed herein, and other embodiments that fall within the spirit and scope of the above described invention,

[00177] In this specification, the terms "comprise", "comprises", "comprising" or similar terms are intended to mean a non-exclusive inclusion, such that a system, method or apparatus that comprises a list of elements does not include those elements solely, but ma well include other elements not listed.

[00178] The reference to any prior art in this specification is not, and should not be taken as, an acknowledgement or any form of suggestion that the prior art forms part of the commo general knowledge.