BACKGROUND

[0001 ] A balun, sometime referred to as a balun transformer, is a two port device or circuit that transforms a signal from a balanced transmission line into a signal for an unbalanced transmission line and vice versa. The balun has an unbalanced port, referenced to ground, and a balanced port with two terminals - each referenced to the other. This is generally described in U.S. Patent 8,638,181 to Gerst, et al. , which is hereby incorporated by reference for all purposes. Balun transformers are used to transform balanced and unbalanced signals in, for example, antenna feed circuitry and push-pull amplifiers.

[0002] The "Guanella balun" is a well-known circuit configuration that is

characterized by its impedance ratios. More specifically, an x:y Guanella balun has an unbalanced port impedance that is x/y times its balanced port impedance where

Guanella baluns with ratios of 1 :1 , 1 :4 and 4:1 are common. Known Guanella baluns use magnetic material in order to increase the impedance seen by common mode currents as a higher common mode impedance improves the balun performance.

[0003] As discussed in U.S. Patent 9,276,056 to Akhtar, et al., which is hereby incorporated by reference for all purposes, radio frequency (RF) circuitry uses differential signaling to eliminate common mode noise and increase dynamic range. The signals received by an antenna, or transmitted by an antenna, however, are single- ended and a balun is implemented to convert from single-ended to differential or from differential to single-ended. In addition to providing signal conversion, baluns also provide impedance transformation between preceding and following stages for maximizing power and signal transfer.

[0004] Akhtar, et al., also disclose a balun having a differential primary (or secondary) inductor winding and a single-ended secondary (or primary) inductor formed in a stacked configuration. The balun is formed using layers of metal available in a CMOS fabrications process.

[0005] What is needed, however, is an improved balun device.

SUMMARY

[0006] In one aspect of the present disclosure, a Guanella balun comprises a substrate; a first pair of first and second generally planar coupled coils, interleaved with one another, and formed on the substrate by a CMOS process, each coil comprising multiple turns and having a respective input and output, the interleaved coils including a first plurality of crossings between turns of the respective coils, wherein each of the crossings of the first plurality of crossings is structured to match an impedance on each side of the crossing; a second pair of third and fourth generally planar coupled coils, interleaved with one another and formed on the substrate by the CMOS process, each coil comprising multiple turns and having a respective input and output, the interleaved coils including a second plurality of crossings between turns of the respective coils, wherein each of the crossings of the second plurality of crossings is structured to match an impedance on each side of the crossing; and an inductive coil formed on the substrate by the CMOS process, the inductive coil having first and second ends, wherein the output of the first coil is coupled to the input of the third coil and the first end of the inductive coil, and wherein a first diameter of the first pair of interleaved coils and a second diameter of the second pair of stacked coils are different from one another.

[0007] In one aspect of the Guanella balun, a ratio of the first diameter to the second diameter is not an integer value. In another aspect, a shape of the inductive coil is one of rectangular or octagonal.

[0008] In one aspect of the Guanella balun, a width of a coil at each crossing and a spacing between the coils in each pair of interleaved coils are structured to provide the matched impedances.

[0009] In one aspect of the Guanella balun, a first switch is configured to, in a first state, couple a first section of the first coil to a second section of the first coil and, in a second state, couple the first section of the first coil to a first node; a second switch is configured to, in a first state, couple a first section of the second coil to a second section of the second coil and, in a second state, couple the first section of the second coil to a second node; a third switch is configured to, in a first state, couple a first section of the third coil to a second section of the third coil and, in a second state, couple the first section of the third coil to a third node; a fourth switch is configured to, in a first state, couple a first section of the fourth coil to a second section of the fourth coil and, in a second state, couple the first section of the fourth coil to a fourth node; a fifth switch is configured to, in a first state, couple the second section of the first coil to the first section of the third coil and, in a second state, couple the first section of the third coil to the first node; a sixth switch is configured to, in a first state, couple the second section of the third coil to a first output node and, in a second state, couple the first output node to the second node; a seventh switch is configured to, in a first state, couple the second section of the second coil to the first section of the fourth coil and, in a second state, couple the first section of the fourth coil to the third node; and an eighth switch is configured to, in a first state, couple the second section of the fourth coil to a second output node and, in a second state, couple the second output node to the fourth node.

[0010] Another aspect of the Guanella balun includes a first switching circuit coupled to the first coil and configured to, in a first state, bypass a section of the first coil; a second switching circuit coupled to the second coil and configured to, in a first state, bypass a section of the second coil; a third switching circuit coupled to the third coil and configured to, in a first state, bypass a section of the third coil; and a fourth switching circuit coupled to the fourth coil and configured to, in a first state, bypass a section of the fourth coil.

[0011 ] In another aspect of the present disclosure, a Guanella balun comprises a substrate; a first pair of first and second generally planar coupled coils, interleaved with one another, and formed on the substrate by a CMOS process, each coil comprising multiple turns and having respective first and second ends, the interleaved coils including a first plurality of crossings between turns of the respective coils, wherein each of the crossings of the first plurality of crossings is structured to match an impedance on each side of the crossing; a first output node coupled to the second end of the first coil; a second output node coupled to the second end of the second coil; an inductive coil formed on the substrate by the CMOS process, the inductive coil having a first end and a second end, the first end of the inductive coil coupled to the first output node; a first switching circuit coupled to the first coil and configured to, in a first state, bypass a section of the first coil; and a second switching circuit coupled to the second coil and configured to, in a first state, bypass a section of the second coil.

[0012] Each of the switches further comprises one or more of: at least one FET device; a pin diode switch; or a bipolar transistor (BJT).

[0013] Further, an aspect of the present disclosure is directed to a Guanella balun comprising: a substrate; a first pair of first and second generally planar coupled coils, interleaved with one another, and formed on the substrate by a CMOS process, each coil comprising multiple turns and having respective first and second ends, the interleaved coils including a first plurality of crossings between turns of the respective coils, wherein each of the crossings of the first plurality of crossings is structured to match an impedance on each side of the crossing; a first output node coupled to the second end of the first coil; a second output node coupled to the second end of the second coil; an inductive coil formed on the substrate by the CMOS process, the inductive coil having a first end and a second end, the first end of the inductive coil coupled to the first output node; a first switching circuit coupled to the first coil and configured to, in a first state, bypass a section of the first coil; and a second switching circuit coupled to the second coil and configured to, in a first state, bypass a section of the second coil.

[0014] In one aspect, the first switching circuit comprises a first switch configured to, in a first state, couple a first section of the first coil to a second section of the first coil and, in a second state, couple the first section of the first coil to a first node; a second switch configured to, in a first state, couple the second end of the first coil to a first output node and, in a second state, couple the first output node to the first node; a third switch configured to, in a first state, couple a first section of the second coil to a second section of the second coil and, in a second state, couple the first section of the second coil to second node different from the first node; and a fourth switch configured to, in a first state, couple the second end of the second coil to a second output node and, in a second state, couple the second output node to the second node.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Various aspects of the disclosure are discussed below with reference to the accompanying figures. It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn accurately or to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity or several physical components may be included in one functional block or element. Further, where considered appropriate, reference numerals may be repeated among the drawings to indicate corresponding or analogous elements. For purposes of clarity, not every component may be labeled in every drawing. The Figures are provided for the purposes of illustration and explanation and are not intended as a definition of the limits of the disclosure. In the Figures:

[0016] Figure 1 is an electrical schematic diagram of a Guanella balun device in accordance with an aspect of the present disclosure;

[0017] Figure 2 is a representation of the Guanella balun device of Figure 1 implemented on a CMOS substrate;

[0018] Figure 3 is a representation of one pair of coupled coils implemented in CMOS in accordance with an aspect of the present disclosure;

[0019] Figure 4 is a close-up view of a crossing of coupled coils as presented in Figure 3;

[0020] Figure 5 is a tunable Guanella balun device in accordance with another aspect of the present disclosure; and

[0021 ] Figure 6 is a switching circuit in accordance with an aspect of the present disclosure. DETAILED DESCRIPTION

[0022] Details are set forth in order to provide a thorough understanding of the aspects of the disclosure. It will be understood by those of ordinary skill in the art that these may be practiced without some of these specific details. In other instances, well- known methods, procedures, components and structures may not have been described in detail so as not to obscure the aspects of the disclosure.

[0023] Generally, and as will be described in more detail below, one aspect of the present disclosure is directed to a Guanella topology balun/unun impedance

transformer containing cascaded, i.e. , series-coupled, coils implemented in RF CMOS technology as, for example, traces on a substrate. In one aspect, shunt inductive loading is provided and the cascaded coils are of different sizes. Advantageously, the shunt inductive loading maximizes low frequency performance and the cascade of coils of different sizes enables a large resonance-free bandwidth of operation.

[0024] Referring to Figure 1 , which is an electrical schematic a Guanella balun device 100 in accordance with an aspect of the present disclosure includes a first coil pair circuit 104 including a first coil 105 and a second coil 106, a second coil pair circuit 108 including a third coil 109 and a fourth coil 110, and an inductive coil 112. Each of the first and second coil pair circuits 104, 108 has respective first and second input nodes (116-1 , 116-2)(124-1 , 124-2) and first and second output nodes(120-1 , 120- 2)(128-1 , 128-2). The first input node of the second coil pair circuit is coupled to the first output node of the first coil pair circuit and the second input node of the second coil pair circuit is coupled to the second output node of the first coil pair circuit. The inductive coil is coupled between the first output of the first coil pair circuit and a ground node 130.

[0025] Generally, the device 100 operates with the first and second input nodes of the first coil pair circuit configured as a single-ended port PS where the first input is arranged to receive/transmit a single-ended signal and the second input port is coupled to ground. The first and second output nodes of the second coil pair circuit are configured as a differential port PD where the first output node is a positive node PD+ and the second output node is a negative node PD-. As shown, a reference node 132, i.e. , coupled to ground, is included. As the device 100 is operable bi-directionally, as understood by those of ordinary skill in the art, the differential port PD can transmit or receive a differential signal.

[0026] In one aspect of the present disclosure, the device 100 is implemented in CMOS, per known manufacturing processes. Referring now to Figure 2, a substrate 204 has each of the first and second coil pair circuits 104, 108 provided thereon as a pair of first and second generally planar coupled coil traces (105, 106), (109, 110), interleaved with, i.e.,“crossed-over” or“crossed-under,” one another, and formed on the substrate 204 by a known CMOS process as is well understood by those of ordinary skill in the art.

[0027] Each coil trace 105, 106, 109, 110 comprises multiple turns and the interleaved coils 105, 106 of the first coil pair circuit 104 include a first plurality of crossings 208 between turns of the respective coils. The interleaved coils 109, 110 of the second coil pair circuit 108 includes a second plurality of crossings 212 between turns of the respective coils 109, 110. Advantageously, each of the crossings 208, 212 of the first and second pluralities of crossings is structured to match an impedance on each side of the respective crossing 208, 212. The inductive coil 112 is also formed on the substrate as a trace by the CMOS process and, per the schematic in Figure 1 , the output 120-1 of the first coil 105 is coupled to the input of the third coil 109 and the first end of the inductive coil 112. Further, a ground plane 130 is provided on the substrate.

[0028] In one aspect, the device 100 is formed using metal layers available in, for example, a digital CMOS fabrication process, as shown in Figure 3, where the first or second coil is formed at a level of a single available thick copper (Cu) metal layer, and the other coil is formed at a level of a single available thick aluminum (Al) top metal bonding layer. The crossovers (cross-unders) are formed using available underlying thin metal layers. [0029] A first diameter D1 of the first pair of interleaved coils 104 and a second diameter D2 of the second pair of interleaved coils 108 are different from one another.

In one aspect of the present disclosure, the first diameter D1 is larger than the second diameter D2. Further, the diameters of the two are set such that a ratio D1 :D2 is not an integer value.

[0030] In one aspect of the present disclosure, a general shape of the inductive coil is rectangular although it could be implemented as an octagonal.

[0031 ] In an aspect of the present disclosure, impedance matching is provided in the layers of traces that cross over each other as will be discussed with reference to Figure 4, a close-up of a crossover portion 208 of a coil trace. The impedance is matched by selecting values for a width W of the trace 105 that“crosses under,” a distance T between the coils and a linear gap G from where the“crossing under” trace 105“ends” or“stops.” Each of these values can be adjusted to compensate for a change in any of the others. As is known in the art, the impedance value can be determined by the use of known CAD modeling software tools with prototypes being made to confirm the modeling and the values.

[0032] Advantageously, the“cascade” of multiple coil sizes, as set forth above, provides for large resonance-free bandwidths.

[0033] In another aspect of the present disclosure, referring now to Figure 5, an electrical schematic, a tunable Guanella balun device 500 in accordance with an aspect of the present disclosure includes a first switched coil pair circuit 504 including a first coil 505 and a second coil 506, a second coil pair circuit 508 including a third coil 509 and a fourth coil 510, and a switched inductive coil 512. Each of the first and second switched coil pair circuits 504, 508 has respective first and second input nodes (516-1 , 516-2)(524-1 , 524-2) and first and second output nodes(520-1 , 520-2)(528-1 , 528-2). The first input node of the second switched coil pair circuit is coupled to the first output node of the first switched coil pair circuit and the second input node of the second switched coil pair circuit is coupled to the second output node of the first switched coil pair circuit. The switched inductive coil is coupled between the first output of the first switched coil pair circuit and a ground node. The device 500 is implemented in CMOS per known processes.

[0034] Each coil in the first and second switched coil pair circuits 504, 508 includes sub-sections and respective switches to couple or decouple the sub-sections from one another. Accordingly, the first coil 505 includes sub-sections 505-1 , 505-2 and switches SW505-1 , SW505-2, as shown. The second coil 506 includes sub-sections 506-1 , 506-2 and switches SW506-1 , SW506-2, as shown. The third coil 509 includes sub-sections 509-1 , 509-2 and switches SW509-1 , SW509-2, as shown. The fourth coil 510 includes sub-sections 510-1 , 510-2 and switches SW510-1 , SW510-2, as shown. The switches are configured to, in one state, couple the respective sub-sections in series with one another and, in another state, bypass, i.e. , isolate or operatively remove, one of the sub sections.

[0035] Similarly, the switched inductive coil 512 includes a first coil sub-section 512- 1 and a second coil sub-section 512-2 with a switch SW512 configured to, in one state, couple the first and second coil sub-sections in series with one another and, in another state, bypass, i.e., isolate, the respective second coil sub-section.

[0036] Each of the first and second switched coil pair circuits 504, 508 is provided as a pair of first and second generally planar coupled coil traces, interleaved with one another, and formed on a substrate by a CMOS process similar to that which has been described above. Each coil trace comprises multiple turns and has a respective first and second end, i.e., an input and output.

[0037] Advantageously, the switched coil pair circuits, due to the isolating function of the switches, minimizes high end losses. The ability to switch sections of the device 500 in and out allows for adjusting an operating bandwidth over a wide frequency range in order to terminate the second harmonic of an amplifier and also increase overall efficiency.

[0038] Advantageously, the switched inductive coil provides for improved common mode rejection. [0039] Each of the switches may be implemented, in one non-limiting example, with two FETs 604, 606 arranged as shown in Figure 6 and also implemented in CMOS. Alternatively, the switches may be implemented as a pin diode switch or a bipolar transistor switch.

[0040] Generally, the device 500 operates with the first and second input nodes of the first switched coil pair circuit 504 configured as a single-ended port PS where the first input port is arranged to receive/transmit a single-ended signal and the second input port is coupled to ground. The first and second output nodes of the second switched coil pair circuit 508 are configured as a differential port PD where the first output node is a positive node PD+ and the second output node is a negative node PD-. As shown, a reference node 532, coupled to ground, is included. As the device 500 is operable bi-directionally, as understood by those of ordinary skill in the art, the differential port PD can transmit or receive a differential signal.

[0041 ] The interleaved coil pairs (505, 506) (509, 510) include a first plurality of crossings between turns of the respective coils. Advantageously, each of the crossings of the first plurality of crossings is structured to match an impedance on each side of the crossing. The switched inductive coil 512 is also formed on the substrate as a trace by the CMOS process and has first and second ends. As per the schematic in Figure 5, the output of the first coil is coupled to the input of the third coil and the first end of the inductive coil. Further, a ground plane is provided on the substrate.

[0042] Further, aspects of the present disclosure are advantageous over known multi-tapped magnetically coupled baiuns/transformers or a known multi-tapped

Guanella balun as both of these approaches only change the impedance transformation ratio and not the bandwidth.

[0043] Generally, the device 500 operates with the first and second input nodes of the first coil pair circuit configured as a single-ended port PS where the first input is arranged to receive/transmit a single-ended signal and the second input port is coupled to ground. The first and second output nodes of the second coil pair circuit are configured as a differential port PD where the first output node is a positive node PD+ and the second output node is a negative node PD-. As shown, a reference node, i.e. , ground, is included. As the device 100 is operable bi-directionally, as understood by those of ordinary skill in the art, the differential port PD can transmit/receive a differential signal.

[0044] It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangement of the components set forth herein or illustrated in the drawings as it is capable of implementations or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description only and should not be regarded as limiting.

[0045] Certain features, which are, for clarity, described in the context of separate implementations, may also be provided in combination in a single implementation. Conversely, various features, which are, for brevity, described in the context of a single implementation, may also be provided separately or in any suitable sub-combination.

[0046] The present disclosure is illustratively described in reference to the disclosed implementations. Various modifications and changes may be made to the disclosed implementations by persons skilled in the art without departing from the scope of the present disclosure as defined in the appended claims.

What is claimed is: