Title:
CMOS LEVEL SHIFTER CIRCUIT DESIGN
Document Type and Number:
WIPO Patent Application WO/2010/027915
Kind Code:
A3
Abstract:
A level shifting circuit (402) has a pair of assist circuits (404, 40S). The level shifting circuit (402) includes an input point (420), two output points (416/418), a pair of cross-coupled PMOS transistors (412, 414) coupled to the output points (416, 418), and a pair of NMOS transistors (424, 426, 432, 434) coupled between the input and output points (420). Each assist circuit (404, 406) includes a pair of PMOS transistors (424, 426, 432, 434), one responsive (424, 432) to an input applied to the input point (420), the othe (426, 434) r responsive to the drain voltage of one of the NMOS transistors (408, 410). The assist circuit (404, 406) s temporarily weaken the cross-coupled PMOS transistors (412, 414) when an input changes from low to high, or from high to low. The assist circuits also transiently boost the output.
Inventors:
CHABA RITU (US)
PARK DONGKYU (US)
JUNG CHANGHO (US)
YOON SEI SEUNG (US)
PARK DONGKYU (US)
JUNG CHANGHO (US)
YOON SEI SEUNG (US)
Application Number:
PCT/US2009/055339
Publication Date:
June 03, 2010
Filing Date:
August 28, 2009
Export Citation:
Assignee:
QUALCOMM INC (US)
CHABA RITU (US)
PARK DONGKYU (US)
JUNG CHANGHO (US)
YOON SEI SEUNG (US)
CHABA RITU (US)
PARK DONGKYU (US)
JUNG CHANGHO (US)
YOON SEI SEUNG (US)
International Classes:
H03K3/356; H03K3/012
Foreign References:
| US5659258A | 1997-08-19 | |||
| US20040246038A1 | 2004-12-09 | |||
| US5444396A | 1995-08-22 | |||
| JP2001068991A | 2001-03-16 |
Attorney, Agent or Firm:
TALPALATSKY, Sam (San Diego, California, US)
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