Title:
CMOS RF POWER LIMITER AND ESD PROTECTION CIRCUITS
Document Type and Number:
WIPO Patent Application WO/2020/113175
Kind Code:
A3
Abstract:
An RF power limiter and ESD protection circuit has a set of two CMOS FETs each configured to perform a diode function with a defined forward voltage and arranged in an anti-parallel configuration and coupled between the input terminal and the ground terminal. When an RF signal is applied symmetrically to the input terminal and ground terminal it becomes symmetrically attenuated when the signal level exceeds the defined forward voltage of the diode configured CMOS FETs. In the ESD protection mode one of the CMOS FETs acts as a grounded gate NMOS transistor with SCR action to provide for mitigation of voltage and current over-stress of transistors utilized in RF transceiver circuits. Generally, the circuit architectures allow input power levels to be limited to an extent that reliable operation can be maintained.
Inventors:
GORBACHOV OLEKSANDR (US)
ZHANG LISETTE (US)
MILKOVITS STEPHEN (US)
ZHANG LISETTE (US)
MILKOVITS STEPHEN (US)
Application Number:
PCT/US2019/063868
Publication Date:
July 09, 2020
Filing Date:
November 29, 2019
Export Citation:
Assignee:
OCTOTECH INC (US)
International Classes:
H01L27/02; H03G11/02; H04B1/18
Foreign References:
| US20110187475A1 | 2011-08-04 | |||
| US20130026550A1 | 2013-01-31 | |||
| US6094088A | 2000-07-25 | |||
| EP1498998A1 | 2005-01-19 |
Attorney, Agent or Firm:
KARICH, Eric (US)
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