FOR ENHANCING THE ACCURACY OF DIGITAL DATA

COMMUNICATED THROUGH A NETWORK

This subject matter of this document is a continuation-in-part of and daims priority to the following copending and commonly assigned U.S. patent applications, all of which are incorporated herein by reference: (a) application entitled, "Rob Bit Compensation System And Method Associated With A Transmitter Or Codec," filed August 23, 1996, and assigned ser. no. 08/701,849;

(b) apphcation entitled, "Noncooperative Feedback System And Method For A Compensation System Assodated With A Transmitter Or Codec," filed August 23, 1996, and assigned ser. no. 08/702,023; and (c) apphcation entitled, "Cooperative Feedback System And Method For A Compensation System Associated With A Transmitter Or Codec," filed August 23, 1996, and assigned ser. no. 08/697,371.

FIELD OF THE INVENTION

The present invention generally relates to data communications and, more particularly, to a compensation system and method for improving the accuracy of digital data that is communicated through a network, for example but not limited to, a telephonic network. In essence, the compensation system and method are employed in connection with the digital data transmitted to a network, prior to transmission, in order to increase the accuracy of the digital data that is ultimately received from the network by minimizing loss, or error, caused by digital attenuation quantization (DAQ) and rob bit signaling (RBS).

BACKGROUND OF THE INVENTION

A telephone network is often used as an interface between communication devices, such as modulators/demodulators (modems). Some modems are digital in nature and others are analog. Specifically, a digital modem is a device that communicates digital data by using digital signals that rephcate analog waveforms. In contrast, an analog modem is a device that communicates digital data by encoding the data on analog waveforms.

Fig. 1 shows a typical telephone network 99 for interconnecting a digital modem 101 and an analog modem 102. The digital modem 101 is usually interconnected with a digital network 113 via digital connections 112a, 112b.

For instance, the digital modem 101 may be interconnected to a digital network 113, such as a public switch telephone network (PSTN), via a Local Exchange Carrier (LEC) subscriber loop. The digital network 113 may comprise, among other things, a Tl carrier system, a basic rate or primary rate Integrated Services Digital Network (ISDN), a fiber optic cable network, a coaxial cable network, a satellite network, or even a wireless digital communications network. Communications over the digital network 113 are conducted in accordance with a pulse code modulation (PCM) scheme. Channel capacity through these digital facilities is typically between 56 and 64 kilobits per second (kb/s). Coding of the signals is also employed so that compression and a constant signal/distortion performance over a wide dynamic range is achieved for optimal transmission of voice signals.

A commonly used coding technique is nonlinear mu-law coding. The linear amplitude L corresponding with each code word is encoded, or converted to, a mu-law code word by the following equation:

M=(L+33)*2 ^» - ^N (Eq. 1)

where M is the mu-law magnitude (e.g.. 4 bits), L is the hnear amplitude (e.g., 14 bits), and N is the mu-law segment, or segment (e.g., 3 bits). The mu-law code word is decoded, or converted to, a hnear code word-as follows:

L={(2M+33)2 ^N -33} (Eq. 2) The digital network 113 is in turn interconnected with another LEC subscriber loop that indudes a coder/decoder (codec) 106. The codec 106 is interconnected with the digital network 113 via digital connections 114a, 114b.

The codec 106 is often situated at a telephone company office or along a street near the analog modem subscriber in a subscriber loop carrier (SLC) device. The codec 106 provides an interface between the digital network 113 and an analog telephone connection 118, sometimes referred to as a copper loop. For communications in the direction from the digital network 113 to the analog modem 102, the codec 106 indudes a mu-linear digital-analog converter (DAC) 109. The converter 109 converts nonlinear mu-law levels to a linear analog signal.

For communications in the direction from the analog modem 102 to the digital network 113, the codec 106 includes a linear-mu analog- digital (ADC) converter 107. The converter 107 converts the linear analog signal to nonlinear mu-law code words. A hybrid 103 is in communication with the DAC and ADC via respective low pass filters (LPFs) 111, 105. The hybrid 103 serves to separate the bidirectional analog signals from the analog telephone connection 118 into unidirectional transmit and receive analog signals sent to and received from the ADC 107 and the DAC 109, respectively. Furthermore, the analog modem 102 is connected to the analog telephone connection 118 and communicates analog signals therewith. Thus,

communications occur between the digital modem 101 and the analog modem 102 by way of the digital network 113 and the codec 106.

The encoding and decoding processes that are imposed upon a communication signal adversely create a certain amount of error in the ultimately received signal due to digital attenuation quantization (DAQ), or digital pad quantization. This quantization error inherently results from- the fact that the original data signal typically is defined by a larger number of bits than the mu-law code that is derived therefrom, transmitted, and then decoded. Therefore, when the mu-law code is decoded into the received signal, the received signal does not exactly match the transmitted signal due to quantization error. In most connections, the digital network 113 attenuates signals transmitted on connection 114b to codec 106. These signals are digital and are converted to linear format, then attenuated, and finally converted back to mu-law format. This second mu-law conversion introduces a second quantization error. DAQ loss undesirably causes the distortion of the recei ed signal to increase and the performance of the communications system to decrease.

DAQ loss becomes significantly worse when the common technique of loss insertion is used to mitigate the adverse effects of echo produced at hybrids 103 of Fig. 1. Loss insertion is used in the PSTN to control echo impairment during speech calls through a reduction in the signal amplitude of the transmitted analog signal, and hence, a corresponding reduction in the distortion amplitude. When a signal is to be transmitted over the network 113. a standardized transmission loss (typically, 6 dedbels (dBs) for most networks, and 3 dB for the rest) is purposefully inserted into the signal path. The signal amplitude of the received signal is then recovered in the called party's modem

via a well known equalization process which scales the signal amplitude back up to its expected level.

In addition to loss resulting from DAQ, loss can also result from a method known as rob bit signaling (RBS). RBS is utilized in the digital network 113 to communicate on-hook/off-hook status between the modems 101,

102 and the digital network 113. RBS forces the least significant bit (LSB) of every nth segment, where n is typically 6 or 24, to a constant logic level, either logical 1 or 0. Unfortunately, RBS causes the block error rate of data transfers to increase and the peak error to increase from 0.5 LSB to 1.5 LSB. RBS can occur in the network before and/or after DAQ.

Hence, there exists a need in the industry for an improved compensation system and method to m---ιim--ze both the DAQ loss (which loss is made worse by use of digital loss insertion techniques) and RBS loss imposed upon digital data that is transmitted through a digital network.

SUMMARY OF THE INVENTION

The invention provides for a compensation system and method that can be implemented in a transmitter, for compensating digital data prior to transmission through a network, for example, a telephone network, in order to improve the accuracy of the digital data that is ultimately received from the network by minimizing the error imposed upon the data by digital attenuation quantization (DAQ) and rob bit signaling (RBS).

In terms of architecture, the combined DAQ/RBS compensation system can be employed within a transmitting device, such as a modem, connected with the network. Two embodiments of the compensation system are described herein, and one may be preferred over the other, depending upon whether RBS

occurs before or after DAQ in the network. If desired, both embodiments could be implemented in a single transmitter, and then one or both could be selected and used for operation, based upon feedback received during a test tiaining session. In the first embodiment of the combined DAQ RBS compensation system, a first adjustment mechanism, for example, a midtiplie'r, is configured to mathematically combine a DAQ compensation quantity with each segment of the digital data, prior to transmission, in order to enhance accuracy of the received digital data. As an example, a quantity of 1, 1/ 2 , or 1/2 may be multiplied with each segment, depending on feedback that is provided to the compensation system during a series of training or test transmissions. After the DAQ compensation quantity is mathematically combined with the digital data word, the word is communicated to a linear-mu-linear converter, which is configured, in general, to simulate a digital transmission by encoding (e.g., mu- law encoding) each digital data word into a code word and then subsequently decoding (e.g., mu-law decoding) each code word back into a linear digital data word, while taking into account the DAQ compensation quantity during the encoding/decoding process.

In addition, the linear-mu-linear converter includes an RBS compensation system that causes an RBS compensation quantity to be mathematically combined with each RBS segment in order to enhance accuracy of the RBS segments, which typically occur periodically. Apphcation of the RBS compensation corresponds with the frequency of the RBS segments. As an example, one-half of an least significant bit (LSB) may be added to each RBS segment when the RBS logic state is a mark (logical 1), or alternatively, one- half of an LSB may be subtracted from (i.e., add 2's complement) each RBS segment when the RBS logic state is a space (logical 0). A feedback system

advises the combined DAQ/RBS compensation system as to which. segments of outgoing digital data are to have a bit eventually robbed therefrom by the digital network. A second adjustment mechanism, for example, a multipHer, is connected to the linear-mu-linear converter. The second adjustment mechanism mathematically combines the redprocal of the DAQ compensation quantity G with the linear data from the linear-mu-linear converter. Finally, the linear digital data word is passed from the linear ^ι mu- linear converter to a linear-mu converter for conversion into a mu-law code word and transmission to the network. In this way, the loss experienced by the digital data during quantization, RBS, and transmission through the network merely returns the digital data dose to its original precompensated state, resulting in an ultimate received digital output signal with minimal error due to DAQ and RBS.

The second embodiment of the combined DAQ/RBS compensation system has similar architecture to the first embodiment in that the second embodiment comprises a first adjustment mechanism, a linear-mu-linear converter, and a second adjustment mechanism. However, in the second embodiment, the RBS compensation system is not implemented in the linear- mu-linear converter, but is situated after the linear-mu-linear converter, specifically, between the linear-mu converter and the network.

The invention can also be viewed as providing a method for reducing DAQ loss and RBS loss imposed upon digital data that is communicated through a network. In this regard, the method can be broadly summerized as follows: modifying digital data, prior to transmission, so that DAQ loss that is subsequently imposed upon the digital data by a network is reduced by mathematically combining a DAQ compensation quantity to each segment of the digital data; modifying the digital data, prior to transmission, so that

loss resulting from RBS in the network is reduced by mathematically combining an RBS loss compensation quantity with each segment of the digital data that will be modified by RBS; and transmitting the modified digital data to the network. The invention has numerous advantages, a few of which are delineated hereafter, as merely examples.

An advantage of the invention is that it increases the accuracy of digital data communicated through a network by decreasing the amount of error imposed upon the data by both DAQ and RBS. Another advantage of the invention is that it provides for an optimal implementation (first or second embodiment) for minimizing both DAQ and

RBS, the implementation depending upon the order in which DAQ and RBS are implemented in the network. Both embodiments could be implemented in a transmitter, and then one or both could be selected and used for operation, based upon feedback received during a test/training session.

Another advantage of the invention is that data transfer rates of digital data through a network are increased.

Another advantage of the invention is that it can be implemented in any system where DAQ loss and RBS are imposed upon the digital data. Thus, the invention may be employed in, for example, a digital modem, an analog modem, etc..

Another advantage of the invention is that it reduces the RBS induced peak error in a signal that is passed through a digital network that practices

RBS from 1.5 LSB to 1.0 LSB. Another advantage of the invention is that it can detect any number and frequency of RBS frames, even when the digital network includes a plurahty of subnetworks, each of which robs its own bit.

Another advantage of the invention is that the data rate of modem communications can be increased from 28,800 b/s to at least 33,600 b/s.

Another advantage of the invention is that for modems operating at 33,600 bits per second (B/S), the invention reduces the block error rate from at least 0.03 to 0.003 and typically achieves a factor of lOx improvement.

Another advantage of the invention is that it can be implemented with software, hardware, or a combination thereof. Preferably, the invention is implemented in software that is stored in memory and that configures and drives a conventional digital signal processor (DSP). Another advantage of the invention is that it is simple in design, easil implemented in existing modems, and is reliable in operation.

Other objects, features, and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional objects, features, and advantages be induded herein within the scope of .the present invention, as defined by the daims.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale emphasis instead being placed upon clearly illustrating prinriples of the present invention. In the drawings, like reference numerals designate corresponding parts throughout the several views.

Fig. 1 is an electronic block diagram of a possible implementation for coupling together digital and analog modems over a digital network;

Fig. 2A is an electronic block diagram of a possible implementation of a transmit subsystem within the digital modem of Fig. 1 that employs a first

embodiment of the combined DAQ/RBS compensation system of. the present invention;

Fig. 2B is an electronic block diagram of a possible implementation of a transmit subsystem within the digital modem of Fig. 1 that employs a second embodiment of the combined DAQ/RBS compensation system of the present invention;

Fig. 3 is an electronic block diagram of a possible implementation of the RBS compensation system of Figs. 2A and 2B;

Fig. 4 is an electronic block diagram of a possible implementation of a cooperative feedback system for generating a feedback, signal for the compensation systems of Figs. 2A and 2B during an initialization (tiaining) phase to indicate the quality of a transmitted test signal; and

Fig. 5 is an electronic block diagram of a possible implementation of a noncooperative feedback system for generating a feedback signal for the compensation systems of Figs. 2 A and 2B during an initialization (training) phase to indicate the quality of a transmitted test signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The invention provides for a combined DAQ/RBS compensation system 130 (Figs. 2A and 2B) and assodated methodology that can be employed in connection with digital data that undergoes digital attenuation quantization (DAQ) loss and rob bit signaling (RBS) loss when passed through an electronic communication system or network (e.g., PSTN). In essence, the combined DAQ/RBS compensation system 130 rmnimizes the error in the ultimately received digital data that is attributable to DAQ and RBS. Although not required to practice the present invention, the combined DAQ/RBS compensation system 130 (Figs. 2A and 2B) and method of the preferred

embodiment are implemented in a transmit subsystem of a digital modem that is connected to a telephonic digital network, which imposes the DAQ and RBS losses, in order to reduce error in the digital data in a receive subsystem of an analog modem that receives the digital data by way of an analog signal from a telephone line.

A. Combined DAQ/RBS Compensation Method

The unique methodologies employed by the first and second embodiments of the combined DAQ/RBS compensation system 130 (Figs. 2A and 2B, respectively) are broadly summarized, in mathematical terms, as follows. One embodiment may be preferred over the other, depending upon whether RBS occurs before or after DAQ in the network 113.

1. First Embodiment The following discussion pertains to the first embodiment of -the combined DAQ RBS compensation system 130 (Fig. 2A). Initially, the linear data word L is encoded, or converted to, a mu-law code word by the following equation:

M=(G*L+33)*2»-κ (Eq. 3) where M is the mu-law code word (e.g., 4 bits), G is a DAQ compensation quantity (e.g., 14 bits), L is the linear data word (e.g., 14 bits), and N is the mu- law segment, or segment identification (e.g., 3 bits). The DAQ compensation quantity G can be preset in some implementations, but its value is selected during an initialization phase from a library of possible values in the preferred embodiments by the combined DAQ RBS compensation system 130 based upon feedback that is communicated to the combined DAQ/RBS compensation system 130.

Then, if RBS is anticipated on this sample based upon feedback, the mu-law code word is modified as follows:

M=M+0.5 LSB if RBS forces a space LSB (Eq. 4a) - M=M-0.5 LSB if RBS forces a mark LSB (Eq. 4b) Moreover, if during this step, overflow occurs (i.e., addition of the 0.5 LSB causes a shift into another segment), then N is incremented, or N=N+1.

Next, the mu-law code word is converted back to a linear data word as follows:

L={(2M+33)2 ^N -33} (Eq. 5) Finally, the combined DAQ/RBS compensation system 130 (Fig. 2 A) passes the linear data words to a mu-law encoder where the original gain of the signal is restored and where mu-law code words are produced for transmission, as indicated mathematically as follows:

2. Second Embodiment

The following discussion pertains to the second embodiment of the combined DAQ RBS compensation system 130 (Fig. 2B). Initially, the linear data word L is encoded, or converted to, a mu-law code word by the following equation: where M is the mu-law code word (e.g., 4 bits), G is a DAQ compensation quantity (e.g., 14 bits), L is the linear data word (e.g., 14 bits), and N is the mu- law segment, or segment identification (e.g., 3 bits). Next, the mu-law code word is converted back to a linear data word as follows:

L={(2M+33)2 ^N -33} (Eq. 8)

Finally, the combined DAQ/RBS compensation system 130 (Fig. 2B) passes the linear data words to a mu-law encoder where the original gain of the signal is restored and where mu-law code words are produced, as indicated mathematically as follows: M=(L/G+33)*2 ^{8 N} (Eq. 9)

Then, if RBS is antidpated on this sample based upon feedback,- the mu-law code word is modified as follows:

M=M+0.5 LSB if RBS forces a space LSB (Eq. 10a) M=M-0.5 LSB if RBS forces a mark LSB (Eq. 10b) Moreover, if during this step, overflow occurs (i.e., addition of the 0.5 LSB causes a shift into another segment), then N is incremented, or N=N+1.

B. Combined DAQ/RBS 'Compensation System

The architecture of the combined DAQ/RBS compensation system 130 will now be described hereafter with reference to Figs. 2 through 5. In -the preferred embodiment, the combined DAQ/RBS compensation system 130 is implemented in the digital modem 101 (Fig. 1) in order to compensate for and minimize the distortion imposed upon the digital data resulting from quantization and RBS imposed by the digital network 113 (Fig. 1). However, as can be appredated by one ordinarily skilled in the art, the combined

DAQ/RBS compensation system 130 may be employed in assodation with other transmission or transmitter devices and in connection with other types of systems that impose DAQ loss and/or RBS loss.

1. First Embodiment

A first embodiment of the combined DAQ/RBS compensation system 130 will now be described with reference to Fig. 2A. Fig. 2A generally shows an electronic block diagram of a possible implementation of a transmit subsystem 181 that can be situated within the digital modem 101 (Fig. 1) for receiving transmit data 183 from local data terminal equipment (DTE) and communicating it to the digital network 113 (Fig. 1). The elements of the transmit subsystem 181 as well as the combined DAQ/RBS compensation system 130 can be implemented in software, firmware, hardware, or a combination thereof. In the preferred embodiment, the elements of the transmit subsystem 181 as well as the combined DAQ/RBS compensation system 130, as shown in Fig. 2, are implemented in software that is stored in memory and that configures and drives a conventional digital signal processor (DSP). The architecture and functionality of DSPs are well known in the art. Referring to Fig. 2A, the transmit subsystem 181 communicates the transmit data in the form of a binary bit stream from the local DTE to a signal encoder 189 along path 183. The signal encoder 189 is configured to modulate and/or process the transmit data. For this purpose, the encoder 189 may implement, for example, a serial-parallel converter, a filter, a scrambler, a trellis encoder, a modulator, etc., all of which are well known in the art. The signal encoder 189 can employ any suitable modulation and/or signal processing techniques, for example, those recommended by the conventional V.34 standard. When the encoder 189 employs V.34 modulation and signal processing, the data that is output from the signal encoder 189 complies with the well known V.34 protocol so that the data stream corresponds with one of fourteen possible V.34 speeds between 2,400 b/s and 33,600 b/s, inclusive.

The signal encoder 189 drives the linear digital signal to the combined DAQ/RBS compensation system 130 via path 192. In architecture, the combined DAQ/RBS compensation system 130 indudes a compensation selector 194. The compensation selector 194 is configured to receive a feedback signal(s) on connection 112a. The compensation selector 194 processes and decodes the feedback signal to determine the appropriate compensation quantity G to be selected and transmits this quantity G along path 196 to an adjustment mechanism 198, for example but not limited to, a multiplier. From the feedback signal, the compensation selector 194 also identifies RBS segments and whether or not the RBS imposes a mark or space. The foregoing information is forwarded to the linear-mu-linear converter 201, as indicated by reference arrow 153 and as described in more detail hereafter.

As examples of systems for producing the feedback signal(s), a cooperative feedback system 210 and a noncooperative feedback system 240 are described in further detail hereinafter with reference to Figs. 4 and- 5. respectively. Either of these systems 210, 240 can be utilized to produce a suitable feedback signal(s) to assist the combined DAQ/RBS compensation system in selecting an appropriate DAQ compensation quantity G during the initialization phase. In the combined DAQ/RBS compensation system 130 of Fig. 2 A, an adjustment mechanism 198 is configured to combine the compensation quantity G with each segment of the incoming digital data. In the preferred embodiment, this is accomplished by mathematically multiplying each segment of the digital data by the selected DAQ compensation quantity G. In the context of equation (3), this process produces the value (G*L). As mentioned, the combined DAQ/RBS compensation system 130 of the preferred embodiment receives feedback during an initialization phase for aiding it in selecting and

utilizing an appropriate DAQ compensation quantity G for typical steady state operation.

Each compensated data segment of digital data is then relayed to the linear-mu-linear converter 201 along path 202. The linear-mu-linear converter 201 first encodes each digital data segment (e.g., 14 bits) into a mu-law code word (e.g., 4 bits) according to equation (3). If the segment is ari RBS segment, then an RBS compensation quantity is mathematically combined with- the segment in order to minimize the effects of RBS. In the preferred embodiment, 0.5 LSB is added or subtracted from the segment, depending upon whether the RBS imposes a space LSB or a mark LSB, respectively. If overflow occurs, then the segment indicator N is incremented, or N=N+1.

Referring to Fig. 3, the preferred embodiment of the linear-mu-linear converter 201 includes a linear-mu converter 191, which is configured to convert the incoming linear code word to a mu-law code word. A compensation addition mechanism 131 receives the mu-law code word from the linear-mu converter

191. The mechanism 131 indudes successive adders 131a, 131b and is controlled by a compensation control 133. Generally, the compensation addition mechanism 131 receives successive mu-law code words 125 from the converter 191 and to each, it performs one of the following: (a) mathematically combines a zero with the code word 125 to produce a modified code word 137

(i.e., effectively, forwards the code word 125 unchanged but with an additional bit); (b) adds 0.5 LSB to the code word 125 in order to produce a modified code word 137; or (c) subtracts 0.5 LSB (i.e., adds 2's complement of 0.5 LSB, or -0.5 LSB) to the code word 125 in order to produce a modified code word 137. In order to accomplish the aforementioned functionality, the adder 131a of the compensation addition mechanism 131 is configured to add either nothing or +0.5 LSB to each code word 125 in order to generate the modified code word

137, while similarly, the adder 131b is configured to add either nothing or -0.5 LSB to each code word 127 in order to generate the modified code word 137. The foregoing functionality is in accordance with equations (4a) and (4b) discussed hereinbefore. The compensation control 133 controls the adders 131a, 131b, as indicated by respective reference arrows 151, 161, to accomphsh one of-the aforementioned options. Furthermore, the compensation control 13-3 is configured to receive space and mark initialization signals 153a, 153b, which are essentially a bit pattern that identifies which segments are RBS segments. Based upon the foregoing initialization signals 153a, 153b, the compensation control 133 detects when an RBS segment occurs and is configured to advise the compensation addition mechanism 131 when to combine a quantity (i.e., to effectively add or subtract an amount) with the RBS segment in order to enhance the accuracy of the RBS segment. In architecture, the compensation control 133 of the combined DAQ/RBS compensation system 130 has mark RBS logic for identifying an RBS segment having an LSB that is a mark and space RBS logic for identifying an RBS segment having an LSB that is a space. The space and mark RBS logic mechanisms generate respective control signals 151, 161 for the compensation addition mechanism 131. The signals 151, 161 are indicative of whether or not there is an RBS segment and whether the RBS segment either has a space LSB or a mark LSB, respectively.

The mark RBS logic indudes a mark ring counter 146. The mark ring counter 146 is a shift register or other suitable mechanism. The mark ring counter 146 is configured to receive its own output at its data terminal (D). The mark ring counter 146 is preset so that all states match the mark initialization

word 153b and is docked by a dock signal 155 at a rate of preferably 8000 hz to correspond with the segment frequency rate of the incoming signal 125.

In the preferred embodiment, the mark ring counter 146 is an n state device, where n represents the frequency of the RBS segment. Typically, n is 6, 12, or 24. The mark ring counter 146 is shifted one state of n states every segment. In Fig. 3, the mark ring counter 146 shifts to the left so that the most significant bit (MSB) is output at reference arrow 148. When RBS compensation should be applied, the mark ring counter output (i.e., the most significant bit (MSB) of the stored word) exhibits a logical 1, and automatically tracks the RBS segments that have a mark LSB.

The space RBS logic identifies RBS segments having an LSB that exhibits a space. The space RBS logic indudes a space ring counter 156. The space ring counter 156 is a shift register or other suitable mechanism. The space ring counter 156 is configured to receive its own output at its data terminal (D). The space ring counter 156 is preset so that all states match the space initialization (INIT) word 153a and is docked by a dock signal 155 at a rate of preferably 8000 hz to correspond with the segment frequency rate of the jLncoming digital data 125.

In the preferred embodiment, just as with the mark ring counter 146, the space ring counter 156 is an n state device, where n represents the frequency of the RBS segment, and the space ring counter 156 is shifted one of n states every segment. In Fig. 3, the space ring counter 156 shifts to the left so that the MSB is output at reference arrow 158. When space RBS compensation should be apphed, the space ring counter 156 output (i.e., the most significant bit (MSB) of the stored word) exhibits a logical 1 and automatically tracks the

RBS segments that have a space LSB.

Each mu-law code word 137 is forwarded to a mu-linear converter 197, which device is well known in the art and which converts each mu-law code word back to linear format 204.

As a result of the RBS compensation system 129 in Fig. 3, the transmit subsystem can encode each RBS segment so that the maximum possible error in each RBS segment at a receiver is no greater than 1.0 LSB. The possible maximum error in an RBS segment resulting from the encoding/decoding process of the prior art is 1.5 LSB. Almost needless to say, modem performance is significantly improved by the invention during an RBS segment. Further note that multiple RBS bits can occur as the signal passes through multiple switches, multiplexers, or subscriber loop carriers (SLC) assodated with the digital network 113. The ring counters 146, 156 can monitor and compensate for RBS in multiple bit positions.

In accordance with another feature of the invention, in order to save on processing time, the linear-mu-linear converter 201 may be configured- to manipulate only a particular field of each segment, while tracking the other fields, and reconstructing the segment at the end for output. In this regard, each incoming segment typically has three fields: (a) a sign field, (b) a segment field (essentially, a gain); and (c) a quantized code field. The sign and segment fields are left unchanged and are tracked, while the quantized code word field is manipulated by the RBS compensation quantity. Then, after the RBS compensation quantity has been introduced, the sign and segment fields are re- attached. This feature saves processing time and complexity.

Once processing in the linear-mu-linear converter 201 is complete, the DAQ compensation quantity G (previously multiplied with the digital data prior to the conversion of the digital data in the linear-mu-linear converter 201) is removed from the segment of digital data. In the preferred embodiment, this

is accomphshed by relaying each digital data segment along path 204 to an adjustment mechanism 205, for example but not limited to, a multipHer, and by communicating along path 207 the redprocal of the previous DAQ compensation quantity G to the adjustment mechanism 205. In the context of equation (6), this procedure is directed to deriving the quantity L/G. By multiplying the redprocal with the digital data segment, the adjustment mechanism 205 effectively removes the DAQ compensation quantity G previously multipHed with the digital data in adjustment mechanism 198. This leaves the digital data in a modified form that will be returned to near its original state after it experiences the DAQ and RBS assodated with the digital network 113.

Having compensated the digital data for DAQ loss and RBS loss, the digital data is next communicated from the combined DAQ/RBS compensation system 130 to a linear-mu converter 208 via path 209, before it is transmitted to the digital network 113 along path 112b. The linear-mu converter 208, another device which is weU known in the art, converts each incoming linear data word to a mu-law code word in accordance with equation (6) and transfers each mu-law code word to the digital network 113 (Fig. 1) via connection 112b.

2. Second Embodiment

A second embodiment of the combined DAQ/RBS compensation system

130 will now be described with reference to Fig. 2B. Fig. 2B shows a transmit subsystem corresponding with that of Fig. 2A and, for the sake of simpHdty, the discussion set forth previously relative to Fig. 2A is incorporated herein by reference and is equally apphcable to Fig. 2B.

In the second embodiment of the combined DAQ/RBS compensation system 130 of Fig. 2B, the adjustment mechanism 198 is configured to combine

the compensation quantity G with each segment of the incoming digital data. In the preferred embodiment, this is accomphshed by mathematically multiplying each segment of the digital data by the selected DAQ compensation quantity G. In the context of equation (7), this process produces the value (G*L). As mentioned, the combined DAQ/RBS compensation system 130 of the preferred embodiment receives feedback during an initialization phaser for aiding it in selecting and utilizing an appropriate DAQ compensation quantity G for typical steady state operation.

Each compensated data segment of digital data is then relayed to the linear-mu-linear converter 201 along path 202. The linear-mu-linear converter

201 first encodes each digital data segment (e.g., 14 bits) into a mu-law code word (e.g., 4 bits) according to equation (7).

Referring to Fig. 3, the preferred embodiment of the linear-mu-linear converter 201 of the second embodiment indudes a linear-mu converter 191, which is configured to convert the incoming linear code word to a mu-law code word 125. Each mu-law code word 125 is forwarded to a mu-linear converter 197, which device is well known in the art and which converts each mu-law code word 125 back to linear format 204.

Once processing in the linear-mu-linear converter 201 is complete, the DAQ compensation quantity G (previously multipHed with the digital data prior to the conversion of the digital data in the linear-mu-linear converter 201) is removed from the segment of digital data. In the preferred embodiment, this is accomplished by relaying each digital data segment along path 204 to an adjustment mechanism 205, for example but not limited to, a multipHer, and by communicating along path 207 the redprocal of the previous DAQ compensation quantity G to the adjustment mechanism 205. In the context of equation (9), this procedure is directed to deriving the quantity L/G. By

multiplying the redprocal with the digital data segment, the adjustment mechanism 205 effectively removes the DAQ compensation quantity G previously multipHed with the digital data in adjustment mechanism 198. This leaves the digital data in a modified form that will be returned to near its original state after it experiences the DAQ assodated with the digital network

113.

Having compensated the digital data for DAQ loss and RBS loss, the digital data is next communicated from the combined DAQ/RBS compensation system 130 to a linear-mu converter 208 via path 209, before it is transmitted to the digital network 113 along path 112b. The linear-mu converter 208, another device which is well known in the art, converts each incoming Hnear data word to a mu-law code word in accordance with equation (9) and transfers each mu-law code word to the RBS compensation system 129, as illustrated in Fig. 2B. The mu-law code word on line 211 contains one extra LSB to faαLHtate the RBS compensation.

In the RBS compensation system 130, in accordance with equations (10a), (10b), if the segment is an RBS segment, then an RBS compensation quantity is mathematicaUy combined with the segment in order to minimize the effects of RBS. In the preferred embodiment, 0.5 LSB is added or subtracted from the segment, depending upon whether the RBS imposes a space LSB or a mark LSB, respectively. If overflow occurs, then the segment indicator N is incremented, or N=N+1. The RBS compensation system 130 of the second embodiment is configured to forward each mu-law code word to the network 113 on connection 112b. It should be mentioned that both of the first and second embodiments of the combined DAQ/RBS compensation system 130 could be implemented in a single transmitter, and then one or both could be selected and used for

operation, based upon feedback received during a testΛraining session. In this configuration, the selector 194 could be utilized to select, initiate, and control the appropriate embodiment.

B. Initialization - Selection Of DAQ And RBS Compensation Quantities

The DAQ compensation quantity G as weU as an RBS compensation quantity are selected preferably during an initialization period by the compensation selector 194 (Figs. 2A, 2B). In this regard, the compensation selector 194 is configured to test different compensation quantities by combining different compensation quantities with different data segments

(preferably, in succession), analyzing feedback from a feedback system regarding the accuracy of the received/decoded segment, for example, the cooperative feedback system 210 (Fig. 4) or the noncooperative feedback system 240 (Fig. 5), and selecting an appropriate compensation quantity for normal steady state operation based upon the feedback.

1. Cooperative Feedback System

The preferred embodiment of the cooperative feedback system 210 is depicted in Fig. 4, which is merely one example of an implementation of numerous possible designs. The feedback system 210 supphes the feedback signal that is used by the selector 194 to determine the appropriate DAQ compensation quantity G and the polarity and frequency for applying the RBS compensation quantity. The feedback system 210 indudes elements in the local transmit subsystem 181 assodated with, for example, the modem 101 (Fig. 1), cooperating with elements in a remote receive subsystem 214 assodated with, for example, the analog modem 102 (Fig. 1). Furthermore, these elements of the feedback system 210 can be implemented in software,

firmware, hardware, or a combination thereof. In embodiments where elements are implemented in soi^are/firmware, they may be stored and transported on any computer-readable medium for use by or in connection with a computer-related system or method. In the preferred embodiment, the elements of the remote receive subsystem 214 that are pertinent to the feedback system 210, as illustrated in Fig. 4, are implemented in software that is stored in memory and that configures and drives a conventional digital signal processor (DSP) situated within the receive subsystem 214.

As shown in Fig. 4, the remote receive subsystem 214 receives the mu- law code words corresponding to the compensated segments -of digital data in succession from the connection 118 via a switch 229 at a predefined sampling rate, typically 8000 hertz (Hz), when the connection 118 is a telephone line. The mu-law code words 231 from the switch 229 are passed to standard signal processing components, induding an interpolator, a decoder, etc., as denoted collectively by block 232. The decoder is configured to generally demodulate and process the incoming series of linear data words in accordance with any suitable format, such as the V.34 protocol.

A comparator 234 receives the decoded bit stream 235 from the block 232 of components and compares it with a reference 236. In the preferred embodiment, the reference 236 is essentiaUy a bit stream that is substantially free of errors and that should have been received by the remote receive subsystem 214 in the absence of DAQ loss. However, other types of references 236 are possible. For example, in another possible embodiment, a signal-to- noise (S/N) level could be derived from the decoded bit stream 235, and in this case, the reference 236 would be a S/N threshold level, which is compared with the S/N level derived from the incoming signal.

A good/bad indicator 238, such as one or more bits, to indicate whether or not the accuracy of a segment 235 has improved, is generated by the comparator 234 and forwarded to a feedback transmitter 239. The feedback transmitter 239 is adapted to perform any suitable processing of the good/bad indicator 238. In the preferred embodiment, a coUection of good/bad indicators

238 or a derivative signal thereof is returned to the compensation selector 194 of the local transmit subsystem 181 via the feedback transmitter 239 situated at the remote receive subsystem 214 and the connection 118. The good/bad indicators 238 may be forwarded together in a single segment, independently, or in groups back to the transmit subsystem 181, whichever is appropriate.

In the preferred embodiment, the remote receive subsystem 214 analyzes each segment independently, reporting back to the local transmit subsystem 181 through the MP Type 1 sequence, which is a portion of the training sequence specified by the V.34 recommendation. Using currently undefined or reserved bits in the MP sequence, an indication as to which segments were improved is relayed back to the local transmit subsystem 181.

With the good/bad indicators 238 from the receive subsystem 214, the compensation selector 194 of the transmit subsystem 181 can select and apply the compensation quantity G and, if necessary, an RBS compensation quantity that improve the accuracy of the received data in order to ultimately allow high speed data transfers between the modems.

As an example of the selection process for determining an appropriate DAQ compensation quantity G by the compensation selector 194, if the remote receive subsystem 214 in the feedback system 210 detects that the transmission of a digital data segment through the digital network 113 and codec 106 results in no DAQ loss to the segment, then the feedback signal relayed to the compensation selector 194 causes the selector 194 to select a

compensation quantity G with a value of 1. If the feedback system 210 determines and indicates that a particular compensation quantity G results in a 3 db loss in the digital data segment, then the feedback signal causes the selector 194 to select the compensation quantity G of H-Jl . A 6 db loss causes the selection of a compensation quantity of 1/2, and so on. These compensation quantity values are listed merely as examples, and it can be appreάated by one ordinarily skilled in the art that other appropriate quantities are possible depending on the implementation details, the technique chosen for combining quantities with the digital data, etc.

2. Noncooperative Feedback System

Figs. 5 is electronic block diagram of the noncooperative feedback system, generally denoted by reference numeral 240. In this example of an implementation, a method for producing feedback (for helping the selector 194 determine the appropriate compensation quantities) involves monitoring requests for block retransmission from the remote modem 102 (Fig. 1). This method can be used, for example, with any modem that uses standard V.42 error correction. An advantage of this method is that it does not require modification of any existing modem and does not require cooperative effort between the transmitting and receiving modems.

More specifically, referring to Fig. 5, the noncooperative feedback system 240 indudes elements in the local transmit subsystem 181 corresponding with those shown in Fig. 2A or Fig. 2B and described previously. The local transmit subsystem 181 compensates the segments, one at a time, with different compensations during the initialization phase. After each compensation in a particular segment, the transmit subsystem 181 will dwell for a predetermined time period while the local receive subsystem 121 monitors the channel 112a

for retransmission requests. The receive subsystem 121 can be equipped with any suitable error correction mechanism 242 for monitoring retransmission requests. In the preferred embodiment, the error correction mechanism 242 is a standard V.42 error correction mechanism set forth in the industry standard V.42 specification.

In essence, the data rate will increase and the number of retransmission requests will decrease as the compensation parameters approach optimum values. Conversely, the data rate will decrease and the number of retransmission requests will increase as the compensation parameters digress from optimum values. A feedback signal 193, which can he the number of retransmission requests or some other derivative information, is generated by the error correction mechanism 242 and is communicated to the compensation selector 194.

Based upon the feedback 193 from the error correction mechanism 242, the compensation selector 204 can select and implement appropriate compensations, if any.

An advantage of the noncooperative feedback system 240 of Fig. 5 is that no loss of data synchronization ever occurs. The system 240 also works with any vender's product that supports automatic rate control, V.42 bis error correction, or other error correcting protocols.

C. Software

The combined DAQ/RBS compensation system 130 can be implemented in software. In embodiments where the system 130 is implemented in software, it may be stored and transported on any computer-readable medium for use by or in connection with a computer-related system or method. One possible implementation of the software version for the system 130, which is meant as merely an example, is set forth hereafter.

Hn2mu: a0=a0»l a0=a0»l /* right justify 14 bits */ a0=rnd(a0) /* round 14 bit value */ a0=a0«l /* left justify 14 bits */ a0=a0«l /* aOh = Sddd dddd dddd ddOO */ y=0x8000 /* mask for sign bit */

/* y = 1000 0000 0000 0000 */ al=aO&y /* alh = S000 0000 0000 0000 */ if ne aO=-aO /*if negative take 2s complement */

/* input data in-place in aOh */

/* Begin Digital attenuation quantization Loss Compensation */ rO=d_lossl /* Get loss sealer table pointer */ pt=*rO y=aO x=*pt++ d._lossin: p_ _χ *y * _r 3 _=a ι al=p y=132 * y = 0000 0000 1000 0100 */

/* bias value (33) shifted left by 2 */ /* bits to compensate for the 14 bit */

/* input data being left justified */ al=al+y /* aOh += 0000 0000 1000 0100 */

/* *finmu = S000 0000 0000 0000 */ cl=-8 /* initialize counter 1 for finding */ /* the segment */ do 8 { /* determine the segment number */ ifc pi al=al«l /* (exponent) and the */ } /* compressed code word into place */

/* aOh ^■ = lccc cxxx xxxx xxxx */ al=al»8 x=al /* Temp store of a 1 data */ al=c2 /* Move c2 to cO */ cO=al cl=-l /* Set cl for no RBS */ r0=d_loss2 /* Read RBS indentifier bits */ al=*rO al=al«l /* Shift next bit to msb */

*rO=al /* Save RBS identifier */ al=x /* Restore al */ if pi goto Hn2mu05 /* No changes if msb=0 */ al=*r0 y=0x200 /* RBS identifier bit */ al=al | y /* Reset RBS identifier */

*r0=al /* Save RBS identifier */ al=x /* Restore al */ y=4 al=al+y /* combine 0.5 LSB */ y=0x80 /* Test for negative result */ al&y if ne goto Hn2mu05 /* Jump if no segment change */ cl=0 /* clear cl for segment change */

Hn2mu05: y=0x78 a l=al&y y=132 /* put Is before and after the */ al=al+y /* compressed code word */

/* alh = 0000 0000 001c cccl */ if clge a l=a l«l /* Shift if segment change */ do 7 { /* the formatted compressed */ if cOlt al=al«l /* code word into place, i.e. */ } /* apply exponent (segment) */

/* alh = 00 0000 001c cccl seg = 0 */ /* alh = 00 0000 01cc ccl0 seg = 1 */

/* alh = 00 0000 lccc c 100 seg = 2 */ /* alh = 00 0001 cccc 1000 seg = 3 */ /* alh = 00 001c cccl 0000 seg = 4 */ /* alh = 00 Olcc cclO 0000 seg = 5 */ /* alh = 00 lccc clOO 0000 seg = 6 */

/* alh = 01 cccc 1000 0000 seg = 1 *1

al=al-y /* alh -= 0x21 subtract bias (33) */ v=al ..— * pt++ p=x*y aO=p End Digital attenuation quantization Loss Compensation */ End */ y=132 /* y = 0000 0000 1000 0100 */

/* bias value (33) shifted left by 2 */ /* bits to compensate for the 14 bit */ /* input data being left justified */ aO=aO+y /* aOh += 0000 0000 1000 0100 */

/* *linmu = S000 0000 0000 0000 */ cl=-8 /* initialize counter 1 for finding */ /* the segment */ 8 { /* determine the segment number */ ifc pi aO=aO«l /* (exponent) and the */ } /* compressed code word into place */

/* aOh = lccc cxxx xxxx xxxx */ a0=a0»4 /* the compressed code word */ a0=a0«l /* into place */ /* aOh = 1111 cccc xxxx xxxx */ al=c2 /* c2 = negative segment number */ al=-al /* alh = segment number */ /* alh = 0000 0000 0000 Oeee */ al=al«4 /* segment number into place */ al=al«8 /* alh = Oeee 0000 0000 0000 */ y=0x0f00 /* mask for compressed code word */ /* y = 0000 1111 0000 0000 */ a0=a0&y /* aOh = 0000 cccc 0000 0000 */ y=al /* y = Oeee 0000 0000 0000 */ a0=a0+y y=*r3 /* add segment number to aOh */ /* aOh = Oeee cccc 0000 0000 */ /* y = S000 0000 0000 0000 */ a0=a0+y /* add sign bit to aOh */ /* aOh = Seee cccc 0000 0000 */ a0=a0»8 /* to low byte of aOh */ I* aOh = xxxx xxxx Seee cccc */ y=0x00ff /* mask for 8 bit Mulaw value */ a0=a0&y /* mask 8-bits to insure removal of */ /* sign extension */

/* aOh = 0000 0000 Seee cccc */ a0=a0 ^Λ y /* invert bits to provide an inverted*/

/* Mulaw value in low byte of aOh */ return d_losstbl: int 1.0, 1.0, 0.5, 0x7fff, 0.7071, 1.4142

END OF CODE

Many variations and modifications may be made to the preferred embodiment of the invention without departing substantiaHy from the spirit and principles of the invention. All such modifications and variations are intended to be included herein within the scope of the present invention, as is defined by the foHowing. claims.

In the claims set forth hereinafter, the structures, materials, acts, and equivalents of all "means" elements and "logic" elements are intended to include any structured), material(s), or act(s) for performing the functions specified in connection with said elements.