COMBINED VOLATILE NONVOLATILE ARRAY by

Andreas Scade Stefan Guenther

[0001] TECHNICAL FIELD

[0002] The present disclosure relates to combined volatile and nonvolatile memory circuits.

[0003] BACKGROUND

[0004] High speed volatile and noo-volarilc storage of data is an important feature in computer systems. Present solutions use specialized volatile memory technologies, like DRAM and SRAM with non volatile back up memories, such as BBSRAM, EEPROM and FLASH. In case of power loss significant amounts of volatile data may have to be stored in the non-volatile memory. This is typically done via signaling interfaces between volatile and nonvolatile memory regions, the interfaces having limited parallelism, high current requirements, and possibly using multiple processor cycles to manage the data transfer. A faster and less power intensive solution is nvSRAM memories, where each volatile cell is paired with a non-volatile cell and data may pass from one region to another without first being placed on a bus or other signaling interface. One disadvantage of present nvSRAM circuits is their limited density and relatively large memory cell size, typically involving 12 high and low voltage transistor.

[0005] BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the drawings, the same reference numbers and acronyms identify elements or acts with the same or similar functionality for case of understanding and convenience. To easily identify the discussion of any particular clement or act, the most significant digit or digits in a reference number refer to the figure number in which that clement is first introduced.

[0007] Figure 1 is a block diagram of an embodiment of an integrated non-volatile static random access memory array.

[0008] Figure 2 illustrates in more detail an embodiment of an integrated non-volatile static random access memory array.

[0009] Figure 3 is an illustration of an embodiment of signaling for a volatile READ operation.

[0010] Figure 4 is an illustration of an embodiment of signaling for a volatile WRITE operation.

[001 1 ] Figure 5 is an embodiment of signaling to perform a non-volatile flash memory cell STORE operation.

[0012] Figures 6 and 7 illustrate signaling for an embodiment of a non-volatile memory cell

RECALL operation.

[ 0013] Figure 8 is a block diagram of an embodiment of a computing system including an integrated volatile-nonvolatile memory.

[0914] DETAILED DESCRIPTION

[0015] References to "one embodiment" or "an embodiment" do not necessarily refer to the same embodiment, although they may.

[0016] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; (hat is to say, in the sense of "including, but not limited to." Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words "herein," "above," "below" and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. When the claims use the word "or" in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.

[0017] "Logic" refers to signals and/or information that may be applied to influence the operation of a device. Software, hardware, and firmware are examples of logic. Hardware logic may be embodied in circuits. In general, logic may comprise combinations of software, hardware, and/or firmware.

[0018] Those skilled in the art will appreciate that logic may be distributed throughout one or more devices, and/or may be comprised of combinations of instructions in memory, processing capability, circuits, and so on. Therefore, in the interest of clarity and correctness logic may not always be distinctly illustrated in drawings of devices and systems, although it is inherently present therein.

[0019] Figure 1 is a block diagram of an embodiment of an integrated non-volatile static random access memory array. The array comprises volatile memory cells 108 - 113, in this embodiment SRAM memory cells. The array comprises non-volatile memory cells 114 - 119, in this embodiment flash memory cells. The array comprises sense amplifiers 102 and 103. Data is communicated to and from the volatile and non-volatile cells 108-119 using bit lines BT0 and BTl and their compliment lines BCX) and BCl . The sense amps 102 and 103 drive the bit lines and their complements to unambiguous values when reading data from the cells.

[0020] Each volatile memory cell 108-113 has an associated non-volatile cell 114-119 which may be used to store the information in the associated volatile cell. Thus each volatile cell 108-113 has a "backup" non-volatile cell 114-119. For example, cell 108 may have a non-volatile "backup" cell 115. Cell 109 may have a "backup" cell 117, and so forth. The same bit lines and compliment lines BT0, BTl, BC0, BCl are used to insert data into and obtain data from some number of volatile cells. The bit lines BT0, BTl together with the Vc0 / VcI lines are used to insert data into or obtain data from their non-volatile associated cells.

[0021] Insertion of data into volatile cells 108-113 is performed using WRITE operations. Obtaining of data from volatile cells 108-113 is performed with READ operations. Insertion of data from volatile ceils 108-113 or from the data bus via the sense amplifier to non- volatile cells 114- 119 is performed using STORE operations. Obtaining data from non-volatile cells 114-119 is performed with RECALL operations. Clearing data stored in the FLASH cells is performed with ERASE operations.

[0022] In Figure 1 , three volatile/nonvolatile pair* are shown associated with each bit line BT0 or BTl , but in fact any practical number of ceils pairs may be associated with a particular bit line, according to the application. Each grouping of cells associated with a particular bit line may be referred to as a column. Various embodiments may comprise more or fewer cells per column. Typically, only one cell per bit line may be operated on simultaneously. The cell of a column to

operate on is selected using a signal called a "word line", WL. A WL may select cells from a number of columns simultaneously: these columns form one or more memory words, and the number of columns in a memory word may be referred to as the "word width" or "page size". [0023] Figure 2 illustrates in more detail an embodiment of an integrated non-volatile static random access memory array. SRAM 111 is associated with a non-volatile flash cell 114 comprising transistors 206 and 208 (as an example). SRAM 108 is associated with a non- volatile flash cell 115 comprising transistors 202 and 204 (as an example). Word line VwIs0 is in this embodiment a common control to both volatile cells 108 111 and therefore both cells are part of the same memory word and/or page.

[0024] Non-volatile charge storage is accomplished in this embodiment of a FLASH cell at all gates connected with Vse0. In prior designs a differential approach is taken to sensing the charge stored in both the volatile and nonvolatile cells. The sense amplifiers sense differential voltage on the bit lines and their complements and drive the difference to an unambiguous result representing the bit value. In this embodiment the sense amplifiers 102 103 may use a nondiffcreniial approach at least for the nonvolatile ceils 114 115, which are each coupled only to a bit line, not a complement bit line. Bit value detection may be facilitated by controlling Vc0 and Vc 1 according to the value sensed on the corresponding bit line. The number of transistors in each nonvolatile cell 114 115 may be reduced for example from six per cell, to three or two (as shown) per cell, due at least in part to removing control and isolation transistors between volatile and nonvolatile regions as well as Vcc (a high supply voltage).

[0025] Transistors of the flash cells 114 115 may in some embodiments comprise SONOS (stlicoo- oxidc-nitridc-oxidc semiconductor) technology. Data is communicated between volatile cell Ul and flash cell 114 using bit line BT0. Control lines VwIF0, VwIsO, Vc0, and Vse0 control the transfer of data to and from flash cell U4. Data is communicated between volatile cell 108 and flash cell 115 using bit line BT 1. Control lines VwIF0, VwIs0, Vc I , and Vse0 control the transfer of data to and from flash cell 115. Non- volatile STORE operations on flash memory may require medium (relative low) voltages Vc0 and VcI , leaving Vse0 as the only high voltage node. RECALL is a low voltage operation and at ERASE all nodes are low voltage except for Vse0. Word line VwIF0 is a common control to both flash cells 114 115 and therefore both cells are part of the same memory word and/or page.

[0026] The medium control voltages Vc0 VcI for the flash cells 114 115 are isolated from the corresponding volatile cells 111108, which operate using comparatively low-voltages. The areas of the memory comprising flash memory cells 114 115 and nonvolatile cells 111 108 may therefore be fabricated with higher density than would be the case if high, medium and low voltage areas were more integrated. The bit lines BT0 and BTl are used to communicate data between volatile and nonvolatile ceils, increasing performance over systems that employ external bus interfaces between volatile and nonvolatile regions.

[0027] Thus, the memory circuit includes volatile memory cells coupled to bit lines, and nonvolatile memory cells coupled to the volatile memory cells via the bit lines but not via other couplings found in prior solutions, such as control and isolation transistors. Consequently, the number of transistors in the non- volatile cells may be reduced to two from six or more. In this example, SONOS (204, 206) and medium voltage (202, 208) transistors implement the nonvolatile cells, respectively. Other possible implementations may involve one SONOS and two medium- voltage transistors per nonvolatile cell, and/or a floating gate NOR structure.

[0028] In the illustrated embodiment, the volatile cells are implemented by SRAM cells coupled to the bit lines and to complements of the bit lines, whereas the nonvolatile cells are flash cells coupled to the bit lines only. The possible implementations could include DRAM and are not specific to using SRAM for the volatile cells. Each non-volatile ceil is coupled to multiple volatile cells via a particular bit line, and coupled to a non-volatile word line corresponding to a volatile word line coupled to only one of the volatile cells on the particular bit line to which the nonvolatile cell is coupled, effectively pairing each nonvolatile cell with a single volatile cell.

[0029 ] Figure 3 is a signal diagram showing an embodiment of signals on the bit lines BT0 and BTl , their respective compliment lines BC0 and BCl, and the volatile word line VwIs0 for a READ operation. In this embodiment each signal may have three states - high, low, and "prc- cbarge". For discussion assume that volatile cells 111 and 108 are read to bit lines BT0 and BTl and complement bit lines BC0 and BCl respectively. The zero or low state in the figures corresponds with the thick vertical base line for each signal. Thc-pre-charge state corresponds to a voltage stepped up to approximately a half-way point between the heavy vertical lines. A one or high state is shown when the voltage appears to the farthest right of the base line for a signal. In Figure 3 the bit lines are pre-charged (i.e. set prior to the READ operation) to the neutral state.

During the pre-chargc phase, the word line VwIs0 has a zero voltage. Voltage levels arc relative to a ground or low supply level (i.e. Vss).

[0030] At time T0, word line VwIs0 has a voltage presented on it. At time Tl, this voltage has reached its peak value. READ and WRITE operations for volatile memory may be performed at lower voltages than operations on nonvolatile cells. Thus "high" or "1" on a volatile signal line may in some embodiments (e.g. other than SONOS) be less than "high" or "1" on a nonvolatile signal line. When the word line achieves a high state, the bit line for a particular cell will assume a level corresponding to the value stored within the volatile cell. For the cell read on BT0, the stored value was zero, thus at T2 the value expressed on BT0 is zero. The compliment of this value, i.e. one, is expressed at T2 on the compliment line BC0. Volatile cell 108 stored a one value driving BTl toward a one and BCl to 0, starting the transition at Tl and completing at T2. Note that a sense amplifier coupled to the bit lines may facilitate driving the values to unambiguous one and zero.

[0031 ] At time T3, the word line VwIs0 has dropped back to state 0. At time T4, the bit and compliment lines return to the pre-chargc state.

[0032] Figure 4 is an illustration of an embodiment of signaling for a volatile WRITE operation. The WRITE operation begins by applying to the bit lines BT0 BTl the values to be stored to the volatile cells, in this example, BT0 is set to the one state and BT) is set to the zero state. The compliment lines BC0 BCI arc set to the compliments of the values to be written to the memory cells. Because VwIsO is not initially asserted, the values on the bit line do not cause any change to the values stored within the memory cells. At time Tt), the word line VwIsO is asserted. By Tl, the voltage value stored in cell Ul begins to "pull down" the value on BT0 and "pull up" the value on BC0. At time Tl the charge value stored in cell 108 begins to "pull up" BTi and to "pull down" BC0. In some embodiments, each volatile memory cell may comprise two pairs of cross coupled transistors with each pair acting as a current source or drain. By time T2, the pull up or pull down effects have reached their maximum value. By time T4, these effects arc no longer present [0033] At time TS, the voltage on word line VwIs0 begins to reduce. At time T6, the voltage being asserted on VwIs0 in zero. The bit lines and compliment lines begin a pre-charge to a neutral state, which concludes at time T7.

[0034] Figure 5 is an embodiment of signaling to perform a non-volatile flash memory ceil STORE operation. The STORE operation is preceded by a read of the corresponding volatile memory cells. During that read, which is not shown in Figure 4, the bit and compliment lines for the flash cells, in this case BT0, BC0, BTl, and BCl, are set to the values which are to be stored within the nonvolatile memory cells. Figure 5 illustrates the situation where BT0 is set to zero and BTl is set to one. The word line for the flash cells, VwIF0, the voltage store/erase line for the cells Vse, and the voltage supply line for memory cell 115 VC0 and for memory cell 114 VCl are illustrated. [0035] Prior to time T0, none of the above lines are asserted. Between T0 and Tl , the word line for the flash cells VwIF0 is driven high. The voltage line VCl is driven high in order to store a one in the cell.

[ 0036] Between Tl and Tl, Vse is driven high. By time T3, the flash cells store charge corresponding to the respective values of 0 and 1, the values in their associated volatile memory cells. At T3, Vse begins to drop. Between times T4 and T5 VCl and VwIF0 also drop, and the STORE operation is complete. In some embodiments, the sense amplifier may also operate to shift the low voltage levels on BT0 and BTl to medium voltage levels on Vc0 and VcI . [0037] Figures 6 and 7 illustrate signaling for an embodiment of a non-volatile memory cell RECALL operation. The recall of data from flash memory is followed by a WRITE operation of the recalled bits into the corresponding volatile cells. In the illustrated example, a flash cell coupled to BT0 stores a zero, and a flash cell corresponding to BTl stores a one. The bit lines and their complements are set low prior to commencing the RECALL operation. Referring to Figure 6, the RECALL begins at time Tl with the assertion of the word line VwIF0 for the flash cells. By Tl, BTl has been pulled up by the stored high (one) voltage in the flash cell to which it is coupled and BT0 remains at zero, reflecting the low (zero) voltage stored in its associated flash cell. BTl may in some cases be pulled to a value that reflects the supply voltage (one, or high) limited or reduced by threshold voltages of the transistor providing the charge storage. In other words. BT0 has zero voltage because its corresponding flash cell stored a zero, while BTl is driven toward (but not to) one to reflect the one stored in its corresponding flash cell. Around T5 transient effects appear on BC 1 and BT0. From T7 to T8 the transient effects dissipate, the sense amplifiers engage, and the bit lines BT0 and BTl have voltages corresponding to the values to be set within the volatile

memory later on. VwIF0 will start to fall and is zero at T8. VwIF0 may stay high without influencing the upcoming WRITE of the bit line values to the volatile cells, [ 0038] Figure 7 illustrates signaling for an embodiment of a second pan of a RECALL operation during which values obtained from the flash cells are written into corresponding volatile memory cells. This writing of SRAM from the associated flash cells is similar to the WRITE operation described earlier in conjunction with Figure 4. As before, the word line for the volatile memory VwIs0 is asserted to drive the values present on the bit lines into the volatile memory cells. Transient effects on the bit and compliment lines result from energy shifts (cross currents) between the transistors and the bit lines. By T4 the transient effects have dissipated and the volatile cells store the values presented on the bit lines.

[ 0039] Figure 8 is a block diagram of an embodiment of a computing system including an integrated volatile-nonvolatile memory. The computing system will typically comprise at least one processor 802, for example a general purpose microprocessor, an embedded special-purpose processor, a digital signal processor, and so on. The processor 802 may interact with a memory 804 to read and write data during system operation. The memory may comprise volatile region 806 and nonvolatile region 808. Cells of the volatile region 806 may have corresponding cells in the nonvolatile region 808. In the course of operation, or upon imminent loss of system power, data may be stored from the volatile region 806 to the nonvolatile region 808. The volatile 806 and nonvolatile 808 regions may communicate via the bit lines BT and corresponding subrcgions may have corresponding word lines WLs and WLf to accomplish the pairing of volatile and nonvolatile cells.

[0040] Those having skill in the art will appreciate that mere are various vehicles by which processes and/or systems described herein can be effected (e.g., hardware, software, and/or firmware), and that the preferred vehicle will vary with the context in which the processes are deployed. For example, if an implementer determines that speed and accuracy are paramount, the implememer may opt for a hardware and/or firmware vehicle: alternatively, if flexibility is paramount, the implementer may opt for a solely software implementation; or, yet again alternatively, the implementer may opt for some combination of hardware, software, and/or firmware. Hence, there are several possible vehicles by which the processes described herein may be effected, none of which is inherently superior to the other in that any vehicle to be utilized is a

choicc dependent upon the context in which the vehicle will be deployed and the specific concerns (e.g., speed, flexibility, or predictability) of the implemented any of which may vary. Those skilled in the art will recognize that optical aspects of implementations may involve optically-oriented hardware, software, and or firmware.

[0041 ] The foregoing detailed description has set forth various embodiments of the devices and/or processes via the use of block diagrams, flowcharts, and/or examples. Insofar as such block diagrams, flowcharts, and/or examples contain one or more functions and/or operations, it will be understood as notorious by those within the art mat each function and/or operation within such block diagrams, flowcharts, or examples can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof. Several portions of the subject matter described herein may be implemented via Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPOAs), digital signal processors (DSPs), or other integrated formats. However, those skilled in the art will recognize that some aspects of the embodiments disclosed herein, in whole or in part, can be equivaientry implemented in standard integrated circuits, as one or more computer programs running on one or more computers (e.g., as one or more programs running on one or more computer systems), as one or more programs running on one or more processors (e.g., as one or more programs running on one or more microprocessors), as firmware, or as virtually any combination thereof, and that designing the circuitry and/or writing the code for the software and/or firmware would be well within the skill of one of skill in the art in light of this disclosure. In addition, those skilled in the art will appreciate that the mechanisms of the subject matter described herein are capable of being distributed as a program product in a variety of forms, and that an illustrative embodiment of the subject matter described herein applies equally regardless of the particular type of signal bearing media used to actually carry out the distribution. Examples of a signal bearing media include, but are not limited to, the following: recordable type media such as floppy disks, hard disk drives, CD ROMs, digital tape, and computer memory; and transmission type media such as digital and analog communication links using TDM or IP based communication links (e.g., packet links). [0042] In a general sense, those skilled in the art will recognize that the various aspects described herein which can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or any combination thereof can be viewed as being composed of various types

of "electrical circuitry." Consequently, as used herein "electrical circuitry" includes, but is not limited to, electrical circuitry having at least one discrete electrical circuit, electrical circuitry having at least one integrated circuit, electrical circuitry having at least one application specific integrated circuit, electrical circuitry forming a general purpose computing device configured by a computer program (e.g., a general purpose computer configured by a computer program which at least partially carries out processes and/or devices described herein, or a microprocessor configured by a computer program which at least partially carries out processes and/or devices described herein), electrical circuitry forming a memory device (e.g., forms of random access memory), and/or electrical circuitry forming a communications device (e.g., a modem, communications switch, or optical-electrical equipment).

[ 0043] Those skilled in the art will recognize that it is common within the art to describe devices and/or processes in the fashion set forth herein, and thereafter use standard engineering practices to integrate such described devices and/or processes into larger systems. That is, at least a portion of the devices and/or processes described herein can be integrated into a network processing system via a reasonable amount of experimentation.

[0044] The foregoing described aspects depict different components contained within, or connected with, different other components. It is to be understood thai such depicted architectures are merely exemplary, and that in tact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operabry connected", or "opcrably coupled", to each other to achieve the desired functionality.