BACKGROUND

[0001] Amplifiers are used for a variety of purposes. For example, a sense amplifier may be used to measure current. A voltage generated across a low resistance value sense resistor is a function of the current through the resistor. The voltage across the sense amplifier is amplified by a sense amplifier and may be used in a control feedback loop. For example, the sense amplifier may be part of a motor controller device and the current through the motor is used as a feedback signal to help control the speed of the motor.

[0002] Amplifiers may have any a wide variety of architectures. For example, some amplifiers have an asymmetric architecture. An asymmetric amplifier is one in which the circuitry differs for signal flow of each input-to-output. For example, if the amplifier is a differential amplifier having a positive input and a negative input, the input circuitry of the positive input is configured differently than the input circuitry of the negative input. Because of such asymmetry, and device modelling inaccuracies, parasitic effects, and semiconductor process variations, the common mode gain of the amplifier may be higher than the value that is acceptable for various applications.

SUMMARY

[0003] In described examples, an an electrical device (e.g., an integrated circuit) includes an amplifier, a configurable common mode gain trim circuit, and a memory. The configurable common mode gain trim circuit is coupled to the amplifier. The memory is configured to include trim data that is usable during an initialization process for the electrical device to configure the impedance matching circuit.

[0004] In other examples, an integrated circuit includes an asymmetric amplifier comprising first and second nodes and a configurable common mode gain trim circuit coupled to the amplifier. The configurable common mode gain trim circuit comprises a first plurality of impedance matching elements coupled between the first node and ground and a second plurality of impedance matching elements coupled between the second node and ground. The integrated circuit also may include a memory configured to include trim data that is usable during an initialization process for the electrical device to configure the first and second impedance matching elements. [0005] In yet another example, a method includes determining a common mode gain of an amplifier, comparing the determined common mode gain to a threshold, and changing the configuration of a common mode gain trim circuit of the amplifier until the common gain of the amplifier is below the threshold.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 shows a circuit architecture of an amplifier and includes a configurable common mode gain trim circuit to assist in reducing the common mode gain of the amplifier in accordance with various examples.

[0007] FIG. 2 depicts the integrated circuit containing the configurable common mode gain trim circuit and the amplifier coupled to a microcontroller unit in accordance with various examples.

[0008] FIG. 3 shows the integrated circuit coupled to a programming unit to determine trim data for the common mode gain trim circuit so as to reduce the common mode gain of the amplifier below a maximum threshold in accordance with various examples.

[0009] FIG. 4 illustrates a method performed by the programming unit in accordance with various examples.

[0010] FIG. 5 illustrates a method performed by the integrated circuit to configure the common mode gain trim circuit during an initialization process.

DETAILED DESCRIPTION OF EXAMPLE EMB ODEVIENT S

[0011] Given the asymmetric nature of various types of amplifiers, such as amplifiers employing single-ended common-gate circuit topologies, the described embodiments include a common mode gain trim circuit that is coupled to various nodes of the amplifier. The common mode gain trim circuit can be configured to adjust the impedance of the nodes in such a way that increases the common mode rejection ratio and the common gain. Trim data is determined for the amplifier during a trim process and the trim data is stored in memory in a device (e.g., integrated circuit) containing the amplifier. During a subsequent device initialization process, the trim data is retrieved from the memory and used to configure the common mode gain trim circuit.

[0012] The techniques described herein to reduce the common mode gain of the amplifier can be applied to any type of amplifier circuit topology. The described technique may be particularly beneficial for asymmetric amplifier topologies, but the technique is further applicable to symmetric amplifier topologies. [0013] FIG. 1 shows at least a portion of an amplifier circuit 80 (or simply amplifier). The amplifier circuit in the example of FIG. 1 has an asymmetric architecture, but can be symmetric in other embodiments. The positive and negative inputs to the amplifier 80 are shown as IPx and INx, respectively. The IPx and INx inputs are connected to the sources of transistors MNl and MN2 through resistors Rl and R2. Transistors MPl and MP2 supply the biasing currents to MNl and MN2 separately. The diode-connected MN2 also connects to the gate of MNl . MNl acts as a common-gate amplifer. A negative-feedback loop is formed by MN2, MNl and MN0 to force the MN2 source voltage to equal to the MNl source voltage. The extra current in R2 over the biasing current coming from MN2 flows through MN0. This current contains the information of the differential voltage between IPx and INx. This current is further mirrored by MP3 and MP4 and then converted to the voltage through resistor R3.

[0014] A common mode gain trim circuit 90 also is shown in FIG. 1. The common mode gain trim circuit 90 is coupled to amplifier nodes 100 and 120 as shown. The common mode gain trim circuit 90 includes a plurality of impedance matching circuits 92-98. A first plurality of impedance matching circuits can be coupled between node 100 and ground, and a second plurality of impedance matching circuits can be coupled between node 120 and ground. In the example of FIG. 1, the first plurality of impedance matching circuits coupled between node 100 and ground includes impedance matching circuits 92 and 94, and the second plurality of impedance matching circuits coupled between node 120 and ground includes impedance matching circuits 96 and 98. Thus, each plurality of impedance matching circuits includes two impedance matching circuits in this embodiment. However, the number of impedance matching circuits in each plurality can be other than two including one or more of such circuits. Further, while the number of impedance matching circuits are the same coupled to each amplifier node 100 and 120 (i.e., 2 in this example), the number of impedance matching circuits coupled to node 100 can be different than the number of impedance matching circuits coupled to node 120. For example, in another embodiment two impedance matching circuits may be coupled to node 100, while three impedance matching circuits are coupled to node 120.

[0015] Each impedance matching circuit 92-98 may include a capacitor and a series connected switch. Impedance matching circuit 92 includes a capacitor CI and a corresponding switch MN3. Impedance matching circuit 94 includes a capacitor C2 and a corresponding switch MN4. Impedance matching circuit 96 includes a capacitor C3 and a corresponding switch MN5. Impedance matching circuit 98 includes a capacitor C4 and a corresponding switch MN6. Thus, the common mode gain trim circuit 90 comprises multiple capacitors and corresponding multiple switches. In some embodiments, the capacitors may include lateral flux metal capacitors, but can be different types of capacitors in other embodiments. Each capacitor C1-C4 in the common mode gain trim circuit 90 is indivudally selectable by way of its corresponding switch MN3-MN6. The switches may be n-type metal oxide semiconductor field effect transistors (MOSFETs) in some embodiments such as that shown in FIG. 1, but can be other types of transistors such as p-type MOSFETS in other embodiments.

[0016] Each switch MN3-MN6 can be operated in an open or closed position based on a control signal provided to its gate terminal. Each switch may be controlled by a separate control signal and thus each switch is individually controlled. Because each switch has its source terminal connected to ground, closing a given switch causes the corresponding capacitor to be coupled between the amplifier node 100 or 120 and ground. Opening the switch causes the corresponding capacitor effectively to be operationally disconnected from the circuit. Thus, the control signals can be set so as to connect any combination of capacitors C1-C4 to the amplifier nodes 100, 120. For example, node 100 may have no capacitors connected to it if neither switch MN3 and MN4 are placed in the closed state by their control signals. In another configuration, switch MN3 may be closed while MN4 is opened thereby electrically connecting only capacitor CI between node 100 and ground. In yet another configuration, switch M3 may be opened while MN4 is closed thereby electrically connecting only capacitor C2 between node 100 and ground. Finally, if both switches MN3 and MN4 are closed, then both capacitors CI and C2 are connected in parallel between node 100 and ground. The control of switches MN5 and MN6 and their corresponding capacitors C3 and C4 is similar, thereby leaving both capacitors C3 and C4 out of the amplifier circuit 80, electrically connecting just one or the other capacitor C3, and C4 to node 120, or electrical connecting both capacitors C3 and C4 to node 120.

[0017] The control signals to be applied to the gates of the individual switches MN3-MN6 in the common mode gain trim circuit 90 may be referred to herein as "trim data." Such trim data may be determined before the amplifier circuit 80 is used. For example, the trim data may be determined at the factory before the part is shipped. A trim data determination process may be performed as described hereinbelow to determine which capacitors in the common mode gain trim circuit 90 are to be electrically connected between their respective nodes 100, 120 and ground. Connecting a capacitor between a node 100 or 120 and ground adjusts the impedance of that node relative to what the impedance would have been absent the capacitor. The trim data is determined so as to more closely balance the impedance between nodes 100 and 120, which in turn advantageously reduces the common mode gain value for the amplifier circuit 80.

[0018] The capacitors that can be electrically coupled between an amplifier node 100, 120 and ground through operation of the corresponding switches may all have the same capacitance value in some embodiments which permits different integer multiples of C (e.g., C may be 30 femtofarads) to be electrically coupled between the amplifier node and ground based on a time data value that closes a number of capacitor switches corresponding to the desired integer number of capacitors. For example, if a 2C capacitor is desired, two capacitor switches are closed to electrically couple two capacitors between the amplifier node and ground. In other embodiments, the capacitors to be selectively coupled to a given node may be binary weighted (1C, 2C, 4C, etc.) which permits different integer multiples of C to be electrically coupled between the amplifier node and ground based on a binary trim data value.

[0019] FIG. 2 illustrates that an electrical device which may include or be an integrated circuit 150 that includes the amplifier circuit 80 and common mode gain trim circuit 90. The integrated circuit may include additional components as well such as a motor drive circuit 152, storage for trim data 154, and control logic and interface circuitry 156. The integrated circuit 150 can be coupled to a motor 180 which may be a single or multiphase motor. The motor 180 may have its own power FETs which are driven by current generated (charging or discharging current) by the motor drive circuit 152. The motor 180 connects to ground through a low resistance sense resistor 185. The sense resistor 185 is coupled to the amplifier 80 which amplifies the voltage generated across the sense resistor as a result of the current flowing through the motor 180. The amplifier provides its amplified output signal to the control logic and interface circuitry 156 (which may include conditioning circuitry such as a clamp circuit). The integrated circuit 150 may be coupled to a microcontroller unit (MCU) 190 which can be used to program and control the integrated circuit.

[0020] FIG. 3 illustrates a configuration in which the integrated circuit 150 is coupled to an external programming unit 200. The programming unit 200 may be configured to determine trim data 154 to be programmed into the integrated circuit 150 to reduce and/or minimize the common mode gain of the amplifier 80. The programming unit may be a computer or other type of electrical equipment that has an electrical interface suitable to be connected to the integrated circuit 150. The programming unit 200 may include software or firmware executed by a processor internal to the programming unit 200. The programming unit, upon execution of its software, may be configured to determine the common mode gain of the amplifier 80 of the integrated circuit, and generate certain trim data 154 to configure the common mode gain trim circuit 90 to adjust the impedance of the amplifier's nodes 100 and 120 to reduce the common mode gain. For example, the programming unit 200 may be configured to determine trim data 154 for the common mode gain trim circuit 90 that causes the amplifier's common mode gain to be below a desired threshold. The particular threshold may be preset in the programming unit's software or may be programmable by a user of the programming unit. Some applications may necessitate a lower amplifier common mode gain value than other applications, and the programming unit may be configured to help ensure the common mode gain of the amplifier falls below the desired threshold.

[0021] The programming unit 200 may be connected to the input pins for the amplifier (i.e., the pins to which the sense resistor 185 would otherwise be connected). The programming unit is able to generate a common mode signal to be applied to both inputs of the amplifier 80. The resulting output signal from the amplifier 80 is then conditioned and provided back to the programming unit. The ratio of the magnitudes of the amplifier's output signal to the common mode input signal is computed and represents the common mode gain of the amplifier 80.

[0022] The programming unit 200 can inject a common mode signal into the amplifier's inputs, record the output signal magnitude and compute the common mode gain. If the common mode gain is too high (relative to a desired maximum level), then the programming unit can transmit updated trim data to the integrated circuit 150 for adjusting the configuration of the common mode gain trim circuit 90. The programming unit 200 then can compute the amplifier's common mode gain with the newly reconfigured common mode gain trim circuit. If the newly computed common mode gain is less than the target maximum level, then the process stops and the trim data 154 remains stored in the integrated circuit 150. Otherwise, the programming unit again transmits updated trim data to the integrated circuit in an attempt to reduce the common mode gain. The process is iterative until the programming unit computes a suitably low common mode gain for the amplifier 80.

[0023] FIG. 4 is a method flow chart illustrating the process for configuring the integrated circuit's trim data 154. At 210, the method includes determining the common mode gain of the amplifier. This determination can be made as described hereinabove (e.g., injecting a common signal into the amplifier, measuring the output signal's magnitude and computing the ratio of the output signal magnitude to the input signal magnitude). The programming unit 200 can be used to perform this operation.

[0024] At 212, the programming unit 200 then compares the computed common mode gain to a threshold. The threshold may have been preprogrammed into the programming unit or may be a value indicative of the threshold received through a user interface thereby permitting a user of the programming unit to adjust the threshold to suit a particular application. If the common gain is greater than the threshold, then at 214, the method includes changing the configuration of the common mode gain trim circuit for the amplifier in an attempt to reduce the common mode gain of the amplifier. In some embodiments, this operation may include the programming unit 200 generating new trim data. For example, the trim data can be used to select targeted capacitors within the common mode gain trim circuit 90. The newly generated trim data then may be transmitted to the integrated circuit containing the amplifier 80 and common mode gain trim circuit 90 for storage as trim data 154. Control then loops back to operation 210 at which time the common mode gain is reassessed with the newly programmed trim data. After the programming unit 200 determines the amplifier's common mode gain to be less than the threshold (or less than or equal to the threshold), the process stops and the most trim data most recently transmitted to the integrated circuit remains loaded into the integrated circuit and used from that point forward.

[0025] FIG. 5 is an example of a process flow that may be performed each time the integrated circuit is initialized such as might occur during a power-on event. The initialization process for the integrated circuit begins at 220 and triggers the rest of he process flow to occur. During or after the initialization process, the trim data is retrieved from memory at 222. A state machine (e.g., a programmable controller) may be included in the integrated circuit and used to retrieve the trim data from memory. The trim data is then used (e.g., by the state machine) to configure the common mode gain trim circuit 90 at 224. The trim data may comprise a number of bits, and in some embodiments each bit is used to open or close a corresponding switch (e.g., MN3-MN6 in the example of FIG. 1) to selectively electrically couple (or not) the capacitor of each such switch between an amplifier node and ground.

[0026] In this description, the term "couple" or "couples" means either an indirect or direct wired or wireless connection. For example, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections.

[0027] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.