AMPLIFIER

Related Applications

[0001] This application claims the benefit of provisional patent application serial number 63/162,583, filed March 18, 2021 , the disclosure of which is hereby incorporated herein by reference in its entirety.

Field of the Disclosure

[0002] The technology of the disclosure relates to a differential power amplifier with a common mode change structure, which can provide even harmonic traps in a common mode operation without sacrificing performance at the fundamental frequency in a differential mode operation, and/or can achieve a specific load line impedance at even harmonics in the common mode operation without changing load line impedance at the fundamental frequency in the differential mode operation.

Background

[0003] In certain circumstances, a class F operation is desired for a differential power amplifier, which operates in a differential mode at a fundamental frequency and odd harmonics, while operating in a common mode at even harmonics.

[0004] In the common mode operation, it is often desired that the differential power amplifier has output circuitry providing second harmonic traps, so as to terminate unwanted harmonics for the differential power amplifier. Unfortunately, conventional output circuitry, which can provide second harmonic traps to the differential power amplifier in the common mode, will add loss and reduce a bandwidth at the fundamental frequency of the differential power amplifier in the differential mode, especially when broadband traps are used.

[0005] Accordingly, there remains a need for improved output circuitry designs for differential power amplifiers, which can provide second harmonic traps in the common mode operation without sacrificing efficiency and the fundamental frequency bandwidth in the differential mode operation.

Furthermore, there is also a need to keep the final differential power amplifier area-effective and easy to implement.

Summary

[0006] The present disclosure describes a differential power amplifier with a common mode change structure, which can provide even harmonic traps in a common mode operation without sacrificing performance at the fundamental frequency in a differential mode operation, and/or can achieve a specific load line impedance at even harmonics in the common mode operation without changing impedance at the fundamental frequency in a differential mode operation. The disclosed differential power amplifier includes transforming circuitry and an amplification stage with a top amplification structure and a bottom amplification structure. The top amplification structure and the bottom amplification structure are configured to receive stage input signals at a top stage input terminal and a bottom stage input terminal, respectively, and configured to provide stage output signals at a top collector and a bottom collector, respectively. The transforming circuitry is connected to the amplification stage at the top collector and the bottom collector and includes the common mode change structure electrically coupled between the top collector and the bottom collector. Herein, during a common mode operation, the common mode change structure is configured to provide a first conducting path between the top collector and ground and a second conducting path between the bottom collector and ground. During a differential mode operation, the common mode change structure is configured to provide a primary capacitance between the top collector and the bottom collector without introducing inductance.

[0007] In one embodiment of the differential power amplifier, during the common mode operation, the common mode change structure is configured to at least partially terminate an even harmonic of a fundamental frequency of the differential power amplifier. [0008] In one embodiment of the differential power amplifier, during the common mode operation, the common mode change structure is configured to at least partially terminate a second harmonic of the fundamental frequency of the differential power amplifier.

[0009] In one embodiment of the differential power amplifier, the common mode change structure includes a first primary capacitor, a second primary capacitor, and a shunt inductor. Herein, the first primary capacitor and the second primary capacitor are electrically coupled in series between the top collector and the bottom collector, and the shunt inductor is electrically coupled between a connection point of the first primary capacitor and the second primary capacitor and ground. The top amplification structure and the bottom amplification structure are identical, and the first primary capacitor and the second primary capacitor are identical. As such, during the common mode operation, the common mode change structure is configured to provide the first conducting path through the first primary capacitor and the shunt inductor, and configured to provide the second conducting path through the second primary capacitor and the shunt inductor. During the differential mode operation, the connection point of the first primary capacitor and the second primary capacitor is equivalent to ground, such that the shunt inductor is hidden. A combination of the first primary capacitor and the second primary capacitor provides the primary capacitance.

[0010] In one embodiment of the differential power amplifier, the common mode change structure further includes a switch, which is electrically coupled between the shunt inductor and ground.

[0011] In one embodiment of the differential power amplifier, the transforming circuitry further includes a transformer and a secondary capacitor. Herein, a primary winding of the transformer is electrically coupled between the top collector and the bottom collector, and a secondary winding of the transformer is electrically coupled between a top transformed terminal and a bottom transformed terminal. The secondary capacitor is electrically coupled between the top transformed terminal and the bottom transformed terminal. [0012] In one embodiment of the differential power amplifier, the top transformed terminal is an output terminal of the differential power amplifier, and the bottom transformed terminal is coupled to ground.

[0013] According to one embodiment, the differential power amplifier further includes an extra amplification stage followed by the amplification stage. Herein, the extra amplification stage is connected to the amplification stage at the top stage input terminal and the bottom stage input terminal.

[0014] According to one embodiment, the differential power amplifier further includes an extra amplification stage following the transforming circuitry. Herein, the extra amplification stage is connected to the transforming circuitry at the top transformed terminal and the bottom transformed terminal.

[0015] According to one embodiment, a differential power amplifier includes transforming circuitry and an amplification stage with a top amplification structure and a bottom amplification structure. The top amplification structure has a top stage input terminal and a top collector, while the bottom amplification structure has a bottom stage input terminal and a bottom collector. The transforming circuitry is connected to the amplification stage at the top collector and the bottom collector and includes a common mode change structure. Herein, the common mode change structure includes a first primary capacitor, a second primary capacitor, and a shunt inductor. The first primary capacitor and the second primary capacitor are electrically coupled in series between the top collector and the bottom collector, and the shunt inductor is electrically coupled between a connection point of the first primary capacitor and the second primary capacitor and ground.

[0016] In one embodiment of the differential power amplifier, the top amplification structure and the bottom amplification structure are identical, and the first primary capacitor and the second primary capacitor are identical.

[0017] In one embodiment of the differential power amplifier, the first primary capacitor, the second primary capacitor, and the shunt inductor are selected, such that a load line impedance at an even harmonic of a fundamental frequency of the differential power amplifier achieves a certain non-zero value during the common mode operation.

[0018] In one embodiment of the differential power amplifier, the first primary capacitor, the second primary capacitor, and the shunt inductor are selected, such that a load line impedance at a second harmonic of the fundamental frequency of the differential power amplifier achieves a certain non-zero value during the common mode operation.

[0019] In one embodiment of the differential power amplifier, the first primary capacitor, the second primary capacitor, and the shunt inductor are selected to be resonated at an even harmonic of the fundamental frequency of the differential power amplifier during the common mode operation.

[0020] In one embodiment of the differential power amplifier, the first primary capacitor, the second primary capacitor, and the shunt inductor are selected to be resonated at a second harmonic of the fundamental frequency of the differential power amplifier during the common mode operation.

[0021] In another aspect, any of the foregoing aspects individually or together, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein.

[0022] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

[0023] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0024] Figure 1 shows a typical non-harmonic-termination differential power amplifier without second harmonic termination. [0025] Figure 2 shows a modified differential power amplifier with modified transforming circuitry to provide second harmonic traps.

[0026] Figure 3 shows an exemplary differential power amplifier with a common mode change structure, which provides even harmonic traps in the common mode operation without sacrificing performance at the fundamental frequency in a differential mode operation, and/or changes load line impedance at even harmonics in the common mode operation without changing load line impedance at the fundamental frequency in the differential mode operation, according to some embodiments of the present disclosure.

[0027] Figures 4A-4C show differential mode half-circuits of the differential power amplifier shown in Figures 1-3.

[0028] Figures 5A-5C show common mode half-circuits of the differential power amplifier shown in Figures 1-3.

[0029] It will be understood that for clear illustrations, Figures 1 -5C may not be drawn to scale.

Detailed Description

[0030] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0031] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. [0032] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0033] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0036] Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter and may or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently re described.

[0037] Figure 1 shows a typical differential power amplifier 10 (e.g., a push- pull amplifier) without harmonic-termination. For the purpose of this simplified illustration, the typical differential power amplifier 10 includes an amplification stage 12 and non-harmonic-termination transforming circuitry 14. The amplification stage 12 is active circuitry part of the typical differential power amplifier 10, while the non-harmonic-termination transforming circuitry 14 is passive circuitry part of the typical differential power amplifier 10. In realistic applications, there might be extra amplification stage(s) before the amplification stage 12 and/or extra amplification stage(s) after the non-harmonic-termination transforming circuitry 14 (not shown in Figure 1).

[0038] Herein, the amplification stage 12 includes a top amplification structure 16 and a bottom amplification structure 18, which are configured to receive stage input signals STIT and STIB at top and bottom stage input terminals AT and AB, respectively, and configured to provide stage output signals STOT and STOB at top and bottom collectors Biand BB, respectively. In one embodiment, the top amplification structure 16 and the bottom amplification structure 18 are identical. [0039] The non-harmonic-termination transforming circuitry 14 includes a primary capacitor 20, a transformer 22 with a primary winding 24 and a secondary winding 26, and a secondary capacitor 28. The primary capacitor 20 is electrically coupled between the top collector BT of the top amplification structure 16 and the bottom collector BB of the bottom amplification structure 18. The primary winding 24 of the transformer 22 is also electrically coupled between the top collector BT and the bottom collector BB. The secondary winding 26 of the transformer 22 is magnetically coupled with the primary winding 24 of the transformer 22 and is electrically coupled between a top transformed terminal CT and a bottom transformed terminal CB. The secondary capacitor 28 is also electrically coupled between the top transformed terminal CT and the bottom transformed terminal CB. Transformed signals TRT and TRB are provided at the top transformed terminal CT and the bottom transformed terminal CB, respectively.

[0040] The primary capacitor 20 and the secondary capacitor 28 are configured to tune out the inductance of the transformer 22, so as to achieve a relatively stable load line impedance within a fundamental bandwidth of the typical differential power amplifier 10. Herein, a load line impedance refers to a total impedance seen at collectors of one amplification stage (e.g., a total impedance of the non-harmonic-termination transforming circuitry 14 seen at the collectors BT and BB of the amplification stage 12). A fundamental bandwidth of differential power amplifier refers to a bandwidth, within which, satisfactory amplification performance (e.g., <3dB loss) is achieved. A fundamental frequency of the differential power amplifier is a frequency within the fundamental bandwidth. For analysis purposes, we assume that the capacitances of the primary and secondary capacitors 20 and 28 (corresponding to the transformer 22) to achieve the desired load line impedance are Cpri and Csec, respectively. [0041] Notice that, if there is an extra amplification stage before the amplification stage 12 and no amplification stage after the non-harmonic- termination transforming circuitry 14, the amplification stage 12 is an output amplification stage and the transforming circuitry 14 is output circuitry. In such circumstance, the extra amplification stage is connected to the amplification stage 12 at the stage input terminals AT and AB. The top transformed terminal CT is an output terminal providing the transformed/output signal TRito external circuits (not shown), while the bottom transformed terminal CB IS coupled to ground with the zero-valued transformed signal TRB. In addition, if there is an extra amplification stage after the non-harmonic-termination transforming circuitry 14 and no amplification stage before the amplification stage 12, the amplification stage 12 is an input amplification stage and the transforming circuitry 14 is internal transforming circuitry. In such circumstance, the extra amplification stage is connected to the non-harmonic-termination transforming circuitry 14 at the transformed terminals CT and CB. The transformed signals TRT and TRB at the transformed terminals CT and CB are input signals for the next amplification stage.

[0042] The typical differential power amplifier 10 cannot eliminate any signal harmonic, which, however, might be highly desired by some certain class operations. Therefore, in order to terminate certain harmonics (e.g., the second harmonic), harmonic trapping circuits may be added to the typical differential power amplifier 10. As illustrated in Figure 2, a modified differential power amplifier 30 includes modified transforming circuitry 34, which can provide second harmonic traps (extra amplification stage(s) before the amplification stage 12 and/or extra amplification stage(s) after the modified transforming circuitry 34 are not shown herein). [0043] Compared to the typical differential power amplifier 10, the modified differential power amplifier 30 includes the same active amplification stage 12 and the different transforming circuitry 34. Compared to the non-harmonic- termination transforming circuitry 14 in the typical differential power amplifier 10, the modified transforming circuitry 34 in the modified differential power amplifier 30 includes an alternative primary capacitor 20A, extra trap capacitors 36 (i.e., a first trap capacitor 36-1 and a second trap capacitor 36-2), and extra trap inductors 38 (i.e., a first trap inductor 38-1 and a second trap inductor 38-2). Herein, the modified transforming circuitry 34 in the modified differential power amplifier 30 also includes the same transformer 22 (i.e., the same primary winding 24 and secondary winding 26) and the same secondary capacitor 28 as the non-harmonic-termination transforming circuitry 14.

[0044] The alternative primary capacitor 20A is electrically coupled between the top collector Btoί the top amplification structure 16 and the bottom collector BB of the bottom amplification structure 18. The first trap capacitor 36-1 and the first trap inductor 38-1 are electrically coupled in series between the top collector BT and ground to provide a first extra path P1 from the top collector BT of the top amplification structure 16 to ground. The second trap capacitor 36-2 and the second trap inductor 38-2 are electrically coupled in series between the bottom collector BB and ground to provide a second extra path P2 from the bottom collector BB of the bottom amplification structure 18 to ground. Herein, the first trap capacitor 36-1 and the first trap inductor 38-1 are selected to be resonated near the second harmonic of the fundamental frequency of the modified differential power amplifier 30 (i.e., the second harmonic impedance equal to zero through the first extra path P1). Similarly, the second trap capacitor 36-2 and the second trap inductor 38-2 are selected to be resonated near the second harmonic of the fundamental frequency of the modified differential power amplifier 30 (i.e., the second harmonic impedance equal to zero through the second extra path P2). As such, the second harmonic in the stage output signals STOT and STOB can be trapped by the first trap capacitor 36-1 /first trap inductor 38-1 pair and the second trap capacitor 36-2/second trap inductor 38-2 pair (more details in the following paragraphs). To compensate for additional impedance from the extra trap capacitors 36 and the extra trap inductors 38, so as to obtain the desired load line impedance as in the typical differential power amplifier 10, the alternative primary capacitor 20A in the modified differential power amplifier 30 is tuned (e.g., having a capacitance Cpri2 smaller than the capacitance Cpri of the primary capacitor 20 in the typical differential power amplifier 10). Each trap capacitor 36 has capacitance Cb, and each trap inductor 38 has inductance Lb.

[0045] Unfortunately, the modified transforming circuitry 34 with the extra trap capacitors 36 and the extra trap inductors 38 will add loss and reduce fundamental bandwidth compared to the typical differential power amplifier 10 (more details in the following paragraphs). And the extra trap inductors 38 will also increase amplifier area consumption compared to the typical differential power amplifier 10.

[0046] Figure 3 illustrates an exemplary differential power amplifier 40 with improved transforming circuitry 44, which can provide even harmonic traps in a common mode operation without sacrificing performance at the fundamental frequency in a differential mode operation, according to some embodiments of the present disclosure.

[0047] The exemplary differential power amplifier 40 includes the same active amplification stage 12 as the typical differential power amplifier 10. Compared to the non-harmonic-termination transforming circuitry 14 in the typical differential power amplifier 10, the improved transforming circuitry 44 in the exemplary differential power amplifier 40 includes a first primary capacitor 46-1 and a second primary capacitor 46-2 instead of one primary capacitor 20, and a shunt inductor 48. Herein, the improved transforming circuitry 44 in the exemplary differential power amplifier 40 also includes the same transformer 22 (i.e., the same primary winding 24 and secondary winding 26) and the same secondary capacitor 28 as the non-harmonic-termination transforming circuitry 14.

[0048] In the improved transforming circuitry 44, the first primary capacitor 46- 1 and the second primary capacitor 46-2 are electrically coupled in series between the top collector BT of the top amplification structure 16 and the bottom collector BB of the bottom amplification structure 18. The shunt inductor 48 is electrically coupled between a connection point D of the first primary capacitor 46-1 and the second primary capacitor 46-2 and ground. As such, the first primary capacitor 46-1 and the shunt inductor 48 are capable of providing a first conducting path Pci, and the second primary capacitor 46-2 and the shunt inductor 48 are capable of providing a second conducting path Pc2. The first primary capacitor 46-1 , the second primary capacitor 46-2, and the shunt inductor 48 form a common mode change structure 50. In some cases, it may be beneficial for the improved transforming circuitry 44 to utilize the common mode change structure 50 in certain operating modes and switch it off in other modes, which can be done with a switch 51 coupled between the shunt inductor 48 and ground.

[0049] To obtain the desired load line impedance as in the typical differential power amplifier 10, a total capacitance of the first primary capacitor 46-1 and the second primary capacitor 46-2 in the exemplary differential power amplifier 40 should be Cpri. In one embodiment, the first primary capacitor 46-1 and the second primary capacitor 46-2 are identical, and each has a capacitance of 2xCpri, which is twice the primary capacitor 20. Because of such symmetry, the connection point D is capable of being a virtual ground (i.e., an alternative current ground) in the differential mode (more details in the following paragraphs). In addition, the first primary capacitor 46-1 , the second primary capacitor 46-2, and the shunt inductor 48 may be selected to be resonated at an even harmonic of the fundamental frequency of the exemplary differential power amplifier 40 in the common mode (i.e., such even harmonic impedance equal to zero through Pci and Pc2). For instance, the first primary capacitor 46-1 , the second primary capacitor 46-2, and the shunt inductor 48 are selected to be resonated at a second harmonic of the fundamental frequency of the exemplary differential power amplifier 40 in the common mode: where wo is the fundamental frequency of the exemplary differential power amplifier 40, 2Cpri is the capacitance of one (first/second) primary capacitor 46, and Lc is the inductance of the shunt inductor 48. As such, the second harmonic impedance equal to zero through Pci and Pc2, and the second harmonic in the stage output signals STOT and SToBcan be trapped by the common mode change structure 50 (more details in the following paragraphs).

[0050] In one embodiment, the first primary capacitor 46-1 , the second primary capacitor 46-2, and the shunt inductor 48 may be selected to be resonated near (but not equal to) one even harmonic (e.g., the second harmonic) of the fundamental frequency of the exemplary differential power amplifier 40 in the common mode. As such, the even harmonic impedance (e.g., the second harmonic impedance) is close to (but not equal to) zero through the first and second conducting paths Pci and Pc2 in the common mode. In consequence, the even harmonic (e.g., the second harmonic) in the stage output signals STOT and SToBcan be partially terminated by the common mode change structure 50 (i.e., reducing the even harmonic power in the stage output signals STOT and STOB). [0051] In some applications, the common mode change structure 50 is not configured to trap the even harmonic in the stage output signals STOT and STOB, but to achieve a specific even harmonic impedance (non-zero impedance) in the common mode. Therefore, the first primary capacitor 46-1 , the second primary capacitor 46-2, and the shunt inductor 48 do not need to be resonated near or at the even harmonic of the fundamental frequency of the exemplary differential power amplifier 40.

[0052] Similar to the typical differential power amplifier 10, the exemplary differential power amplifier 40 may also include extra amplification stage(s) before the amplification stage 12 and/or extra amplification stage(s) following the improved transforming circuitry 44. If there is an extra amplification stage (not shown) before the amplification stage 12 and no amplification stage following the improved transforming circuitry 44, the amplification stage 12 is an output amplification stage and the improved transforming circuitry 44 is output circuitry. In such circumstance, the extra amplification stage is connected to the amplification stage 12 at the stage input terminals AT and AB (not shown in Figure 3). The top transformed terminal CT is or is connected to an output terminal OUT, which provides the transformed/output signal TRT to external circuits (not shown), while the bottom transformed terminal CB IS coupled to ground (i.e., the transformed signal TRB is zero).

[0053] Alternatively, if there is an extra amplification stage 52 following the improved transforming circuitry 44 and no amplification stage before the amplification stage 12, the amplification stage 12 is an input amplification stage and the improved transforming circuitry 44 is internal transforming circuitry. In such circumstance, the transformed signals TRT and TRB at the transformed terminals CT and CB are input signals for the next amplification stage 52. For instance, the extra amplification stage 52 includes an extra top amplification structure 54 and an extra bottom amplification structure 56. The extra top amplification structure 54 is electrically coupled to the top transformed terminal CT and is configured to receive the transformed signal TRT from the top transformed terminal CT. The extra bottom amplification structure 56 is electrically coupled to the bottom transformed terminal CB and is configured to receive the transformed signal TRB from the bottom transformed terminal CB. In one embodiment, the extra top amplification structure 54 and the extra bottom amplification structure 56 are identical.

[0054] Furthermore, if there is the extra amplification stage 52 following the improved transforming circuitry 44 and another extra amplification stage before the amplification stage 12 (not shown), the amplification stage 12 is an internal amplification stage and the improved transforming circuitry 44 is the internal transforming circuitry. In such circumstance, the stage input signals STIT and STIB at the stage input terminals AT and AB are output signals from the previous amplification stage, while the transformed signals TRT and TRB at the transformed terminals CT and CB are the input signals for the next amplification stage 52.

[0055] Clearly, the improved transforming circuitry 44 with the common mode change structure 50 can be used at various locations within a differential power amplifier. For instance, the improved transforming circuitry 44 with the common mode change structure 50 can be the output circuitry, which is after an output amplification stage (i.e., not followed by any amplification stage). For another instance, the improved transforming circuitry 44 with the common mode change structure 50 can be the internal circuitry, which is following one amplification stage and followed by another amplification stage. In different applications, the improved transforming circuitry 44 with the common mode change structure 50 may be used after any or all amplification stages (not shown). Each common mode change structure 50 can provide even harmonic traps in the common mode operation without sacrificing performance at the fundamental frequency in the differential mode operation, and/or can achieve a specific even harmonic impedance in the common mode operation without changing load line impedance at the fundamental frequency in the differential mode operation.

[0056] It is easier to understand how a differential power amplifier works when it is viewed as differential mode and common mode half circuits. A half circuit is what is seen by one (top or bottom) side of the differential power amplifier.

Figures 4A-4C show differential mode half-circuits of the differential power amplifier shown in Figures 1-3. For simplicity and clarity, half circuits shown herein only illustrate a circuitry portion between the stage input terminal AT of the top amplification structure 16 and the top collector BT of the top amplification structure 16 before the transformer 22.

[0057] Differential power amplifiers operate in the differential mode at the fundamental frequency and odd harmonics, while operating in the common mode at even harmonics. During the differential mode operation, the stage input signals STIT and STIB received by the top amplification structure 16 and the bottom amplification structure 18, respectively, are inverted to each other (i.e., the stage input signals STIT and STIB have a same amplitude but opposite phases). As such, when the top amplification structure 16 and the bottom amplification structure 18 are identical, the stage output signals STOT and STOB at the top collector BT of the top amplification structure 16 and the bottom collector BB of the bottom amplification structure 18, respectively, are also inverted to each other (i.e., the stage output signals STOT and STOB have a same amplitude but opposite phases). The differential mode half-circuit of the typical differential power amplifier 10 and the differential mode half-circuit of the exemplary differential power amplifier 40 have a same circuit configuration, as illustrated in Figures 4A and 4C. It is because that in the exemplary differential power amplifier 40, the connection point D of the first primary capacitor 46-1 and the second primary capacitor 46-2 is a virtual ground during the differential mode operation (this virtual ground is formed by the symmetry of the first primary capacitor 46-1 and the second primary capacitor 46-2, and the inversion of the stage output signals STOT and STOB). AS such, the shunt inductor 48 is hidden (both sides of the shunt inductor 48 are connected to ground) and will not affect the load line impedance at the fundamental frequency /fundamental bandwidth in the differential mode operation. In the typical differential power amplifier 10, an equivalent primary capacitor 20’ is coupled between the top collector BT of the top amplification structure 16 and ground, where a capacitance (2xCpri) of the equivalent primary capacitor 20’ is twice the capacitance (Cpri) of the primary capacitor 20. There should be another equivalent primary capacitor 20’ that is coupled between the bottom collector BB of the bottom amplification structure 18 and ground (not shown in Figure 4A). As such, a combination of the two equivalent primary capacitors 20’ can achieve the primary capacitor 20. In the exemplary differential power amplifier 40, the first primary capacitor 46-1 is coupled between the top collector BT of the top amplification structure 16 and ground (i.e., the connection point D during the differential mode operation) and has the capacitance 2 ^* Cpri. The second primary capacitor 46-2 is coupled between the bottom collector BB of the bottom amplification structure 18 and ground (i.e., the connection point D during the differential mode operation) and has the capacitance 2 ^* Cpri (not shown in Figure 4C). As such, a combination of the first primary capacitor 46-1 and the second primary capacitor 46-2 can achieve a total capacitance Cpri.

[0058] On the other hand, the extra trap inductors 38 in the modified differential power amplifier 30 can still be seen in the differential mode, as illustrated in Figure 4B. In the modified differential power amplifier 30, an equivalent alternative primary capacitor 20A’ is coupled between the top collector BT of the top amplification structure 16 and ground, where a capacitance (2xCpri2) of the equivalent alternative primary capacitor 20A’ is twice the capacitance (Cpri2) of the alternative primary capacitor 20A. There should be another equivalent alternative primary capacitor 20A’ that is coupled between the bottom collector BB of the bottom amplification structure 18 and ground (not shown in Figure 4B). As such, a combination of the two equivalent alternative primary capacitors 20A’ can achieve the alternative primary capacitor 20A. In addition, the first and second extra paths P1 and P2 are still conducted in the modified differential power amplifier 30 during the differential mode operation.

The first extra path P1 is formed by the first trap capacitor 36-1 and the first trap inductor 38-1 coupled in series between the top collector BT of the top amplification structure 16 and ground, and the second extra path P2 is formed by the second trap capacitor 36-2 and the second trap inductor 38-2 coupled in series between the bottom collector BB of the bottom amplification structure 18 and ground (not shown in Figure 4B). The first and second trap inductors 38-1 and 38-2 affect the load line impedance at the fundamental frequency and the odd harmonics, so as to add loss and decrease the fundamental bandwidth. [0059] Figures 5A-5C show common mode half-circuits of the differential power amplifier shown in Figures 1-3. In the common mode operation, the stage input signals STIT and STIB received by the top amplification structure 16 and the bottom amplification structure 18, respectively, are identical (i.e., the stage input signals STIT and STIB have the same amplitude and phase). As such, when the top amplification structure 16 and the bottom amplification structure 18 are identical, the stage output signals STOT and STOB at the top collector BT of the top amplification structure 16 and the bottom collector BB of the bottom amplification structure 18, respectively, are also identical (i.e., the stage output signals STOT and STOB have the same amplitude and phase). In the typical differential power amplifier 10, the top collector BT of the top amplification structure 16 and the bottom collector BB of the bottom amplification structure 18 always have a same voltage, thus there is no signal passing through the primary capacitor 20, and the primary capacitor 20 is hidden, as illustrated in Figure 5A. It is clear that during the common mode operation, the typical differential power amplifier 10 does not provide any harmonic termination.

[0060] During the common mode operation, in the modified differential power amplifier 30, there is no signal passing through the alternative primary capacitor 20A (the stage output signals STOT and STOB at the top collector BT and the bottom collector BB, respectively, are identical), and consequently, the alternative primary capacitor 20A is hidden. Different from the typical differential power amplifier 10, in the modified differential power amplifier 30, signals could pass through the first and second extra paths P1 and P2 (i.e., from the collector BT/BB to ground). Figure 5B illustrates the common mode half-circuit of the modified differential power amplifier 30 with the first extra path P1 (the first extra path P1 is formed by the first trap capacitor 36-1 and the first trap inductor 38-1 coupled in series between the top collector BT of the top amplification structure 16 and ground). The modified differential power amplifier 30 also provides the second extra path P2 (the second extra path P2 is formed by the second trap capacitor 36-2 and the second trap inductor 38-2 coupled in series between the bottom collector BB of the bottom amplification structure 18 and ground) during the common mode operation (not shown in Figure 5B). The first trap capacitor 36-1 and the first trap inductor 38-1 can be selected to be resonated near/at the second harmonic of the fundamental frequency of the modified differential power amplifier 30 (i.e., the second harmonic impedance is equal to zero through the first extra path P1), and the second trap capacitor 36-2 and the second trap inductor 38-2 are selected to be resonated near/at the second harmonic of the fundamental frequency of the modified differential power amplifier 30 (i.e., the second harmonic impedance is equal to zero through the second extra path P2). As such, the second harmonic of the fundamental frequency can be terminated by the first trap capacitor 36-1 /first trap inductor 38-1 pair and the second trap capacitor 36-2/ second trap inductor 38-2 pair in the common mode operation (i.e., the second harmonic in the stage output signals STOT and STOB can be trapped by the first trap capacitor 36-1 /first trap inductor 38-1 pair and the second trap capacitor 36-2/second trap inductor 38-2 pair).

[0061] During the common mode operation, in the exemplary differential power amplifier 40, the top collector BT of the top amplification structure 16 and the bottom collector BB of the bottom amplification structure 18 provide the identical stage output signals STOT and STOB. However, due to the shunt inductor 48 being coupled to ground, signals could pass through the first and second conducting paths Pci and Pc2 (i.e., from the collector BT/BB to ground). Figure 5C illustrates the common mode half-circuit of the exemplary differential power amplifier 40 with the first conducting path Pci. The first conducting path Pci is formed by the first primary capacitor 46-1 and an equivalent shunt inductor 48’ coupled in series between the top collector BT of the top amplification structure 16 and ground, where the equivalent shunt inductor 48’ has an inductance 2xLc twice the inductance Lc of the shunt inductor 48. The exemplary differential power amplifier 40 also provides the second conducting path Pc2, which is formed by the second primary capacitor 46-2 and another equivalent shunt inductor (with a 2xLc inductance) coupled in series between the bottom collector BB of the bottom amplification structure 18 and ground, during the common mode operation (not shown in Figure 5C). As such, a combination of the first conducting path Pci and the second conducting path Pc2 can achieve the inductance Lc as the shunt inductor 48.

[0062] In one embodiment, the first primary capacitor 46-1 , the second primary capacitor 46-2, and the shunt inductor 48 are selected to be resonated at or near an even harmonic (e.g., the second harmonic) of the fundamental frequency of the exemplary differential power amplifier 40 (i.e., the even harmonic impedance equal or close to zero through the first conducting path Pci and the second conducting path Pc2). As such, this even harmonic in the stage output signals STOT and STOB can be at least partially terminated by the common mode change structure 50.

[0063] During the common mode operation, the modified differential power amplifier 30 and the exemplary differential power amplifier 40 have a similar circuit configuration but will provide different harmonic bandwidth. As mentioned above, when the extra trap capacitors 36 and the extra trap inductors 38 are used in the modified transforming circuitry 34 of the modified differential power amplifier 30, the primary capacitor 20 with the capacitance Cpri is changed to the alternative primary capacitor 20A with reduced capacitance Cpri2 to compensate for the additional capacitance at the fundamental frequency. To get the widest bandwidth out of the trap, the capacitance Cb of the first/second extra trap capacitor 36 is increased until the capacitance Cpri2 of the alternative primary capacitor 20A is reduced to zero. If the capacitance Cb of the first/second extra trap capacitor 36 gets larger than this limit, it is difficult to maintain the desired load line for the modified differential power amplifier 30. Herein, Eq.2 is used to solve the maximum value of the capacitance Cb of the first/second extra trap capacitor 36:

(equating the load line impedance of the typical differential power amplifier 10 and the load line impedance of the modified differential power amplifier 30 at the fundamental frequency wo, and setting Cpri2 to zero). In addition, since the first trap capacitor 36-1 and the first trap inductor 38-1 are selected to be resonated at the second harmonic of the fundamental frequency, so

By solving Eq. 3 for Lb, then plugging it into Eq. 2 to solve for Cb_max

C _bjna x — 1-5 x C _pri Eq. 4 The capacitance of the first primary capacitor 46-1 used for the second harmonic trap is 2Cpri, which is 33% larger than the maximum capacitance Cb_max of the first extra trap capacitor 36-1. Near resonance, the rate of change of reactance with respect to frequency is inversely proportional to capacitance. Therefore, the bandwidth of the second harmonic trap formed from the first primary capacitor 46-1 (2Cpri) is at least 33% larger than the bandwidth of the second harmonic trap formed from the first trap capacitor 36-1 (Cb). [0064] Compared to the modified differential power amplifier 30 with the modified transforming circuitry 34, the exemplary differential power amplifier 40 with the improved transforming circuitry 44 has another advantage in size. The improved transforming circuitry 44 may have a same capacitor area as the modified transforming circuitry 34 but saves area on inductors. The improved transforming circuitry 44 includes one shunt inductor 48, while the modified transforming circuitry 34 includes two trap inductors 38. Also, the shunt inductor 48 is smaller than one trap inductor 38 (e.g., the shunt inductor 48 may be equivalent to a parallel combination of the first trap inductor 38-1 and the second inductor 38-2, Lc=Lb/2). Therefore, the inductance needed for the improved transforming circuitry 44 may be only 25% of the sum of inductances needed for the modified transforming circuitry 34.

[0065] For certain class operations, the common mode change structure 50 in the exemplary differential power amplifier 40 is not configured to trap the even harmonic signal during the common mode, but is configured to achieve a specific even harmonic impedance in the common mode operation without changing a load line impedance at the fundamental frequency in the differential mode operation. During the differential mode operation, the shunt inductor 48 is hidden (both sides of the shunt inductor 48 are connected to ground), such that the exemplary differential power amplifier 40 can maintain the same load line impedance at the fundamental frequency. During the common mode operation, the shunt inductor 48 is conducted, such that the exemplary differential power amplifier 40 can achieve a specific even harmonic impedance. Neither the typical differential power amplifier 10 nor the modified differential power amplifier 30 can achieve that.

[0066] It is contemplated that any of the foregoing aspects, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein. [0067] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.