Technical field

The disclosure relates to techniques for transmission of data signals through galvanic-isolation barriers.

One or more embodiments may be used, for example, in lighting systems.

Technological background

The term "galvanic-isolation barrier" (or, more briefly, "electrical isolation", or else again "galvanic isolation") applies to circuit arrangements where between two points at a different electrical potential there is no circulation of DC current.

Electrical energy may, however, be exchanged through such a barrier by resorting to other physical phenomena such as electromagnetic induction or optical phenomena.

A solution commonly adopted for transferring data signals through such an isolation barrier envisages recourse to an optical coupler.

In the case where it is desired to transfer data signals from the secondary side to the primary side of the barrier, this solution can encounter difficulties of application, in particular when (as in the case of outdoor applications) it is desired to provide isolation levels capable of withstanding overload voltages in the region of 10 kV.

In principle, the above problem could be tackled using optical couplers of large dimensions.

This solution is not, however, particularly appreciated, also as regards driving of such an optical coupler.

Object and summary

The object of one or more embodiments is to tackle the problem outlined previously.

According to one or more embodiments, the above object can be achieved thanks to a circuit having the characteristics recalled in the ensuing claims.

One or more embodiments may regard a corresponding system (comprising a galvanic-isolation barrier and a device for transfer of data signals through the barrier).

One or more embodiments may regard a corresponding method.

The claims form an integral part of the technical teachings provided herein in relation to the embodiments .

One or more embodiments may afford one or more of the following advantages: high isolation level, even higher than 10 kV; small dimensions, also in relation to an area occupied on a PCB (Printed Circuit Board); low-cost components; and high switching speed.

Brief description of the annexed drawings

One or more embodiments will now be described, purely by way of non-limiting example, with reference to the annexed drawings, wherein:

Figure 1 is a general representation of a galvanic- isolation barrier where embodiments of the present invention can find application;

Figure 2 is a block diagram of possible implementation of embodiments of the present invention;

Figure 3 illustrates a component (transformer) that can be used in embodiments of the present invention;

Figure 4 is a circuit diagram of embodiments of the present invention; and

Figure 5 comprises a number of time charts, designated by A, B, C and D, representing possible plots of signals in embodiments of the present invention. Detailed description

In the ensuing description, various specific details are illustrated in order to enable an in-depth understanding of various examples of embodiments according to the disclosure. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that the various aspects of the embodiments will not be obscured.

Reference to "an embodiment" or "one embodiment" in the framework of the present description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as "in an embodiment" or "in one embodiment" that may be present in various points of the present description do not necessarily refer exactly to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

The references used herein are provided merely for convenience and hence do not define the sphere of protection or the scope of the embodiments.

It will be appreciated that, for brevity - unless the context indicates otherwise - like parts or elements are denoted in the various figures by like references, without the corresponding description being repeated for each figure.

Once again for brevity and simplicity of illustration, in the sequel of the present description, one and the same reference (for example, IS or OS) may be used to designate both a node or line of a circuit and a signal that is present at said node or line of the circuit. Represented schematically in Figure 1 is a galvanic-isolation barrier comprising a primary side PS and a secondary side SS coupled together via a transformer designated by TGB.

Such a barrier enables transfer of energy from the primary side to the secondary side, for example for supplying light sources (not visible in the drawings) arranged on the secondary side SS with energy supplied on the primary side, for example via an electric mains supply (which is not visible in the drawings either).

The galvanic barrier may likewise make it possible to perform functions, such as voltage-level transformations, power-factor correction, dimming, various adjustments, etc.

The criteria of construction and operation of the circuits exemplified herein by the blocks PS (primary side) and SS (secondary side) may be extremely varied, also considering the mode of application or use envisaged.

The above criteria are to be deemed certainly known to persons skilled in the art and are hence such as not to require a more detailed description herein. It will, rather, be noted that one or more embodiments may be deemed amply "transparent" in regard to the criteria of construction and operation of the galvanic barrier.

One or more embodiments tackle the issue of possible transmission of a data signal between the primary side PS and the secondary side SS, for example as regards the possibility of ensuring transmission of data signals from the secondary side SS to the primary side PS, for instance for adjustment purposes.

As has already been said, a currently adopted solution envisages the use of an optical coupler (optocoupler) constituted by a light-radiation generator (for example, a LED) and by a photovoltaic converter (such as a photodiode or a phototransistor).

As has been said in the introductory part of the present description, the use of optocouplers may encounter difficulties in particular when we have to do with barriers that are to be exposed (maintaining their characteristics of isolation) to voltage overloads in the region of 10 kV.

One or more embodiments envisage tackling the above problem in the terms represented schematically in Figure 2, i.e., envisaging a communication device 10 capable of ensuring transmission of data signals from one side to the other of the galvanic barrier.

For instance (in what follows reference will be made chiefly to this mode of use, even though this is not to be deemed in itself imperative), the device 10 may be designed to ensure transfer of data signals from the secondary side SS to the primary side PS of the galvanic- isolation barrier.

Basically, the device 10 as illustrated herein comprises: transmission or transmitter circuitry 12, which can be coupled to one of the sides of the galvanic-isolation barrier (for example, to the secondary side SS); receiving or receiver circuitry 14, which can be coupled to the other side of the galvanic-isolation barrier, i.e., (in the example considered herein, which, it is once again recalled, is to be deemed such) to the primary side PS of the galvanic barrier; and a data-signal-transfer transformer 16 set between the transmitter circuitry 12 and the receiver circuitry 14.

As illustrated herein, the transformer 16 comprises a primary winding 161 (coupled to the transmitter circuitry 12) and a secondary winding 162 (coupled to the receiver circuitry 14). Advantageously, the transformer 16 (which may in general be deemed at least partially distinct from the "main" transformer TGB of the galvanic barrier as represented in Figure 1) may be a toroidal transformer, as represented schematically in Figure 3.

Such a transformer is suited to being provided in the form of a toroidal core 163 set on a supporting substrate 164 (in practice, a small PCB) of small dimensions, for example with a dimension D defined between mounting holes provided on the PCB 164 in the region of 10 mm or less.

A transformer 16 of this nature can be built so that it has small dimensions using a primary winding 161 and a secondary winding 162 having a small number of turns, for example less than 10 turns.

For instance, the windings 161 and 162 may comprise five turns each, hence with a unit transformer ratio.

Added to the above is the possibility of setting the two windings (as may be appreciated in Figure 3) in diametrally opposite positions of the toroidal core 163, hence with the possibility of providing a rather wide spacing (designated by SW in Figure 3) between the primary winding 161 and the secondary winding 162.

These aspects make it possible to achieve a high level of isolation between the two windings with an accordingly reduced degree of coupling (mutual inductance).

It is possible to take into account the above reduced coupling by envisaging that the transmitter circuitry 12 will comprise a pulse generator that generates very sharp pulses (the so-called spikes) at the transitions between the logic levels (LL1 or "high" logic level and LL2 or "low" logic level, in the example considered herein) of an input data signal that is to be transmitted through the galvanic barrier. For instance, the aforesaid input logic signal (designated by IS in Figure 4) may be a binary signal generated by a (micro)controller not visible in the figures - located, for example, on the secondary side of the galvanic barrier.

The pulse generator provided in the transmitter circuitry 12 is able to generate and apply to the primary winding 161 of the transformer 16 (voltage) spikes at the logic-level transitions of the input signal IS.

For instance, as represented also in Figure 5, it is possible to envisage (by operating in a way in itself known) that the spike generator in question will behave as a differentiator configured to generate positive spikes at the low-to-high transitions (LL2 to LL1), i.e., at the rising edges, of the data signal IS and negative spikes at the high-to-low transitions (LL1 to LL2), i.e., at the falling edges, of the data signal IS.

Of course, this choice is not imperative, since it is possible to adopt combinations of signs opposite to the ones just described.

In a complementary way, one or more embodiments may envisage that the receiver circuitry 14 will comprise a squarer circuit coupled to the secondary winding 162 of the transformer 16 that is able to "square" the spike transmitted through the transformer 16 so as to (re)construct at output a logic signal (designated by OS in Figure 4) that has transitions between the logic levels LL1 and LL2 at the aforesaid spikes denoted as a whole by SPk and SPk+i.

For instance, as represented on the right in Figure 2, it is possible to envisage (operating in a way in itself known) that the squarer circuit 14 will behave as a sort of bistable circuit configured to generate at output a logic signal with low-to-high transitions (LL2 to LL1), i.e., rising edges, in the presence of positive spikes, and high-to-low transitions (LL1 to LL2), i.e., falling edges, in the presence of negative spikes.

Of course, this choice is not imperative since it is possible to adopt combinations of signs opposite to the ones just described.

For instance, as represented in Figures 4 and 5, it is, instead, possible to envisage that the squarer circuit 14 will be configured to generate at output a logic signal with low-to-high transitions (LL2 to LL1), i.e., rising edges, in the presence of negative spikes, and high-to-low transitions (LL1 to LL2), i.e., falling edges, in the presence of positive spikes.

An action of reconstruction of the data signal transmitted through the transformer 16 can hence be obtained either without reversal of polarity (as in the case of the example represented schematically in Figure 2), or with reversal of polarity, as in the case of the circuit implementation to which Figure 4 refers, with the plot of the signals represented in Figure 5.

The circuit diagram of Figure 4 refers, purely by way of example, to a possible implementation regarding its use for the transmission of a data signal IS (for example, with two logic levels LL1, LL2) coming from a data source DS.

The source D2 may, purely by way of non-limiting example, be a processing circuit, such as a microcontroller located on the secondary side SS of the galvanic barrier with the corresponding data signal, designated by IS, that is to be transmitted and received (as output signal OS) by a circuit that uses the aforesaid data. This circuit, designated by UD, may itself also be another control device, such as a microcontroller, located on the primary side PS of the galvanic barrier.

In one or more embodiments, the spike-generator circuit, designated by 121 in Figure 4, may comprise a capacitor 122 coupled, at a coupling node Nl, to the primary winding 161 of the transformer 16.

For instance, the capacitor 122 may be a capacitor with a value of capacitance in the region of 3.3 nF (hence a capacitor having a low capacitance and small dimensions) referenced to the transmitter ground GNDT coupled, at the node Nl, to a charge-transfer (resistive) network, comprising resistors R3, R9 and RIO, which acts under the control of a driver circuit 123 (in the figure, LI and L2 are the inductances associated with the primary and secondary windings of the transformer 16).

The driver circuit 123 operates so as to give rise to modes of charging and discharging of the capacitor 122 that are to lead to generation of the spikes applied to the primary winding 161 of the transformer 16.

As exemplified in Figure 4, the network R3, R9 and RIO for transfer of charge from and to the capacitor 122 operates as a function of the level of the signal IS sent at its input and in particular as a function of the transitions thereof between the logic level LL1 and the logic level LL2.

As exemplified in Figure 4, the driver circuit 123 comprises a first electronic switch Q1 and a second electronic switch Q2. These are electronic switches that may be provided, for example, in the form of transistors, such as bipolar transistors with opposite polarities (for example, n-p-n for the transistor Q1 and p-n-p for the transistor Q2).

The two electronic switches Q1 and Q2 are arranged with the current paths that pass through them (emitter- collector in the case of bipolar transistors here mentioned by way of example) cascaded with respect to one another in a current-flow line between a transmitter- supply node, designated by ST, and the transmitter ground, designated by GNDT.

The electronic switches Q1 and Q2 have their respective control nodes (bases, in the example of bipolar transistors provided herein by way of example) coupled via resistors R1 and R2 to the input node, to which the logic signal IS is applied.

The opposite polarities (n-p-n and p-n-p) of the transistors Q1 and Q2 are hence such that the first switch Q1 and the second switch Q2 are alternately rendered conductive and non-conductive as a function of the logic level (high or low, LL1 or LL2) of the input signal IS.

For instance, with reference to the polarities here considered, when the input signal IS is at a high logic level LL1, the transistor Q1 is conductive (ON) and the transistor Q2 is non-conductive (OFF). The capacitor 122 hence tends to charge towards the supply voltage ST with a time constant given by the network R3, R9, R10, LI.

In a complementary way, when the input signal IS is at the low logic level LL2, the transistor Q1 is non- conductive (OFF) and the transistor Q2 is conductive (ON). The capacitor 122 hence tends to discharge towards ground GNDT with a time constant given by the network R3, R9, R10, LI.

In this way, the signal at the node N2 intermediate between the switches Q1 and Q2 may present, for example, a square-wave plot (see the time chart A of Figure 5) that in fact reproduces the plot of the logic input signal IS with the voltage across the capacitor 122 that may present a plot such as the one represented in the time chart B in Figure 5, i.e., a plot that substantially reproduces the plot of the input signal IS.

The inductive behaviour of the primary winding 161 of the transformer 16 causes the process of charging discharging of the capacitor 122 to give rise to spikes at the transitions between the logic levels of the signals of plots A and B.

Such spikes have opposite signs, i.e., in the case illustrated here by way of example, a negative sign at the falling edges of the signals A and B and a positive sign at the rising edges of the signals of plots A and B. A possible plot of these spikes is exemplified in the time chart C of Figure 5.

In other words: during the capacitor-charging mode 122, the coupling node N1 at the primary winding 161 of the transformer 16 is coupled to the supply line/node ST through the node N2, and the switch Q1 is rendered conductive (with the switch Q2 non-conductive); and during the capacitor-discharging mode 122, the coupling node N1 at the primary winding 161 of the transformer 16 is coupled to ground GNDT through the node N2, and the switch Q2 is rendered conductive (with the switch Q1 non-conductive).

The persons skilled in the art will appreciate on the other hand that the aforesaid alternating operation of the switches Q1 and Q2 with alternating passage between the condition of conduction and the condition of non-conduction (ON/OFF) here achieved using transistors Q1 and Q2 of opposite polarities may be achieved with equivalent means (for example, by resorting to logic inverters).

Likewise, persons skilled in the sector will on the other hand appreciate that what is exemplified in Figure 4 constitutes only a possible advantageous implementation of a spike generator capable of generating positive spikes at the low-to-high and high- to-low transitions, i.e., at the rising and falling edges of the data signal IS. Other possible implementations fall within the scope of the person skilled in the sector.

The spikes exemplified in the diagram C of Figure 5 are transferred through the transformer 16 from the primary winding 161 to the secondary winding 162.

Coupled to the above secondary winding 162 is a reconstruction circuit 14 based upon a squarer circuit comprising a rectifier network comprising at least one diode (for example, two cascaded diodes 141 with the cathodes facing one end the secondary winding 162 of the transformer 16 and the anodes facing a squarer node N3 and a resistor R7 set in position intermediate between the squarer node N3 and the other end of the secondary winding 162 of the transformer 16 (which is here assumed as being referenced to the ground GNDR of the receiver circuitry 14).

Also, the receiver circuitry 14 comprises two electronic switches Q3, Q4, which may be implemented by resorting to bipolar transistors with complementary polarities (for example, p-n-p for the transistor Q3 and n-p-n for the transistor Q4).

The switch Q4 is set with the current-flow path that passes though it (from the emitter to the collector, in the case of the bipolar transistor here considered by way of example) in a current-flow line between a supply node (designated by SR) of the receiver circuitry 14 and the ground of the receiver circuitry GNDR.

The first electronic switch (transistor Q4) is set with its control node (base in the case of the bipolar transistor here considered by way of example) coupled to the squarer node N3.

The second electronic switch (transistor Q3) is set with the current-flow path that passes through it (from the emitter the collector, in the case of the bipolar transistor here considered by way of example) in a current-flow line between the supply node SR of the receiver circuitry 14 and the squarer node N3.

The transistor Q3 has its control node (base, in the case of the bipolar transistor here considered by way of example) coupled to the current-flow line between the supply node SR (of the receiver circuitry 14) and ground GNDR (once again of the receiver circuitry).

The output node OS that is to produce the output data signal is coupled to the aforesaid current-flow line between the supply node SR and ground GNDR with the switch or transistor Q3 that is located in an intermediate position between the output node OS and the other end of the secondary winding 162 of the transformer 16.

In the example presented in Figure 4, the rectifier network 141 comprises two diodes D1 and D2 arranged between one end of the secondary winding 162 of the transformer 16 and the squarer node N3 with a further resistor R8 set in parallel to the diodes Dl, D2.

As exemplified in Figure 4, the transistor Q3 is set with its control node (base, in the case of the bipolar transistor here considered by way of example) coupled to the current-flow line between the supply node SR and ground GNDR at an intermediate node or tap-point N4 of a resistive voltage divider comprising two resistors R5 and R6, set between the supply node SR and the output node OS.

Once again, as illustrated in Figure 4, the transistor Q3 is coupled to the supply node SR via a bias resistor R4 set along the current-flow path (from the emitter to the collector, in the case of the bipolar transistor here considered by way of example) through the transistor Q3.

Also in this case, persons skilled in the art will appreciate that what is exemplified in Figure 4 constitutes only a possible advantageous implementation of circuit coupled to the secondary winding 162 of the transformer 16 capable of squaring the spikes transmitted through the transformer 16 so as to (re)construct at output a logic signal (designated by OS in Figure 4) that has transitions between the logic levels LL1 and LL2 at the aforesaid spikes.

Other possible implementations fall within the reach of the person skilled in the sector.

It will be appreciated that the solution described herein envisages use of a transformer 16 with a (very) low impedance, with a few turns and with reduced coupling so that it can have small dimensions with a high level of isolation, at the same time with the possibility of using very sharp pulses.

For instance, the inductance LI and the capacitance C may be chosen so as to give rise to a time constant such that the resonance frequency 1/(2n -sqrt(LI-C)) may be greater, by approximately ten times, than the switching frequency, with the impedance ratio L1/R9 higher than R9-C].

L1/L2 is a transformer that can be obtained in such a way that by measuring L2 with LI shorted, the value of LI is reduced less than 5%.

Without prejudice to the underlying principles, the details of construction and the embodiments may vary, even significantly, with respect to what has been illustrated herein purely by way of non-limiting example, without thereby departing from the extent of protection, as this is determined by the annexed claims. LIST OF REFERENCE SIGNS galvanic-barrier primary side PS galvanic-barrier secondary side ss galvanic-barrier transformer TGB device 10 transmitter circuitry 12 receiver circuitry 14 data-signal-transfer transformer 16 primary winding 161 secondary winding 162 primary/secondary inductances LI, L2 spike generator 121, 122 driver circuit 123 input data signal 15 logic level LL1, LL2 signal-reconstruction circuit 141, Q3, Q4 spacing between windings SW capacitor 122 coupling node N1 charge-transfer network R3, R9, R10 first electronic switch Q1 second electronic switch Q2 transmitter supply node ST transmitter ground GNDT coupling resistors Rl, R2 driver node N2 squarer circuit 141 diodes Dl, D2 resistor R7 squarer node N3 first respective electronic switch Q4 second respective electronic switch Q3 receiver supply node SR receiver ground GNDR intermediate node N4 receiver output node N5 further resistor R8 bias resistor R4