Field of the invention The present invention relates to broad band telecommunication systems and, more in particular, to a communication between a central unit and a plurality of peripheral units through a high speed synchronous bus.

The invention relates also to a suitable system for the implementation of said method.

The last years recorded an acceleration in the demand of high transmission speed by the users having access to the public telecommunication network. This was true up to now mainly for large business users having branches spread over the territory, and the suppliers of telecommunication services answered by furnishing dedicated or packet switching lines (such as, for instance, X.25, Frame Relay or SMDS). More recently, the exponential growth of internet, the increased interest for the access to multimedia services through the telecommunication network, and the expected increase of telework (telecommuting), highlighted the need to enable also the small business users and even residential users to have access to the public telecommunication network with transmission speeds higher than the present ones.

Among the emerging communication techniques, the ATM technique, acronym for Asynchronous Transfer Mode, deserves a particular interest due to its flexibility and effectiveness in supplying even very high bandwidths.

An evolution of the access network is foreseen for the next years both for the higher transmission speed used on said network and for the typology of the services that shall be offered through the same. Therefore, it shall be necessary to offer an access to the public telecommunication network at high speed, reliable, low-cost and suitable to receive different type of traffic coming from a plurality of different sources (or users), with traffic characteristics and service features even very different among them, in particular, but not only, for the requested transmission speed.

Therefore, in the last years a plurality of access networks to the public telecommunication network have been developed. One of these networks is described in the Italian patent application no. Ml 96A 001064, under the name of the same applicant, where the above mentioned access network consists of a broad band, passive optical network or PON (Passive Optical Network) interconnecting a line

termination (Optical Line Termination or, shortly OLT), generally located close to a switching exchange, to a plurality of network units (Optical Network Unit or ONU in short), typically located close to the users.

The passive optical network forming the so-called network infrastructure, typically has a tree structure, that is point-multipoint, where the root is connected to the OLT and the terminal branches to each ONU, and consists of sections of optical fibre interconnected by passive optical components called power splitter/combiners, enabling to divide on the outputs or re-combine on a single output the signals reaching their inputs.

The system of the present invention, hereinafter defined ATM BUS has its preferred application field in the above mentioned access network, to collect the communication traffic, preferably ATM, coming from multiple input interfaces and to send communication traffic, preferably ATM, towards the same, particularly when different transmission speeds (bit rates) are present. In particular, one of these preferred applications is inside the above mentioned Optical Network Units or ONU to convey the data coming from a plurality of peripheral units to the PON, through a BUS Master, unit, as better described below.

Other possible applications are for instance inside service or access multiplexers based on ATM technique.

Background art WO 95/08887 discloses a source traffic control and asynchronous data transmission system including a master of the bus and a plurality of bus users coupled to a bi- directional data bus, said system, having a particular application in arranging the transfer of ATM cells in broad band ISDN systems.

The system employs a frame format of fifteen or sixteen cycles of system clock, which include a field for the request to bus access from the users and an access-grant field.

The arbitration algorithm for the access to the bus is implemented in the bus master unit and can be unknown to the bus users.

This system appears particularly useful to switch the traffic among the different units of the bus, irrespective of the fact that they are master or bus users. However, the system appears too complex for applications requiring to collect the traffic from a plurality of peripheral units (bus users) towards a single central unit (bus master) and to distribute the traffic from said single unit to one or more (possibly all) peripheral units.

In fact, in this case the presence of a bi-directional bus is not requested since the

packets (cells) of data are not switched between the peripheral units.

Moreover, this patent application does not suggest in any way the solutions to reduce the system global costs and/or optimize the tables relevant to each active connection and consequently the control of the cells can be made only analyzing the information of Virtual Path Identifier or VPI and of Virtual Channel Identifier or VCI.

ATM Forum/95-0114R1 - Utopia Level 2 Specification, Version 0.8 - April 1995, discloses an interface between the physical layer and the ATM layer, called also UTOPIA M-PHY for the connection of a plurality of physical layer devices to a single ATM layer device. This interface is of particular interest for the flow control functions and relevant separation of the operation speed of the ATM layer versus those of the physical layer devices, enabling to have physical layer devices operating at different speed among them and different from the operation speed of the ATM layer device.

Said interface implies, from physical layer to ATM layer, a clock signal having direction opposite to the data transfer one (counter-directional) and, as it is specified, it appears it cannot be directly employed on a system where the peripheral interfaces are distributed on a plurality of peripheral boards connected to a backplane of significant size, said backplane connecting the peripheral boards with the single central interface, placed on a central board, mainly when the transmission between the central board and the peripheral boards occurs at high speed (e.g., up to 622 Bits).

Also, not even the above mentioned ATM Forum suggests solutions to optimize the tables relevant to each active connection and consequently the cell control can be made only analyzing the Virtual Path Identifier or VPI information and the Virtual Channel Identifier or VCI information.

Obiects of the Invention The main object of the present invention is to overcome the disadvantages and limits of the communication methods of the known type and in particular to identify a communication method enabling to reduce the cost of the system and enabling the peripheral units PU to control the cells without processing the VPI/VCI information.

Disclosure of the Invention The previous problems are overcome and an advance is made in the technique through the method and system of the present invention.

Is therefore object of the present invention a multiple access communication method implemented in compliance to what disclosed in the main claim.

The present invention relates also to a multiple access system implemented according to what disclosed in claim 11.

The features of the present invention which are believed to be novel are set forth with particularity in the appended claims.

Advantaaes of the invention Thanks to the use of the Bundle Flow Identifier or BFI, described in the characterizing part of the main claim, it is possible to control the cells without processing the VPlNCl information.

Thanks always to the presence of said bundle flow identifier it is possible to perform the greatest part of the processing of data packets in the central unit, maintaining at peripheral unit level only a very limited processing capacity with consequent important cost reduction.

Brief description of the drawings The invention, together with further objects and advantages thereof, may be understood with reference to the following description, taken in conjuction with the accompanying drawings, and in which: Fig. 1 shows a functional block diagram of the ATM BUS according to the present invention: Fig. 2 shows the format of the well-known ATM cell; Figures 3a to 3d show the format of the data packet (cell) used by the ATM BUS; Fig. 4 shows the block diagram of a BMU embodiment; and Fig. 5 shows the block diagram of an embodiment of the PU.

Detailed description of a preferred embodiment The system of the present invention is a high speed synchronous bus (ATM BUS) (up to 622 Mbit/s),implementing a bi-directional interface based on fixed length data packets, preferably equal or similar to ATM cells, transmitted by a central part (10) and a plurality of peripheral parts (20-20). It is based on two kinds of units, that is the Bus Master Unit (BMU = Bus Master Unit) and the Peripheral units (PU = Peripheral Unit), connected to the BMU through a shared connection means (bus). The BMU plays its role in the central part (master), while the PUs are associated to the peripheral parts (slave) and in particular they are placed on a peripheral board (PB Peripheral Board) connected to the bus. Of course, more than one single PU can be placed, if the board feasibility limits allow it.

The architecture of the ATM BUS (Fig. 1) consists of three main functional blocks: the Bus Master Unit (BMU = Bus Master Unit) 10, the Peripheral units (PU = Peripheral Unit) 20-20, and the 60,70 connection means, respectively. The BMU 10 supplies an interface with physical layer device (PHY Layer) 30, this interface preferably being an

8-bit or 16-bit UTOPIA interface. Each PU 20 has an interface with physical layer devices (PHY) 40 or ATM adaptation layer ATM (AAL = ATM Adaptation Layer) 40, said interface preferably being an 8-bit or 16-bit UTOPIA Multi-Physical (M-PHY). The PUs transmit ATM cells to the BMU (upstream) and receive ATM cells from the same (downstream) through a high speed, synchronous, failure-enduring, connection means (bus). In a preferred embodiment the bus is 16 bits of data and operated at 622 Mbit/s.

In a preferred embodiment, the connection means 60,70 consists of a UBUS (Upstream BUS) 60, transporting to the BMU the data supplied at output by the PUs, and of a DBUS (Downstream BUS) 70 transporting the data supplied at output by the BMU to the PUs.

The detailed description of a preferred embodiment of the PMD layer, that is the merely physical layer through which the signals are exchanged between the BMU and the PUs is made known in the Italian Patent Application pending under the title 'System for the transmission of data between a central unit and a plurality of peripheral units through a high speed synchronous bus under the name of the same applicant, the disclosure of which is hereby expressly incorporated herein by reference.

Each PU processes a plurality (e.g. 8) of peripheral ATM interfaces with PHY/AAL devices through the UTOPIA M-PHY. Each peripheral interface is associated to a single address of the UTOPIA M-PHY dedicated to the specific peripheral interface.

Furthermore, the PU can process flows of broadcast channels (= broadcast VC) in the direction from BMU to PU (downstream), generating and addressing copies of the cells to the corresponding PHY/AAL devices.

The BMU performs all the functions of ATM layer, as the translation of the header (= header translation) and the control of usage parameters (UPC = Usage Parameters Control), and acts as arbitrator for the accesses to the bus from PU to BMU (upstream) of the PUs through a specific interrogation protocol that shall be described below.

The ATM BUS consists of two sections, separate from the logic point of view, one controlling the upstream flow and the other one the downstream flow. Both the sections have a gross throughput, for instance of (up to) 622 Mbit/s. The size of the ATM BUS cell is 54 bytes. For the preferred embodiment (16-bit data bus), in the downstream direction, 27 clock cycles are required to transport one 54-byte cell from the BMU to the PUs (on DBUS). In the upstream direction, 2 additional words

(meaningless) are foreseen to supply an interruption in the transmission among cells, therefore 29 clock cycles are required to transport one 54-byte cell from a PU to the BMU (on the UBUS). This interruption is necessary to avoid that two PUs that transmit in succession, superimpose their transmissions on the bus due to the uncertainty in the step in which each PU engages the bus, thus damaging the cells that would be received wrong for the last bytes of the preceding cell and the first bytes of the next cell.

The format of the cell transported on the connection means 60,70 (Fig. 3a-d) shall now be described. In this description the term cell is used to intend a predeterminea group of bytes logically organized and transmitted as single entity, because the present invention is particularly oriented to ATM applications, which use the term cell to indicate a packet of 53 bytes (Fig.) (The device of the present invention includes UTOPIA interfaces and the specification of the UTOPIA interface implies that the 53- byte ATM cell can be actually transmitted as 53 byte cell in case of 8-bit UTOPIA interface, while it is transmitted as 54 bytes in case of 16-byte UTOPIA interface).

Other terms which can be used and intended as included in the present invention, are frame or packet, so the following description could be considered valid also for the transmission of frames and/or packets.

The cell format on the connection means 60,70 is defined to enable a simple and effective transport of ATM cells from the BMU to the PUs and vice versa, considering the requirements of the cell format for the UTOPIA interface of Level 1. More in detail, the ATM header field (ATM header) and the UDF field (User Defined Field) defined by the UTOPIA specification) can be transported in a transparent way through the bus in both directions, while an additional field (corresponding to the UDF2 field in the specific UTOPIA based on 16 bits of data) is configured to transport important proprietary information for the PUs and/or the BMU.

For the cell format at UNI (= User Network Interface), it shall be given the ability to transport in a transparent way the GFC field (= Generic Flow Control). In this case, in the upstream direction, the GFC field transparently crosses the PUs and the UBUS, and reaches the BMU, where the GFC can be terminated; in the downstream direction, the GFC in the cell coming from the BMU reaches the peripheral interface through the DBUS and the PU.

Where this function is not requested, in the upstream direction the GFC can be terminated at peripheral interface level (that is at the PU one), and no treatment of the GFC shall be made at BMU level, both for the upstream flow and the downstream

one. If no transparent transport of the GFC is requested by the user at ONU level, in the position of the cell corresponding to the GFC field, an identification of the multiplexing group called Multiplex identifier (MID = Multiplex IDentifier) can be transported, which enables each physical layer interface (PHY) to multiplex/demultiplex up to 8 ATM user flows per remote ATM interface. In this case, a Remote Termination Unit (RTU = Remote Termination Unit) (not shown), for instance placed at share level, will use the MID to multiplex/demultiplex the ATM flows of the relevant UNI interfaces.

The VPI, VCI, PTI and CLP fields of the standard ATM cell (Fig. 2) are processed by the ATM layer device, placed on the side of the BMU (or even integrated in the same).

All the VCI, PTI and CLP fields, transparently cross the PUs, while the VPI field on the downstream flow can be modified as indicated below.

The UDF field specified in the 8-bits UTOPIA protocol, can be transparently transported through the ATM BUS between the UTOPIA interface of the PU and the UTOPIA interface of the BMU, and vice versa.

According to the invention, on the ATM BUS, in both the directions, ATM cells are accompanied by a Bundle Flow Identifier (BFI = Bundle Flow Identifier), grouping the whole ATM point-to-point flow relevant to a single peripheral ATM address or source interface. The PUs address the cells coming from their peripheral interfaces and from the UBUS according to the BFI and the corresponding address of the UTOPIA M- PHY. Advantageously, using the BFI, the PUs can control the cells without having to process the VPI/VCI information and therefore optimising the dimensions of the tables relevant to each active connection.

According to the cell format on the proposed connection means (see Figures 3a-d), the BFI has 6 bits and identifies up to 64 peripheral interfaces. To overcome this limit, the invention foresees to use the four more significant bits of the first word (16 bit) of the cell as an extension of the BFI (BFI DCT), instead of MID, and also in this case the GFC cannot transparently cross the ATM BUS as said before. Using the BFI and the BFI UCT 10 bits are available, therefore up to 512 interfaces can be addressed on the RTUs.

In the case of broadcast/multicast (point-multipoint) virtual channels (VC = Virtual Channel) the BFI is not valid and all the broadcast VC at ATM BUS layer are identified by a VPI value called VPI Broadcast (VPlb). The VPlb can be configured at any desired value. Each broadcast VC inside the VPI broadcast is identified by a VCI value. The PUs recognize the VPlb and use the VCI to address a local research table

containing the broadcastjmulticast routing information. The PUs translate the VPlb in a VPlb' value, which is a configurable VPI value, valid on the peripheral interface side, and generate copies of the cells without additional processing of the header. In the broadcast/multicast operation the MID is not valid and the RTU is requested to perform additional broadcast/multicast functions.

In the case of point-to-point flows the VPI field transparently crossed the PUs, while in the case of broadcast/multicast flows, the VPI identifying the broadcast flows(VPlb) can be translated by the peripheral interface in a specified value (VPlb1).

Going back to Figures 3a-d, provisions are also made for a HouSeKeeping field(HSK) to transport cell processing information (routing, copy, extraction) for the diagnostics of the bus and for operation and maintenance purposes. This field determines, both in the upstream and downstream directions the type of treatment the cell will undergo. In the preferred embodiment the following coding for this field are given: - 00: empty cell (that is, to be rejected at receipt since it does not transport significant data); - 01: valid cell to send; - 10: valid cell to extract toward microprocessor; - 11: valid cell to be sent and copied for extraction towards the microprocessor.

We shall now describe the operation of the BMU on the downstream flow, making reference to Fig. 4.

The operation of the BMU on the downstream flow is now described making reference to Fig.4. The BMU 10 receives ATM cells from the physical layer device (30) through the UTOPIA interface at maximum speed (e.g. 622 Bits). It performs a light buffer storage to conciliate the number of clock pulses requested to receive the cell of the incoming flow (27 clock pulses) to the number of clock pulses requested for the transmission of the cell on DBUS (27 clock pulses plus 2 clock stop pulses on the bus). In the Downstream Header Translation block 102, the BMU obtains the ATM switching parameters addressing a local research table with the specific fields of the ATM header, then it translates the ATM header of the entering cell, concerning the VPI or VPI/VCI fields, in the ATM header configured on the PU side. The Downstream Header Translation block 102 then completes the header translation adding the configured BFI value (relevant to the destination peripheral interface) and adding the configured HSK value. The UDF field of the 8-bit UTOPIA protocol is copied in a transparent way in the corresponding position of the cell. Through the interface port

on bus 103, the BMU transmits the cell on the DBUS 70 at the maximum bit rate (e.g.

622 Mbit/s).

The BMU gives the following cell extraction and insertion capabilities. The cells can be extracted from the downstream flow on the basis of the value of their ATM header for OAM functions and extraction of the service channels. The insertion capacity of downstream cells is provided to diagnostic purposes and for the insertion of service channels.

Making reference to Fig.5, the operation of the PU on the downstream flow is as follows. La PU receives the cells from the downstream bus DBUS 70 through the interface block to Bus 201 and builds the 53-byte cell header (Fig. 2). To do this, in the Header Translation block 202, it identifies first if the cell belongs to a point-to-point or point-multipoint connection. In the case of point-to point flow, the block 202 addresses the cell to the relevant queue of the Buffer memory 203 directly on the basis of the BFI value (which identifies a specific peripheral interface). In the case of point-multipoint flow, identified for instance by a particular VPI value (that is, VPlb), the block 202 uses the VCI value to address a local research table containing routing information, that is to which interfaces the copies of a cell belonging to the considered broadcast flow have to be sent; on the basis of this information, the PU routes the copies of the cell to the relevant queues of the involved peripheral interfaces, in the Buffer memory 203, without making (in this case) a translation of the header, except for the translation of VPlb into VPlb'. Since the transmission speed of each single peripheral interface is lower (even significantly) than the transmission speed on the DBUS 70, a speed adjustment is requested in the PU which is performed through the Buffer memory 203. The Buffer memory 203 is implemented as a shared memory with separate queues for peripheral interface. On the downstream flow, the Header Translation block 202 constructs the 53-byte cell header as indicated below. If the four more significant bits of the first word (16 bit) of the cell are occupied by the GFC (Fig.

3a) or by the MID (Fig. 3b), said bits are written in the corresponding position of the output header. On the contrary, if they are occupied by the BFI UCT (Figures 3c and 3d), this information is not written in the output header, but it is locally managed to associate the cell to the relevant output queue. The block 202 knows which field is contained in the above mentioned 4 bits on the basis of the value contained in a configuration record, similarly to what applies to the BMU. Therefore, the PU copies the VPI, VCI, PTI, CLP and UDF fields (UDF1 of the 8-bit UTOPIA protocol) in the corresponding positions of the output cell header. Once the 53 byte cell is built, it is

sent, through the Transmission Port 205 towards the PHY/AAL physical layer devices through the UTOPIA M-PHY interface. The flows are demultiplexed towards the relevant device according to the requirements of the UTOPIA M-PHY specification, the destination peripheral interface being associated to the corresponding UTOPIA M- PHY address. On the downstream flow, the PU gives also the possibility of cell extraction of the basis of the value of the HSK field, for instance, to diagnostic purposes.

The operation of PU on the upstream flow is now described, making reference to Fig.5. The PU receives the cells from the PHY and/or AAL devices(40) according to the UTOPIA M-PHY protocol through the Receipt Port 206, performing the multiplexing of the different physical layer flows in a unique ATM upstream flow, and constructs the header of the 54 byte cell to be transmitted on the UBUS (see Figures 3a-d) in the insertion block of BFI 207. If the PU is configured to enable the GFC to pass in a transparent way, the block 207 constructs the new header of the cell writing the value of the GFC field of the ATM input cell in the more significant bits of the first word (Fig. 3a). If, on the contrary, the PU is configured to insert the MID (Fig. 3b), it will construct the header accordingly. Finally, the PU can be configured to insert the BFi DCT value (Figures 3c and 3d) corresponding to the UTOPIA M-PHY address of the source peripheral interface (and which is associated to the BFI value described below). The PU knows the configuration type since it is written in a record, this configuration being valid at interface level, that is for all the connections active on that PU. The header construction goes on writing in the new header the same values of the VPI, VCI, PTI, CLP fields of the entering ATM cell and the UDF field of the 8-bit UTOPIA protocol, therefore said fields are allowed to pass in a transparent way. The block 207 adds then the HSK value and the BF1 value corresponding to the UTOPIA M-PHY address of the source peripheral interface. The header so obtained is applied to the payload of the corresponding cell. So, in the Buffer Storage Block 208, the PU makes a buffer storage to accept from the UTOPIA interface a burst of n cells. In the preferred embodiment, n is equal to 32. In this way, a single PU can process up to 32 RTU, provided that the PU can transmit on the UBUS 60 at a speed equal to the sum of the physical layer/AAL transmission speeds (local or remote) connected to the same. This implies that the PU will receive, in block 209, a grant to transmit upstream according to the transmission speed so requests, preferably in compliance with what said in the Italian Patent Application under the name of the same Applicant, mentioned above.

The PU gives also the possibility to insert cells in the upstream direction to diagnostic purposes, these being sent to the PU by the local microprocessor. The access to the upstream bus UBUS 60 is managed by the Access Control block to Bus 209. Once the PU has one cell at least available for transmission, it sends a transmission request, according to what defined below, and transmits a single cell on the UBUS 60, through the Interface Block to Bus 210, only after having received the relevant grant.

Therefore the PU engages the UBUS 60 for the time of transmission of one single cell coinciding with each grant received.

Going back to Fig.4, the BMU operation on the upstream flow is now described.

Through the interface block to Bus 104, the BMU drives the timing of the upstream bus UBUS 60 generating upstream frame synchronization pulse (Slot Strobe) defining the transmission time slots for the PUs. The Access Control block to Bus 107 arbitrates the access to the upstream bus by the PUs. During each bus cycle, the BMU expects to receive the availability information of (at least) one cell (CLAV = CelL AVailable) by all the PUs connected and sends a grant to transmit (Transmit Grant) to a single PU. The PU is selected on the basis of a specific algorithm implemented in the Bus Access Control block 107. Such an algorithm, for instance, can be the one described in the Italian Patent Application No. Ml96A 002678 under the title "Method and system for arbitrating the access to a transmission means shared by more sources" in the name of the same Applicant.

In the Usage Parameters Control Block 105, a control of usage parameter functions is made on the cells (UPC/NPC = Usage/Network Parameter Control) to decide whether send or reject the same because not complying with what defined. Once the cells result complying with usage parameters, the BMU obtains all the parameters for the ATM addressing in the Upstream Header translation block 106, a local research table; the address is obtained from the sole BFI (relevant to the queue of one of the source peripheral interfaces) or from the BFI and ATM layer identifiers ATM (VPI, or VPI and VCI). The block 106 translates the ATM headers of cells entering the ATM output configured header. The UDF field (UDF1 of the 8-bit UTOPIA protocol) is copied in a transparent way.

Therefore cells are stored in a buffer memory 108 to adjust the speed the that of the physical layer interface, which can have a lower speed. Finally, the BMU transmits the ATM cells to the physical layer device through output port 109 implementing a UTOPIA interface according to the requested transmission speed. On the upstream flow, the BMU performs also the following functions. It gives extraction capacity of

upstream cells on the basis of the value of the HSK field to ATM BUS diagnostic purposes; extraction capacity of upstream cells on the basis of the value of the BFI field and ATM header for OAM functions and extraction of service channels; it gives insertion capacity of upstream cells for OAM and service channels functions.

Therefore, while a particular embodiment of the present invention has been shown and described, it should be understood that the present invention is not limited thereto since other embodiments may be made by those skilled in the art without departing from the scope thereof. It is thus contemplated that the present invention encompasses any and all such embodiments covered by the following claims.