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Title:
COMPARATOR CIRCUIT, MISMATCH CORRECTION METHOD, AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2023/178819
Kind Code:
A1
Abstract:
The present disclosure relates to the field of semiconductor circuit design, and in particular relates to a comparator circuit, a mismatch correction method, and a memory. The comparator circuit comprises: a first transistor, one terminal being coupled with a first node, another terminal being coupled with a first control node, and the gate being used for receiving a first control signal; a second transistor, one terminal being coupled with the first node, another terminal being coupled with a second control node, and the gate being used for receiving a second control signal; a load unit, one end being coupled with the second node and the other end being coupled with the first control node and the second control node; a first adjustment circuit is used for, according to a first adjustment signal, adjusting the node potential of the first control node after the first transistor is connected on the basis of the first control signal; and a second adjustment circuit is used for, according to a second adjustment signal, adjusting the node potential of the second control node after the second transistor is connected on the basis of the second control signal, thereby eliminating mismatch between two input transistors of a differential structure and further increasing the performance of a memory.

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Inventors:
TIAN KAI (CN)
ZHU LING (CN)
Application Number:
PCT/CN2022/093571
Publication Date:
September 28, 2023
Filing Date:
May 18, 2022
Export Citation:
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Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H03K5/24
Foreign References:
US6388521B12002-05-14
US5045806A1991-09-03
CN106788352A2017-05-31
US20110037507A12011-02-17
CN202210294447A2022-03-23
Other References:
See also references of EP 4280461A4
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
Download PDF:
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