BRATT, Adrian Harvey (18 St. Leonard, Woore, Cheshire CW3 9ST, GB)
GOLDFINCH, Jonathan Lasselet (89 Buxton Road, Whaley Bridge, Derbyshire SK23 7HC, GB)
HARROLD, Stephen John (159 Urmston Lane, StretfordManchester, Greater Manchester M32 9EH, GB)
BRATT, Adrian Harvey (18 St. Leonard, Woore, Cheshire CW3 9ST, GB)
GOLDFINCH, Jonathan Lasselet (89 Buxton Road, Whaley Bridge, Derbyshire SK23 7HC, GB)
| CLAIMS 1. A method of compensating for stress induced variations in the resistance of a semiconductor resistor element, the method including the steps of: providing a semiconductor device which includes the semiconductor resistor element and a reference arrangement, in which the reference arrangement includes a metallic reference resistor and a semiconductor reference resistor; generating a compensation parameter by measuring stress induced changes in the resistances of the metallic reference resistor and the semiconductor reference resistor, or at least one quantity functionally related thereto; and using the compensation parameter to compensate for stress induced variations in the resistance of the semiconductor resistor element. 2. A method according to Claim 1 in which the compensation parameter is generated by measuring a first ratio of the resistances of the metallic reference resistor and the semiconductor reference resistor. 3. A method according to Claim 2 in which the compensation parameter is generated by comparing the first ratio to a second, reference, ratio of the resistances of the metallic reference resistor and the semiconductor reference resistor which is determined under reference conditions. 4. A method according to Claim 3 in which the compensation parameter is generated by obtaining a ratio of the first ratio to the second ratio, or a quantity functionally related thereto. 5. A method according to any previous Claim in which the step of generating a compensation parameter includes a temperature compensation step for compensating for temperature induced variations in the measured resistances of the metallic reference resistor and the semiconductor reference resistor. 6. A method according to Claim 5 in which the temperature compensation step is performed with reference to a database or a mathematical model of metallic resistor and semiconductor resistor resistances as a function of temperature. 7. A method according to any previous Claim which the step of generating the compensation parameter includes correcting for a ratio of the gauge factors of the metallic reference resistor and the semiconductor reference resistor. 8. A method according to Claim 4 in which the correction factor is derived from the relationship RRAS ^ 1 + ASS RR ~ 1 + %-ASM where RRAS is the first ratio, RR is the second ratio, Gs is the gauge factor of the semiconductor material in the semiconductor reference resistor, GM is the gauge factor of the metallic material in the metallic reference resistor, ASS is the change in strain experienced by the semiconductor reference resistor, and ASM is the change in strain experienced by the metallic reference resistor, and wherein, optionally, one or more of the terms GM/Gs and ASM/ASS are ignored. 9. A method according to any previous Claim in which the semiconductor resistor element forms part of an RC oscillator, and the step of using the compensation parameter includes using the compensation parameter as an indication of the stress induced variation in the resistance of the semiconductor resistance element, and adjusting to RC oscillator to achieve a desired output frequency taking account of said indication of the stress induced variation. 10. An apparatus for compensating for stress induced variations in the resistance of a semiconductor resistor element, the apparatus including: a semiconductor device which includes the semiconductor resistor element and a reference arrangement in which the reference arrangement includes a metallic reference resistor and a semiconductor reference resistor; a compensation parameter generator including a measurement arrangement for measuring stress induced changes in the resistances of the metallic reference resistor and the semiconductor reference resistor, or at least one quantity functionally related thereto, in which the compensation parameter generator generates a compensation parameter from the stress induced changes measured by the measurement arrangement; and a compensator which uses the compensation parameter to compensate for stress induced variations in the resistance of the semiconductor resistor element. 11. An apparatus according to Claim 10 in which the semiconductor device is an integrated circuit. 12. An apparatus according to Claim 11 in which the metallic reference resistor is formed by connecting a plurality of vias on the integrated circuit. 13. An apparatus according to Claim 12 in which the vias are connected in series. 14. An apparatus according to any one of Claims 10 to 13 in which the metallic reference resistor is formed from tungsten or an alloy of tungsten. 15. An apparatus according to any one of Claims 10 to 14 in which the semiconductor reference resistor is formed from polysilicon or doped silicon. 16. An apparatus according to any one of Claims 10 to 15 in which the semiconducting device includes an RC oscillator, and the semiconductor resistor element forms part of said RC oscillator. 17. An apparatus according to Claim 16 in which the compensator uses the compensation parameter as an indication of the stress induced variation in the resistance of the semiconductor resistor element, and adjusts the RC oscillator to achieve a desired output frequency taking account of said stress induced variation. 18. An apparatus according to any one of Claims 10 to 17 in which the compensation parameter generator includes a temperature compensator for compensating for temperature induced variations in the measured resistances of the metallic reference sensor and the semiconductor reference resistor. 19. An apparatus according to Claim 18 in which the temperature compensator includes a database of metallic reference resistor and semiconductor reference resistor resistances as a function of temperature or is configured to utilise a mathematical model of metallic reference resistor and semiconductor reference resistor resistances as a function of temperature, and further includes a temperature measurement device for measuring a temperature and a comparator for comparing resistances measured by the measurement arrangement with the database or mathematical model using the temperature measured by the temperature measurement device as a reference datum for the database or mathematical model. |
This invention relates to an apparatus for compensating for stress induced variations in the resistance of a semiconductor resistor element, and to associated methods of compensating for stress induced variations in the resistance of said semiconductor resistor element, with particular, but by no means exclusive, reference to RC oscillators.
Semiconductor devices such as silicon chips can be placed under stress during use or as a consequence of the manufacturing process. For example, packaging of a silicon chip can create stress therein in a manner which is hard to predict in terms of both its magnitude and direction. The stress is determined by the nature of the package, lead frames, curing materials, curing temperatures, and many other factors. This stress produces strain of the silicon die, and changes in the stress can cause resistors to change value in comparison to their values before the change in stress was applied. Changes in the stress and associated strain can also be caused by other means, such as temperature changes, mechanical means such as mounting the silicon chip on a printed circuit board, or by slow changes in the nature of the packaging materials.
A particular example of a semiconductor device which may be realised on an integrated circuit is an electronic oscillator such as an RC oscillator. It will be apparent from the foregoing discussion that a packaged RC oscillator will shift in frequency when the silicon chip is stressed, irrespective of whether it was precisely calibrated prior to stressing of the silicon chip. It is known to precisely calibrate an RC oscillator in order to eliminate naturally occurring wafer to wafer process variations. Typically, this calibration process may be performed during or shortly after the manufacturing process, for example at wafer probe. It is known to perform a temperature sweep at this time, in order to calibrate the response of the device with respect to temperature so that subsequent temperature dependent variations can be removed. However, these known calibration procedures do not account for subsequent changes in the RC product caused by changes in the stress induced by the packaging of the silicon chip.
Package-induced stress is not easy to fully predict, and the present invention is predicated upon the basis that compensation of package stress requires a system for monitoring the package stress or its effects prior to making an appropriate compensation. It is known to use strain gauges for mechanical measurement of stress induced strains, but typically these devices rely on an unstrained, reference component which is compared to one or more components which are strained. Alternatively, a known reference quantity such as voltage or current may be used to measure the strain gauge properties. This represents a major obstacle to implementation on a silicon die, because all of the components on the die are stressed to some degree, and there is no ideal reference component or quantity.
The present invention, in at least some of its embodiments, addresses the above described problems and needs. In particular, the present invention provides methods and apparatus for compensating for stress induced variations in an RC oscillator. However, the invention can be applied more generally to the compensation of stress induced variations in the resistance of semiconductor resistor elements which are used for other purposes. For example, the present invention can be used in connection with band gap reference systems, piezo- resistive devices, sensors, or other semiconductor devices requiring a fine control of resistance.
According to a first aspect of the invention there is provided a method of compensating for stress induced variations in the resistance of a semiconductor resistor element, the method including the steps of:
providing a semiconductor device which includes the semiconductor resistor element and a reference arrangement, in which the reference arrangement includes a metallic reference resistor and a semiconductor reference resistor;
generating a compensation parameter by measuring the stress induced changes in the resistances of the metallic reference resistor and the semiconductor reference resistor, or at least one quantity functionally related thereto; and
using the compensation parameters to compensate for stress induced variations in the resistance of the semiconductor resistor element.
The invention exploits the different sensitivities to stress exhibited by metallic and semiconductor materials to determine and quantify resistance changes which are induced by stress.
Typically, the semiconductor resistor element and the semiconductor reference resistor are formed from the same semiconductor material. Advantageously, at least the semiconductor reference resistor and, optionally, the metallic reference resistor are located close to the location of the semiconductor resistor element.
Advantageously, the compensation parameter is generated by measuring a first ratio of the resistances of the metallic reference resistor and the semiconductor reference resistor. Conveniently, the compensation parameter is generated by comparing the first ratio to a second, reference ratio of the resistances of the metallic reference resistor and the semiconductor reference resistor which is determined under reference conditions. Generally, the second, reference ratio is determined at or shortly after the time of manufacture, such as at the time of wafer probe. This may be performed as part of a larger calibration process which may include a temperature dependence calibration. In preferred embodiments, the compensation parameter is generated by obtaining a ratio of the first ratio to the second ratio, or a quantity functionally related thereto.
Advantageously, the step of generating a compensation parameter includes a temperature compensation step for compensating for temperature induced variations in the measured resistances of the metallic reference resistor and the semiconductor reference resistor. In this way, variations in the measured resistances which are due to changes in temperature can be accounted for. Any remaining variations in resistance can be ascribed to the presence of different stress than existed under the reference conditions. Preferably, the temperature compensation step is performed with reference to a database or a mathematical model of metallic resistor and semiconductor reference resistor resistances as a function of temperature. In one embodiment, a temperature calibration procedure is performed, and the temperature dependence of the ratio of the resistances of the metallic reference resistor and the semiconductor reference resistor (or at least one quantity functionally related thereto) is determined by curve-fitting. The step of generating the compensation parameter may include correcting for a ratio of the gauge factors of the metallic reference resistor and the semiconductor reference resistor.
The gauge factor (G) is defined by the relationship AR/R=G(AL/L) where AR is the change in resistance due to a change in the applied stress, R is the resistance prior to the change in stress, AL is the change in length due to the change in applied stress and L is the length prior to the change in stress, i.e, AUL represents an axial strain.
In preferred embodiments, the correction factor is derived from the relationship
RR AS ^ 1 + G S -AS S
RR 1 + ^ where RR AS is the first ratio, RR is the second ratio, G S is the gauge factor of the semiconductor material in the semiconductor reference resistor, G M is the gauge factor of the metallic material in the metallic reference resistor, AS S is the change in strain experienced by the semiconductor reference resistor, and AS M is the change in strain experienced by the metallic reference resistor,
Optionally, one or more of the terms G M /Gs and ASM ASS can be ignored.
However, more accurate resistance compensation may be obtained if one or both of these ratios are accounted for. In particular, the term GM/G s may be accounted for. The correction factor may derived from the relationship
This relationship being derivable from equation (1) by ignoring quadratic and higher expansion terms. However, the correction factor may be derived using other approaches which are described herein.
Advantageously, the metallic reference resistor and the semiconductor reference resistor are connected in series. This arrangement permits convenient measurement of the ratio of the resistances of these elements. However, other arrangements and associated measurement methodologies may be implemented.
Preferably, the semiconductor resistor element forms part of an RC oscillator, and the step of using the compensation parameter includes using the compensation parameter as an indication of the stress induced variation in the resistance of the semiconductor resistance element, and adjusting the RC oscillator to achieve a desired output frequency, taking account of said indication of the stress induced variation.
However, the compensation parameter may be used in any suitable manner to compensate for stress induced variations in the resistance of one or more semiconductor resistor elements used in many other applications.
According to a second aspect of the invention there is provided an apparatus for compensating for stress induced variations in the resistance of a semiconductor resistor element, the apparatus including:
a semiconductor device which includes the semiconductor resistor element and a reference arrangement, in which the reference arrangement includes a metallic reference resistor and a semiconductor reference resistor; a compensation parameter generator including a measurement arrangement for measuring stress induced changes in the resistance of the metallic reference resistor and the semiconductor reference resistor, or at least one quantity functionally related thereto, in which the compensation parameter generator generates a compensation parameter from the stress induced changes measured by the measurement arrangement; and
a compensator which uses the compensation parameter to compensate for stress induced variations in the resistance of the semiconductor resistor element.
Preferably, the semiconductor device is an integrated circuit. Conveniently, in an integrated circuit the metallic reference resistor may be formed by connecting a plurality of vias on the integrated circuit. The vias may be connected in series, although other arrangements might be utilised.
The metallic reference resistor may be formed from tungsten or an alloy of tungsten. Tungsten has the advantages of possessing a low gauge factor, and also a lower modulus of elasticity than many semiconductor materials such as polysilicon, so that the strain induced by stress is lower than such semiconductor materials, and therefore the second term inside the brackets of equation (1) is smaller. In particular convenient embodiments of the invention, the metallic reference resistor is formed from a plurality of connected tungsten vias on an integrated circuit.
The semiconductor reference resistor may be formed from any suitable semiconductor material, such as polysilicon or doped silicon. Typically, the semiconductor reference resistor and the semiconductor resistor element are formed from the same semiconductor material.
Preferably, the semiconductor device includes an RC oscillator, and a semiconductor resistor element forms part of said RC oscillator. In these embodiments, the compensator may use the compensation parameter as an indication of the stress induced variation in the resistance of the semiconductor resistor elements, and adjust the RC oscillator to achieve a desired output frequency taking account of said indication of the stress induced variation.
The compensation parameter generator may include a temperature compensator for compensating for temperature induced variations in the measured resistances of the metallic reference sensor and the semiconductor reference resistor. The temperature compensator may include a database of metallic reference resistor and semiconductor reference resistor resistances as a function of temperature, or be configured to utilise a mathematical model of metallic reference resistor and semiconductor reference resistor resistances as a function of temperature, and may further include a temperature measurement device for measuring a temperature and a comparator for comparing resistances measured by the measurement arrangement with the database or mathematical model using the temperature measured by the temperature measurement device as a reference datum for the database or mathematical model.
Whilst the invention has been described above, it extends to any inventive combination of the features set out above, or in the following description, drawings or claims. For example, elements of the first aspect of the invention may be incorporated into the second aspect of the invention, or vice versa.
Embodiments of apparatus and method in accordance with the invention will now be described with reference to the accompanying drawings, in which:-
Figure 1 is a schematic diagram of an integrated circuit of the invention;
Figure 2 shows a three dimensional element (a) without an applied axial stress and (b) with an applied axial stress;
Figure 3 shows a reference arrangement of the invention; and
Figure 4 is a cross sectional view of a portion of an integrated circuit of the invention, showing a via.
Figure 1 is a schematic diagram of an integrated circuit 10 of the invention comprising a programmable RC oscillator 12, a control arrangement 14 for the RC oscillator 12, a compensation parameter generator 16 and a temperature sensor 18. The compensator parameter generator 16 comprises a measurement arrangement 16a and a compensation parameter calculator 16b. The measurement arrangement 16a includes a metallic reference resistor and a semiconductor reference resistor (not shown in Figure 1). As is readily understood by the skilled reader, the programmable RC oscillator 12 comprises a plurality of capacitors and resistors which can be interconnected so as to provide an output signal of a desired frequency which is determined essentially by the RC product. The arrangement of the capacitors and the resistors in the RC oscillator is controlled by the control arrangement 12. The resistors in the programmable RC oscillator 12, and the metallic reference resistor and the semiconductor reference resistor in the measurement arrangement 16a are all located on the integrated circuit 10, and therefore are subjected to substantially identical stresses. Advantageously, at least the semiconductor reference resistor is physically located on the integrated circuit close to the location of the resistors in the RC oscillator 12. As explained in more detail below, the compensation parameter calculator 16b utilises measurements of the ratio of the metallic reference resistor and the semiconductor reference resistor in the measurement arrangement 16a to derive a compensation parameter which is indicative of changes in resistance which are induced by a stress that the integrated circuit is subjected to.
The present invention exploits the different sensitivities to stress exhibited by metallic and semiconductor materials. This can be understood and quantified in terms of the gauge factor of a material. The gauge factor arises from the geometric deformation of three dimensional solids when they are subjected to a stress. A change in the applied stress leads to a strain of AL/L which in turns leads to a change in the sectional area of a physical solid which is defined by Poisson's ratio v where,
v = axial strain / transverse strain
For small deformations the stretch of the material can be expressed volumetrically as,
AV / V = (1-2 v ) AL/L
The strain causes the geometries of resistor elements to change. A solid with a Poisson's ratio 0.5 will maintain a constant volume under varying stress conditions, but will show a change in shape. This is shown in Figure 2, wherein Figure 2a shows an element 20 in perspective and cross sectional view before a change in the axial stress, and Figure 2b shows the element 20 in perspective and cross sectional view after the change in axial stress leading to an axial strain. It can be seen that the axial strain causes the element to increase in length, but to decrease in cross sectional area. As an example, a metal resistor which is strained to be 1% longer also has a 1% smaller sectional area, and hence shows approximately a 2% resistance change for a 1 % strain. The gauge factor relates the fractional change in resistance to the fractional change in length, and is defined by the relationship G=(AR/R)/(AL/L) where AR is the change in resistance due to a change in the applied stress, R is the resistance prior to the change in stress, ΔΙ_ is the change in length due to the change in applied stress and L is the length prior to the change in stress, i.e, AL/L represents an axial strain. Most metals have a gauge factor close to 2, because these materials retain a fairly constant volume under strain but show no other significant resistance altering effects under relatively small stresses. In contrast, semiconductor materials such as polysilicon have a higher gauge factor. This is because, in addition to causing changes in length and cross sectional area, strain of these materials also causes changes in the number of minority carriers and carrier mobility within the semiconductor material. As an example, the gauge factor of polysilicon is approximately 20.
The invention exploits the different gauge factors of metals and semiconductor materials by comparing the behaviour of a semiconductor reference resistor with the behaviour of a metal reference resistor. Because the resistance of the metal resistor is less affected by strain in comparison to the semiconductor resistor, it is possible from a differential analysis of the resistances of the metallic reference resistor and the semiconductor reference resistor to obtain a variation in resistance which can be ascribed to the influence of strain. In an ideal system, one of the reference resistors would have a gauge factor of zero, and therefore would act as a strain insensitive reference. The present invention recognises that this ideal reference resistor does not exist, but also recognises that excellent compensation can be achieved using the differential resistor arrangement. In the instance in which a metal reference resistor having a gauge factor of about 2 and a polysilicon semiconductor reference resistor having a gauge factor of about 20 are used, it is readily possible to account for about 90% of the resistance changes caused by an applied stress. This can provide excellent resistance correction; for example, an uncompensated stress related resistance change of 500ppm can be readily reduced to 50ppm. However, as explained in more detail below, it is readily possible to improve upon this by further compensating for the known gauge factors of the reference resistors. In these embodiments, the primary error in the correction would be due to any errors in the gauge factors used for the additional compensation, and it is anticipated that this residual error will be significantly less than the error associated with embodiments in which no correction is made to account for the actual gauge factors of the reference resistors.
Figure 3 shows a possible arrangement of the metallic reference resistor 30 and the semiconductor reference resistor 32 in the measurement arrangement 16a of Figure 1. In the arrangement shown in Figure 3, the metallic reference resistor 30 and the semiconductor reference resistor 32 are placed in series. If a suitable supply current is fed to the resistors 30, 32, then the voltage ratio V1/V2 can be readily measured, where Vi is the voltage across the semiconductor reference resistor 32 and V 2 is the voltage across the metallic reference resistor 30. This voltage ratio represents the ratio of the resistances of the resistors 32, 30, and is independent of the supply current. This method of interrogating the reference resistors is convenient, but the skilled reader will appreciate that many other comparison methods exist using techniques which are well known in the art. For example, the resistors might be connected in parallel, being fed identical currents provided by a current-mirror circuit.
The voltage ratio might be measured by using one voltage as the reference level and the other the input level for an analogue-to-digital converter. Other suitable techniques will be apparent to those skilled in the art.
In the absence of stress, the semiconductor reference resistor resistance
Rsemi and the metallic reference resistor resistance R me tai can be described by:
Rsemi = Ri -fi(T) and
Rmetai = R2-f2(T)
so that the resistor ratio is given by
= R sem i = R r f i ( T ) =
V2 " R metal ~ %¾( Τ ) "
fi(T) and f 2 (T) describe the temperature dependence of the individual resistances, and RR(T) describes the temperature dependency of the resistor ratio. The temperature dependence of the resistor ratio can be determined in a number of ways. For example, the temperature dependent behaviour of the resistors or a direct measurement of the resistor ratio can be determined prior to packaging of the integrated circuits. Typically, the RC oscillator is calibrated prior to packaging of the integrated circuit, and conveniently the temperature dependence of the resistor ratio can be determined at or around this time. Curve fitting may be performed in order to establish the relationship. It can be expected that the temperature coefficient of the metal is greater than the semiconductor material, and accordingly it may be desirable to ensure that the value of R sem i is much greater than the value of R me tai, so that the temperature induced changes in resistance are of similar magnitude and the stress-induced change in R se mi is not swamped by the temperature induced change in Rmetai-
After packaging, any change in the stress experienced by an integrated circuit will induce changes in R sem i and Rmetai. so that the resistor ratio becomes
¾ ~ %¾T)-(I + GM .AS M ) where AS is the change in strain, G.AS is the fractional resistance change due to this change in strain, and the subscripts indicate semiconductor (S) or metal (M). The ratio of the resistor ratio after the change in stress to the original resistor ratio can therefore be described by:-
RR AS 1 + G S -AS S
RR 1 + G M -AS M If the fractional resistance changes are denoted by 5R, and the ratio of the fractional metal resistance change to the fractional semiconductor resistance change is denoted by k, where M
G S - AS S SR S then the ratio of the resistor ratios can be expressed as
and hence the fractional change in the semiconductor resistance can be calculated from the ratio of the resistor ratios: l - RRR
5R S (2) k - RRR -l
Equation (2) can be used to derive a compensation parameter for stress induced resistance changes with varying degrees of approximation. The first term in the denominator of equation 2 might be ignored completely, since it is known that the change in metal resistance will be much less than the change in semiconductor resistance, and hence k will be very small. Alternatively, higher accuracy can be obtained if the ratio of the gauge factors of the metal and semiconductor materials are known, or may be determined. For example, as stated above, the ratio G M /G S for a metal/polysilicon combination is known to be about 0.1. If it is assumed that the applied stress produces similar levels of strain in the metal and semiconductor reference resistors (i.e, AS S ~ASM), then k can be approximated by 0.1 . At a higher level of accuracy, account can be taken of the actual ratio AS M /AS S by exploiting knowledge of the modulus of elasticity of the metal and semiconductor materials, so as to derive a more accurate value for k. It can be seen that various methods might be implemented in order to derive a value for the stress induced change in the semiconductor resistance from the ratio of the resistor ratio after the change in stress to the original resistor ratio. This value can be calculated using an appropriately configured compensation parameter calculator 16b as shown in Figure 1. In the context of the programmable RC oscillator device shown in Figure 1 , the value er rs represents the change which must be applied to the oscillator programming code to compensate for the effect of stress. The value may be transmitted from the compensation parameter calculator 16b to the control arrangement 14 for the programmable RC oscillator. The control arrangement 14 receives the value 5R S , and uses the value in order to ensure that the RC oscillator produces a desired frequency output. The control arrangement 14 can control the operation of the programmable RC oscillator 2 in response to the received value in a number of ways which would readily occur to one skilled in the art. For example, the control arrangement 14 may ensure that a different combination of resistors and capacitors and/or a different interconnection scheme is used in comparison to a situation where no stress induced variation in the resistance is detected. Additionally, or alternatively, a dithering scheme might be implemented in order to fine tune the frequency of the signal outputted by the programmable oscillator 12.
Various metals may be used to produce the metallic reference resistor.
Advantageously, the resistance of the metal chosen exhibits a low sensitivity to stress, and has a temperature dependence which is close to that of the semiconductor material used in the semiconductor reference resistor. An example of a metal which might be used is tungsten, particularly, but not exclusively, when the semiconductor reference resistor is formed from polysilicon. Advantages include a low gauge factor and a lower modulus of elasticity than polysilicon (the modulus of elasticity is approximately one third that of polysilicon), so that the strain induced by a common stress is lower. This has the effect that the term k in the denominator of equation 2 is smaller, and consequently errors in the value of this term will have less impact on the calculated change in semiconductor resistance.
The metallic reference resistor may be formed in a variety of ways. Many standard silicon wafers offer metal resistors with a typical sheet resistance of the order of 100μΩ per square. Metallic reference resistors may be fabricated using these standard metal resistors, although the resistances associated with such structures are likely to be less than preferable for many applications. Silicon wafers having metal resistors with a larger sheet resistance might be advantageously employed. In an alternative approach, a novel use of via structures is proposed. Many standard silicon wafers have via structures, which are small posts of conductive material filled into a hole between insulating layers, such that conductive layers above and below the via are electrically connected. Figure 4 shows a cross sectional view of a portion of an integrated circuit which depicts a first insulating layer 40 having a second insulating layer 42 formed thereon. Adjacent to the first insulating layer 40 is a conductive layer 44, and a further conductive layer 46 is formed on top of the second insulating layer 42. Figure 4 shows a via structure 48 which is positioned in an aperture formed in the second insulating layer 42. It can be seen that the via 48, which is formed from a metallic material, electrically connects the conductive layers 44, 46. Various materials can be used to form the via 48, but it is commonly formed with tungsten. The present inventors have realised that a plurality of vias can be connected together to form the metallic reference resistor in a convenient manner which can be easily integrated into the design as standard silicon wafers. The reference metallic resistor can be conveniently formed by an arrangement of a plurality of vias in series. It is particularly preferred that an arrangement of tungsten vias is used for this purpose, owing to the advantageous properties of tungsten discussed above, and also because each tungsten via resistance is typically about 5Ω, and therefore a metallic reference resistor having a usable resistance (for example, about a few ΚΩ) is readily manufactured using standard silicon wafers. However, other ways of forming the metallic reference resistor, and other suitable metals for use in the metallic reference resistor would readily occur to the skilled person using the principles described herein.