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Title:
COMPONENT INTERCONNECT WITH SUBSTRATE SHIELDING
Document Type and Number:
WIPO Patent Application WO/2006/007098
Kind Code:
A2
Abstract:
An example of a circuit structure (10) may include a first dielectric layer (30) having first and second surfaces (30a, 30b), and a channel (71) extending at least partially between the first and second surfaces (30a, 30b) and along a length of the first dielectric layer (30). First and second conductive layers (34, 36) may be disposed on respective portions of the first and second surfaces (30a, 30b). A first conductor (64), having an end (64a), may be disposed on a surface (30a) of the first dielectric layer (30). The channel (71) may include at least a first portion (78) extending around at least a portion of the conductor end (64a). The second conductive layer (75) may line the channel (71) extending around a portion of the conductor end (64a). Some examples may include a stripline (60) having a second conductor (58) connected to the first conductor (64). Some examples may include a cover (22) having a wall (28) positioned on the first dielectric layer (30) over the second conductor (58).

Inventors:
STONEHAM EDWARD B (US)
GAUDETTE THOMAS M (US)
Application Number:
PCT/US2005/016890
Publication Date:
January 19, 2006
Filing Date:
May 13, 2005
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
ENDWAVE CORP (US)
STONEHAM EDWARD B (US)
GAUDETTE THOMAS M (US)
International Classes:
H01L39/00
Foreign References:
US4673904A1987-06-16
US6483406B12002-11-19
US6617686B22003-09-09
US6356173B12002-03-12
US20040155723A12004-08-12
Attorney, Agent or Firm:
Anderson, Edward B. (P.C. 520 S.W. Yamhill Street, Suite 20, Portland OR, US)
Download PDF:
Claims:
CLAIMS
1. The invention claimed is: A circuit structure (10) comprising: a first dielectric layer (30) having first and second surfaces (30a, 30b) and a channel (78) extending at least partially between the first and second surfaces; a first conductive layer (34) disposed on at least a portion of the first surface (30a); a first conductor (58) disposed on the second surface (30b) of the first dielectric layer (30) and having an end (58b), the channel (78) including at least a first portion (78c) extending along at least a portion of the conductor end (58b); and a second conductive layer (75) lining at least a portion of the channel (78) extending around at least a portion of the conductor end (58b).
2. The circuit structure (10) of claim 1, in which the channel (78) includes a second portion (78d) extending along at least a portion of the conductor end (58b), the first and second portions (78c, 78d) being spaced apart, with a portion of the first dielectric layer (30) adjacent to the conductor end (58a) extending between the first and second portions (78c, 78d) of the channel (78).
3. The circuit structure (10) of claim 2, further comprising a substrate component (42) and a first interconnect (68), the substrate component (42) being mounted relative to the second surface (30a), spaced from the conductor end (58b), and having a terminal (46), the first interconnect (68) extending between the conductor end (58b) and the substrate component terminal (46).
4. The circuit structure (10) of claim 3, in which at least a first portion of the substrate component (42) is mounted relative to the portion of the dielectric layer (30).
5. The circuit structure (10) of claim 4, in which the first conductive layer (34) extends along the portion of the dielectric layer (30), and the substrate component (42) is mounted to the first conductive layer (34).
6. The circuit structure (10) of claim 4, in which a second portion of the substrate component (42) extends over the channel (78).
7. The circuit structure (10) of claim 1, in which at least a portion of the channel (78) extends through the dielectric layer (30), and the second conductive layer (75) in the channel (78) contacts the first conductive layer (34).
8. The circuit structure (10) of claim 1, in which the channel (78) extends continuously along the conductor end (58a).
9. The circuit structure (10) of claim 8, further comprising a second dielectric layer (32), a third conductive layer (38), a second conductor (64), and a second interconnect (62), the second dielectric layer (30) having a first surface (32a) contacting the first conductive layer (34) opposite the first dielectric layer (30), and a second surface (32b), the third conductive layer (38) being disposed on at least a portion of the second surface (32b) of the second dielectric layer (32), at least a portion of the channel (72) extending through the second conductive layer (36) and the second dielectric layer (32), the second conductor (64) being spaced from the first conductive layer (34) and disposed between the first surface (30a) of the first dielectric layer (30) and the first surface (32a) of the second dielectric layer (32), and the second interconnect (62) extending between the first and second conductors (58, 64).
10. The circuit structure (10) of claim 9, in which the channel (72) also extends along the sides (58c, 64c) of the first and second conductors (58, 64).
11. The circuit structure (10) of claim 10, in which the channel (72) extends only through the first dielectric layer (30) along the second conductor (64).
12. The circuit structure (10) of claim 11, in which the channel (72) extends through both the first and second dielectric layers (30, 32) along the sides (58c) of the first conductor (58).
13. The circuit structure (10) of claim 10, further comprising a conductive cover (22) connected to the first conductive layer (34), mounted relative to the second surface (30a) of the first dielectric layer (30), and having walls (28) connected to the first conductive layer (34) and defining a chamber (26) surrounding the substrate component (42), one of the walls (28) of the chamber (26) extending over the first conductor (58).
14. The circuit structure (10) of claim 1, in which the channel (78) extends only along the conductor end (58b).
15. The circuit structure (10) of claim 1, in which a portion (42a) of the substrate component (42) extends over the channel (78).
16. The circuit structure (10) of claim 15, in which the substrate component (40) straddles the channel (80).
17. A circuit structure (10) comprising: a first dielectric layer (30) having first and second surfaces (30b, 30a); a first conductive layer (36) disposed on at least a portion of the first surface (30b) of the first dielectric layer (30); a first conductor (64) disposed on the second surface (30a) of the first dielectric layer (30); a second conductive layer (34) disposed on at least a portion of the second surface (30a) of the first dielectric layer (30) spaced from the first conductor (64); a second dielectric layer (32) having a first surface (32a) contacting the first conductive layer (36) opposite the first dielectric layer (30), and a second surface (32b); a third conductive layer (38) disposed on at least a portion of the second surface (32b) of the second dielectric layer (32); a second conductor (58) spaced from the first conductive layer (36) and disposed between the first surface (30b) of the first dielectric layer (30) and the first surface (32a) of the second dielectric layer (32); a first interconnect (62) extending between the first and second conductors (64, 58); and a conductive wall (28) disposed over the second conductor (58), connected to the second conductive layer (34), and mounted relative to the second surface (30a) of the first dielectric layer (30).
18. The circuit structure (10) of claim 17, further comprising a substrate component (42) mounted on the second conductive layer (34) spaced from the first conductor (64) and having a terminal (46); and a second interconnect (68) extending between the first conductor (64) and the substrate component terminal (46).
19. The circuit structure (10) of claim 17, further comprising a conductive cover (22) including the conductive wall (28), the conductive cover (22) being supported on the second conductive layer (34) and surrounding the first conductor (64).
20. The circuit structure (10) of claim 17, in which the wall (28) has a first side (28b) facing the first conductor (64), and a second side (28a) opposite the first side (28b), the circuit structure (10) further comprising a third conductor (50) disposed on the second surface (30a) of the first dielectric layer (30) on the second side (28a) of the wall (28), spaced from the second conductive layer (34), and a second interconnect (56) connecting the second and third conductors (58, 50).
21. The circuit structure (10) of claim 20, further comprising a conductive cover (22) including the conductive wall (28), the conductive cover (22) being supported on the second conductive layer (34) and including a first chamber (26) surrounding the first conductor (64) and a second chamber (24) surrounding the third conductor (50).
22. The circuit structure (10) of claim 21, further comprising a channel (71) extending between the first and second surfaces (30b, 30a) of the first dielectric layer (30), the channel (71) also extending in a continuous loop around the first and third conductors (64, 50), the second conductive layer (34) lining at least a portion of the channel (71).
23. The circuit structure (10) of claim 22, in which at least a portion of the channel (71) also extends through the second dielectric layer (32) and the first conductive layer (36).
24. The circuit structure (10) of claim 23, in which the second conductor (58) has sides (58c, 58d), and the channel (71) extends through the first and second dielectric layers (30, 34) and the first conductive layer (36) along the sides (58c, 58d) of the second conductor (58).
25. The circuit structure (10) of claim 22, further comprising a substrate component (42) and a third interconnect (68), the substrate component (42) having a terminal (46), being mounted relative to the second surface (30a) of the first dielectric layer (30) in the first chamber (26), on a side of the channel (71) opposite from the first conductor (64), the third interconnect (68) interconnecting the first conductor (64) and the substrate component terminal (46).
Description:
COMPONENT INTERCONNECT WITH SUBSTRATE SHIELDING

BACKGROUND Interconnects between transmission lines, and between a transmission line and a circuit structure, such as a lumped element or a substrate component, may produce interference and/or be subject to interference from other circuits. Shielding may reduce interference between communication signals carried on different transmission lines and other circuit structures. A coaxial cable is a transmission line in which an outer conductor that surrounds an inner conductor provides shielding. Such coaxial cables require separate mechanical interconnects that match the cable configuration. Various other forms of transmission lines have been developed that are formed on or in circuit boards. These include microstrip and other strip lines, slot lines, coplanar waveguides, and the like. These transmissions lines, as well as other circuit components are generally not shielded, with the result that evanescent electromagnetic fields may be produced that can interfere with the operation of other circuit components.

BRIEF SUMMARY OF THE DISCLOSURE A circuit structure may include a first dielectric layer having first and second surfaces, and a channel extending at least partially between the first and second surfaces and along a length of the first dielectric layer. First and second conductive layers may be disposed on at least respective portions of the first and second surfaces. A first conductor, having an end, may be disposed on a surface of the first dielectric layer. The channel may include at least a first portion extending around at least a portion of the conductor end. The second conductive layer may line the channel extending around at least a portion of the conductor end. Some examples may include a stripline having a second conductor connected to the first conductor, or a cover having a wall positioned on the first dielectric over the second conductor. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a top view of an interconnect circuit structure with shielding. FIG. 2 is a cross section taken along line 2-2 of FIG. 1. FIG. 3 is a cross section taken along line 3-3 of FIG. 1.

DETAILED DESCRIPTION OF VARIOUS EMBODIMENTS FIGS. 1-3 depict a simplified exemplary circuit structure 10 having various features illustrated in a single composite embodiment for convenience. These features may have various forms, and may be realized in other circuit structures individually or in various other combinations. As used herein, a circuit structure and a circuit assembly may individually or in combination form one or more complete circuits, one or more portions of one or more circuits, one or more combinations of elements or components of a circuit, or any combination of circuits, circuit portions, and circuit components, and may include shared circuit portions or components. In this example, then, circuit structure 10 may include one or more of a first circuit assembly 12, a second circuit assembly 14, and a connecting circuit assembly 16. Circuit assembly 16 may be connected to one or both of circuit assemblies 12 and 14, and further may interconnect circuit assemblies 12 and 14, such as is shown. Circuit structure 10 may also include a cover 22 that may cover one or both of circuit assemblies 12 and 14. The cover may be made of any appropriate material. For example, the cover may be made of an electromagnetically (including electrically or magnetically) conductive material, such as aluminum, copper or other metal, and may be formed of a single homogeneous material, or a combination of materials, at least one of which is conductive, such as a conductive layer with a non-conductive or semi-conductive material. Cover 22 may provide one or more chambers that may protect enclosed circuit assemblies from environmental and electromagnetic influences and/or isolate the enclosed circuit assemblies. For example, cover 22 may form a first chamber 24 covering circuit assembly 12, and a second chamber 26 covering circuit assembly 14. In this example, a common wall 28 may separate chambers 24 and 26. Wall 28 may have opposite faces or sides 28a and 28b, and may extend along circuit assembly 16. I Generally, circuit structure 10 may further include first and second dielectric layers 30 and 32, having respective first and second surfaces 30a, 30b and 32a, 32b. A top metal layer 34 is in contact with dielectric surface 30a, an intermediate metal layer 36 extends between dielectric surfaces 30b and 32a, and a base metal layer 38 extends along surface 32b. These various layers are not shown to scale, and may have thicknesses different than those shown. For instance, base metal layer 38 may be a conductive substrate used in packaging, as a carrier of circuits, or as part of a housing that includes cover 22. As mentioned, circuit assemblies 12, 14 and 16 may include various components. For purposes of illustration, circuit assemblies 12 and 14 may include respective circuit elements 40 and 42. These circuit elements may for instance include a lumped element or combination or network of passive and/or active elements, such as transmission lines, resistors, capacitors, inductors, and semiconductor devices, and may be mounted on a circuit chip having a dielectric, semiconductive or conductive substrate. When circuit element 40 or 42 includes a substrate, it may also be referred to as a substrate component 40 or 42. In one example, the circuit assemblies may include one or a combination of diodes and transistors in an integrated circuit (IC) or chip, including, for example, a monolithic microwave integrated circuit (MMIC), application specific integrated circuit (ASIC), or the like. Circuit elements 40 and 42 may have a conductive pad, conductor or terminal, such as respective terminals 44 and 46, each of which accommodates connection to another circuit element. Interconnect circuit assembly 16 may interconnect circuit assemblies 12 and 14. This may include an interconnection 47, such as a bond wire 48 interconnecting terminal 44 with a signal conductor 50 of a microstrip line 52. Conductor 50 may include first and second ends 50a and 50b, and opposite sides 50c and 5Od. Intermediate metal layer 36 may serve as a signal return conductor, also referred to as a reference potential or ground conductor or plane, for the microstrip line. Conductor 50 may be positioned on dielectric layer 30 in an opening 54 in top metal layer 34. End 50b of conductor 50 may be connected to a via 56 extending through dielectric layer 30 to a center conductor 58 of a stripline 60. Metal layers 34 and 38 I may function as ground planes for the stripline. Conductor 58, having ends 58a and 58b, and sides 58c and 58d, also may extend under wall 28 to a second via 62. Vias 56 and 62 may also be referred to as interconnects. Via 62 may extend from conductor 58 to a second signal conductor 64 of a second microstrip line 66. Similar to conductor 50, conductor 64 may be positioned on dielectric layer 30 in an opening 67 in top metal layer 34. Conductor 64 also may include first and second ends 64a and 64b, and opposite sides 64c and 64d. Again, metal layer 36 may function as a ground plane for microstrip line 66. End 64a of the signal conductor may be connected to terminal 46 of circuit element 42, by another interconnection 47 in the form of a bond wire 68. This simplistic illustration shows a transition in the form of interconnection assembly 16, coupling circuit element 40 and circuit element 42 using bond wire connections to microstrip lines, and vias interconnecting microstrip lines and an interconnecting stripline. The microstrip lines conduct signals on the surface of dielectric layer 30, whereas the stripline conducts signals under dielectric layer 30, or within dielectric layers 30 and 32. Top metal layer 34 extends over the stripline, providing a layer for supporting wall 28 of cover 22, which layer also provides continuity of ground between the cover and the top metal layer. By using this interconnect circuit structure, chambers 24 and 26 enclose circuit assemblies 12 and 14, effectively shielding them from electromagnetic interference from each other and from other external circuits. A series 70 of channels 71 may provide further shielding between circuit structures. For example, channels 71 may include side trenches 72 and 74 that extend along the sides of microstrip lines 52 and 66, and stripline 60. In particular, trench portions 72a, 74a may extend along respective sides 50c, 5Od of signal conductor 50, portions 72b, 74b may extend along respective sides 58c, 58d of stripline center conductor 58, and portions 72c, 74c may extend along respective sides 64c, 64d of signal conductor 64. Trenches 72 and 74 may extend through upper dielectric layer 30 between top and intermediate metal layers 34 and 36. Trench portions 72b and 74b also may further extend through lower dielectric layer 32, to bottom metal layer 38, as particularly shown in FIG. 2. As shown in the figures, trenches 72 and 74 have a layer of metal or lining 75 in them that, Il v depending on the trench portion, may contact the top, intermediate and bottom metal layers, depending on the depth of the trench. Trench series 70 of channels 71 may also include end trenches 76 and 78 extending along the ends 50a and 64a of microstrip conductors 50 and 64, respectively. Trenches 76 and 78 may extend partially or completely across the ends of the microstrip lines. For example, trench 76 is shown extending continuously along conductor end 50a. Optionally, trench 76 may extend only along a portion adjacent to trenches 72 and 74, as represented by trench ends 76a and 76b, shown in dashed lines, defining short trench portions 76c and 76d. Additionally or alternatively, a trench 80, as shown in dashed lines in FIGS. 1 and 2, may extend in at least dielectric layer 30 under circuit element 40, with a side 80a facing microstrip line 52. End trench 78, illustrated in cross section in FIG. 3, may include ends 78a and 78b defining trench portions 78c and 78d. In the example shown, circuit element 42 has an end 42a extending over trench 78. In particular, trench end 78a is spaced from circuit element 42 and trench end 78b is positioned below the circuit element. A land or neck 82, formed by dielectric layer 30 and top metal layer 34, may extend between trench ends 76a, 76b. Circuit element 42 may be supported on neck 82 during mounting, allowing a portion of the circuit element to extend over trench portion 78d. Circuit element 42 may extend adjacent to the trench, may extend partially over the trench, or may extend to the opposite side of the trench, as shown in dashed lines. End trenches 76 and 78 may be lined with metal lining 75, shown as though it is continuous with top metal layer 34. Depending on the depth of the trenches and the extent of placement of the lining, the lining may or may not contact more than one metal layer. In the examples shown, the trenches extend entirely through at least upper dielectric layer 30, with lining 75 contacting metal layers 34 and 36. Trench side portions 72b and 74b also extend through lower dielectric layer 32, with the lining further contacting bottom metal layer 38. The trenches may also extend only partially through one or both dielectric layers, in which case there may be contact with fewer metal layers. The trenches may extend partially or completely through each dielectric layer. I The trenches with metal lining 75 form a vertical shield for evanescent electromagnetic fields in the dielectric, which fields may be generated by circuit structures on one or both sides of the trench. The longer and deeper the trenches are, the more complete is the shielding that they provide, and the greater the isolation they provide. For example, optional shortened trench portions 76a and 76b provide limited shielding, continuous trench 76 provides greater shielding, and trench 78 having an intermediate extent along the end of conductor 64 of microstrip line 66, provides an intermediate amount of shielding. Optionally, one or more of the trenches described may have lengths longer or shorter than those shown, be formed of separate trench portions, extend at angles, or extend along curved or irregular lines. Further, the metal layer lining the trenches may cover all or a portion of the trench surfaces. It will be appreciated, then, that a circuit structure may include a configuration of dielectric layers, conductive layers, and conductors. In some examples, a first dielectric layer may have first and second surfaces. A first conductive layer may be disposed on at least a portion of the first surface of the first dielectric layer. A first conductor may be disposed on the second surface of the first dielectric layer. A second conductive layer may be disposed on at least a portion of the second surface of the first dielectric layer spaced from the first conductor. A second dielectric layer may have a first surface contacting the first conductive layer opposite the first dielectric layer, and a second surface. A third conductive layer disposed on at least a portion of the second surface of the second dielectric layer. A second conductor may be spaced from the first conductive layer and disposed between the first surface of the first dielectric layer and the first surface of the second dielectric layer. A first interconnect may extend between the first and second conductors. Further, a conductive wall may be disposed over the second conductor, connected to the second conductive layer, and mounted relative to the second surface of the first dielectric layer. Accordingly, while embodiments of circuit structures have been particularly shown and described with reference to the foregoing disclosure, many variations may be made therein. Other combinations and sub-combinations of features, functions, elements and/or properties may be used. Such variations, whether they are directed to different combinations or directed to the same combinations, whether different, broader, narrower or equal in scope, are also regarded as included within the subject matter of the present disclosure. The foregoing embodiments are illustrative, and no single feature or element is essential to all possible combinations that may be claimed in this or later applications. The claims, accordingly, define inventions disclosed in the foregoing disclosure. Where the claims recite λλa" or λλa first" element or the equivalent thereof, such claims include one or more such elements, neither requiring nor excluding two or more such elements. Further, ordinal indicators, such as first, second or third, for identified elements are used to distinguish between the elements, and do not indicate a required or limited number of such elements, and do not indicate a particular position or order of such elements unless otherwise specifically stated.