Title:
COMPOSITE SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2016/185745
Kind Code:
A1
Abstract:
Provided is a composite semiconductor device that has low on-resistance and that is highly tolerant of load short circuits. A composite semiconductor device (10) that is provided with a normally-on first FET (Q1) and a normally-off second FET (Q2) that are cascode-connected to each other. When T is a post-short-circuit elapsed time that is the time elapsed from the beginning of the short circuiting of a load that is connected to the composite semiconductor device (10), RonQ2 is the on-resistance value of the second FET, VTHQ1 is the threshold voltage of the first FET, Idmax1 is the drain current of the first FET when the first FET is in a neutral state and the gate voltage of the first FET is 0 V, and Idmax is drain current limited to prevent the first FET from breaking when the post-short-circuit elapsed time T is greater than or equal to 2 μsec, the present invention satisfies the given formula when the voltage applied to a drain of the first FET (Q1) is 400 V.
Inventors:
NAKAJIMA AKIO
ICHIJOH HISAO
ICHIJOH HISAO
Application Number:
PCT/JP2016/055085
Publication Date:
November 24, 2016
Filing Date:
February 22, 2016
Export Citation:
Assignee:
SHARP KK (JP)
International Classes:
H01L21/822; H01L27/04; H02M7/48; H03K19/003
Domestic Patent References:
| WO2015033631A1 | 2015-03-12 | |||
| WO2014192348A1 | 2014-12-04 |
Foreign References:
| JP2006324839A | 2006-11-30 | |||
| JP2011166673A | 2011-08-25 | |||
| JP2012222360A | 2012-11-12 | |||
| JP2014187726A | 2014-10-02 |
Attorney, Agent or Firm:
HARAKENZO WORLD PATENT & TRADEMARK (JP)
特許業務法人ＨＡＲＡＫＥＮＺＯ ＷＯＲＬＤ ＰＡＴＥＮＴ ＆ ＴＲＡＤＥＭＡＲＫ (JP)
特許業務法人ＨＡＲＡＫＥＮＺＯ ＷＯＲＬＤ ＰＡＴＥＮＴ ＆ ＴＲＡＤＥＭＡＲＫ (JP)
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