COMPRESSOR CIRCUIT, WALLACE TREE CIRCUIT, MULTIPLIER CIRCUIT, CHIP AND DEVICE

WIPO Patent Application WO/2019/196727

A1

Provided in the present application are a compressor circuit, a Wallace tree circuit, a multiplier circuit, a chip and a device, the compressor circuit comprising a first full adder, a second full adder and a first selection circuit; an output end of the first full adder is connected to an input end of the first selection circuit, and an output end of the first selection circuit is connected to an input end of the second full adder; the first selection circuit is used to determine, according to the first selection signal, an input signal that is outputted by the first selection circuit to the second full adder; the input signal outputted by the first selection circuit to the second full adder and the highest bit signal of a multi-bit input signal of the compressor circuit are used to control the startup or shutdown of the second full adder, which may reduce the power consumption of a circuit as well as time delays.

LIU ENHE (CN)
LIU SHAOLI (CN)
LI ZHEN (CN)

PCT/CN2019/081407

October 17, 2019

April 04, 2019

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CAMBRICON TECH CORP LTD (CN)

H03K19/20

CN106897046A	2017-06-27
CN101258464A	2008-09-03
US20050027777A1	2005-02-03

CHEN CHAO;LUO XIAO-HUA;CHEN SHU-QUN;YU GUO-JUN: "Optimizing Implementation of Gaussian Filter based on Field Programmable Gate Array", JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), vol. 51, no. 5, 31 May 2017 (2017-05-31), pages 969 - 975, XP009522682
See also references of EP 3748857A4

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