Title:
COMPUTER SYSTEM AND CONTROL METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2023/084748
Kind Code:
A1
Abstract:
A computer system (10) according to the present invention processes input data, and comprises a plurality of calculation units (11_1 to 11_N) and a host unit (12) that is connected to and controls the plurality of calculation units, wherein: the processed data is transferred between the plurality of calculation units; the calculation units are respectively provided with trace units (14_1 to 14_N) that record trace data upon detecting a prescribed event from the input data, said trace data having a timestamp value that is the detection time of the event based on the operating frequency of the calculation units; and the plurality of calculation units are synchronized. Thus the present invention can provide a computer system that easily synchronizes a plurality of calculation units.
Inventors:
ARIKAWA YUKI (JP)
MIURA NAOKI (JP)
TANAKA KENJI (JP)
ITO TSUYOSHI (JP)
SAKAMOTO TAKESHI (JP)
MURANAKA YUSUKE (JP)
MIURA NAOKI (JP)
TANAKA KENJI (JP)
ITO TSUYOSHI (JP)
SAKAMOTO TAKESHI (JP)
MURANAKA YUSUKE (JP)
Application Number:
PCT/JP2021/041776
Publication Date:
May 19, 2023
Filing Date:
November 12, 2021
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
G06F11/34; G06F15/82
Domestic Patent References:
| WO2018182782A1 | 2018-10-04 | |||
| WO2010038459A1 | 2010-04-08 |
Foreign References:
| US20120331354A1 | 2012-12-27 |
Other References:
TANAKA; KENJI; ET AL: "7A-01 Study of FPGA Ring-Allreduce for Accelerating Distributed Deep Learning", PROCEEDINGS OF THE 82ND NATIONAL CONVENTION OF IPSJ, vol. 82, no. 1, 20 February 2020 (2020-02-20), pages 1 - 31, 1-32, XP009537479
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (JP)
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