Title:
COMPUTER SYSTEM AND FAILURE MANAGEMENT METHOD
Document Type and Number:
WIPO Patent Application WO/2017/199288
Kind Code:
A1
Abstract:
This computer system has a plurality of nodes, and these plurality of nodes exchange information with each other using a first communication protocol. Each node comprises a processor, a functional device, and a failure management circuit which exchanges information relating to failures with the functional device and the processor using a second communication protocol, and also exchanges information relating to these failures with other nodes using the first communication protocol. When the failure management circuit of a first node has received a failure occurrence notification from the functional device of the first node using the second communication protocol, the failure management circuit transmits, using the first communication protocol, a failure occurrence notification to a second node that is using the functional device of the first node.
Inventors:
TSUNODA TAKANOBU (JP)
Application Number:
PCT/JP2016/064483
Publication Date:
November 23, 2017
Filing Date:
May 16, 2016
Export Citation:
Assignee:
HITACHI LTD (JP)
International Classes:
G06F3/06
Foreign References:
| JP2007200319A | 2007-08-09 | |||
| JPH11252181A | 1999-09-17 | |||
| JPH07152697A | 1995-06-16 |
Attorney, Agent or Firm:
WILLFORT INTERNATIONAL PATENT FIRM (JP)
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