Title:
COMPUTER SYSTEM AND FAULT ISOLATION METHOD
Document Type and Number:
WIPO Patent Application WO/2017/006457
Kind Code:
A1
Abstract:
Provided is a computer system, comprising a plurality of computers. The computers are connected to a device via a device interface. The device interface comprises a fault information register and a link state register. A fault isolation unit of the computers periodically acquires values of the fault information register and the link state register. The fault isolation unit determines whether a fault has occurred with the device, determines whether the fault which has occurred with the device is a fault subject to isolation, and if it is determined that the fault is not a fault subject to isolation, determines whether the fault is a fault subject to isolation on the basis of the values of the fault information register and the link state register which are re-acquired after a given time has elapsed. If it is determined that the fault is a fault subject to isolation, the fault isolation unit senses the fault as a fault of a protocol arising from an interruption of a power supply which supplies power to the device.
Inventors:
SUGIMOTO KEN (JP)
FUNAYA YUSUKE (JP)
FUNAYA YUSUKE (JP)
Application Number:
PCT/JP2015/069626
Publication Date:
January 12, 2017
Filing Date:
July 08, 2015
Export Citation:
Assignee:
HITACHI LTD (JP)
International Classes:
G06F13/00; G06F11/30
Domestic Patent References:
| WO2014115257A1 | 2014-07-31 | |||
| WO2012063358A1 | 2012-05-18 | |||
| WO2012169637A1 | 2012-12-13 |
Attorney, Agent or Firm:
TOU-OU PATENT FIRM (JP)
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