Title:
CONCATENATED TWO-WIRE DATA BUS CONSISTING OF TWO SINGLE-WIRE DATA BUSES, EACH WITH A PLURALITY OF DIFFERENTIAL LEVELS FOR TRANSMITTING ILLUMINATION DATA ON THE BASIS OF THE JTAG PROTOCOL
Document Type and Number:
WIPO Patent Application WO/2018/114937
Kind Code:
A3
Abstract:
The invention relates to a light module and the matching housing (GH) for a bus node (BSn) in the form of an integrated circuit. The light module is provided to be used in a data bus system for transmitting illumination data for light-emitting means (LED1, LED2, LED3) by means of a differential two-wire data bus (b1, b2, b3), the differential two-wire data bus (b1, b2, b3) being an essential component of the light module concept. The two-wire data bus (b1, b2, b3) is designed to transmit data between a bus master (BM) and at least two bus nodes (BS1, BS2, BS3). The two-wire data bus (b1, b2, b3) is divided by the bus nodes (BS1, BS2, BS3) into at least two two-wire data bus sections (b1, b2, b3). The bus nodes (BS2, BS3) are provided to be connected to a preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3) or the bus master (BM) by a preceding two-wire data bus section (b2, b3) of the two-wire data bus sections (b1, b2, b3). The housing (GH) of the bus node (BSn) comprises at least two rows of connections, a first row of connections (GND, b1a, b1b, Vbat) and a second row of connections (GND, b2a, b2b, Vbat). At least these at least two rows of connections are arranged opposite each other on the housing (GH). Each of the rows of connections comprises one connection (GND) for the negative supply voltage and preferably one connection (Vbat) for the positive supply voltage, which are arranged in each row of connections such that they can be connected according to their function in pairs without intersection. The in each case two connections (b1a, b1b) for the respective two-wire data bus sections (b1, b2) are arranged between the connections for the supply voltages in in each case one row of connections. A light-emitting means (LED1, LED2, LED3) is arranged in a recess (ASP) of the housing.
Inventors:
SCHMITZ CHRISTIAN (DE)
Application Number:
PCT/EP2017/083523
Publication Date:
November 22, 2018
Filing Date:
December 19, 2017
Export Citation:
Assignee:
ELMOS SEMICONDUCTOR AG (DE)
International Classes:
G06F13/42; F21S4/24; H05B37/02
Domestic Patent References:
| WO2013095133A1 | 2013-06-27 |
Foreign References:
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Attorney, Agent or Firm:
DOMPATENT VON KREISLER SELTING WERNER - PARTNERSCHAFT VON PATENTANWÄLTEN UND RECHTSANWÄLTEN MBB (DE)
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