Field

Examples relate to a conversion circuitry, a means for converting, a conversion method, a Delta-Sigma-modulator, a Delta-Sigma-modulation means, a digital to analog conversion cir cuit, a digital to analog conversion means, a mobile device, a communication device and a base station transceiver.

Background

The analog to digital conversion of analog signals is a field of research and development. One group of circuits suitable for the analog to digital conversion of analog signals are Delta- Sigma-modulators. Delta-Sigma-modulators comprise a quantizer for sampling the analog signal and a digital to analog converter circuit for providing a feedback signal for the quan tizer.

Brief description of the Figures

Some examples of apparatuses and/or methods will be described in the following by way of example only, and with reference to the accompanying figures, in which

Fig. la shows a block diagram of an example of a conversion circuitry, an example of a digital to analog conversion circuit comprising the conversion circuitry and an example of a Delta-Sigma-modulator comprising the digital to analog conversion circuit comprising the conversion circuitry;

Fig. lb shows a block diagram of an example of a conversion circuitry, and an example of a Delta-Sigma-modulator comprising the conversion circuitry;

Fig. lc shows a flow chart of an example of a conversion method; Fig. 2 shows a block diagram of an example of a mobile device or a communication device comprising a Delta-Sigma modulator with a conversion circuitry and an example of a base station transceiver comprising a Delta-Sigma modulator with a conversion circuitry;

Fig. 3a shows a simplified schematic diagram of a multi-bit Sigma-Delta modulator- based analog-to-digital converter;

Fig. 3b shows a simplified schematic diagram of a multi-bit differential digital-to-analog- converter;

Fig. 3c shows an exemplary switching scheme of a multi-bit differential digital-to-analog converter that is driven by a monotonic ADC (e.g. Flash- ADC);

Fig. 3d shows a simplified schematic diagram of a multi-bit differential digital-to-analog converter with dumping circuitry;

Fig. 3e shows an exemplary dumping switching scheme of a multi-bit differential digital- to-analog converter that is driven by a monotonic ADC (e.g. Flash-ADC);

Fig. 4a shows an example of a switching scheme for a 4 bit multi-bit differential digital- to-analog converter driven by a voltage-controlled oscillator type analog-to-digi- tal converter; and

Fig. 4b shows an exemplary dumping switching scheme of a multi-bit differential digital- to-analog converter driven by a voltage-controlled oscillator type analog-to-digi- tal converter.

Detailed Description

Various examples will now be described more fully with reference to the accompanying draw ings in which some examples are illustrated. In the figures, the thicknesses of lines, layers and/or regions may be exaggerated for clarity. Accordingly, while further examples are capable of various modifications and alternative forms, some particular examples thereof are shown in the figures and will subsequently be described in detail. However, this detailed description does not limit further examples to the particular forms described. Further examples may cover all modifications, equivalents, and alternatives falling within the scope of the disclosure. Same or like numbers refer to like or similar elements throughout the description of the figures, which may be implemented iden tically or in modified form when compared to one another while providing for the same or a similar functionality.

It will be understood that when an element is referred to as being“connected” or“coupled” to another element, the elements may be directly connected or coupled or via one or more intervening elements. If two elements A and B are combined using an“or”, this is to be un derstood to disclose all possible combinations, i.e. only A, only B as well as A and B, if not explicitly or implicitly defined otherwise. An alternative wording for the same combinations is“at least one of A and B” or“A and/or B”. The same applies, mutatis mutandis, for combi nations of more than two Elements.

The terminology used herein for the purpose of describing particular examples is not intended to be limiting for further examples. Whenever a singular form such as“a,”“an” and“the” is used and using only a single element is neither explicitly or implicitly defined as being man datory, further examples may also use plural elements to implement the same functionality. Likewise, when a functionality is subsequently described as being implemented using multi ple elements, further examples may implement the same functionality using a single element or processing entity. It will be further understood that the terms“comprises,”“comprising,” “includes” and/or“including,” when used, specify the presence of the stated features, integers, steps, operations, processes, acts, elements and/or components, but do not preclude the pres ence or addition of one or more other features, integers, steps, operations, processes, acts, elements, components and/or any group thereof.

Unless otherwise defined, all terms (including technical and scientific terms) are used herein in their ordinary meaning of the art to which the examples belong. In many circuits, Delta-Sigma-modulators (or Sigma-Delta-modulators) may be used to sam ple analog signals. Such Delta-Sigma-modulators comprise a quantizer and a digital-to-analog converter, which is used to provide a feedback signal to the input of the modulator. The digi- tal-to-analog converter often receives a thermometer-coded input from the quantizer, based on which the feedback signal is generated. The digital-to-analog converter may comprise a plurality of digital to analog conversion units that are controlled by the thermometer-coded input. To achieve a feedback signal with low noise, a dumping scheme may be used by the digital-to-analog converter: If, based on the signal provided by the quantizer, two digital to analog conversion units would mutually cancel out, these units might be disabled (e.g. “dumped from the feedback signal”) and thus might not contribute to the signal noise. With some quantizers, the thermometer-coded signal provided by the quantizer always starts from the same position (e.g. if the signal provided by the quantizer has a logical sequence of n binary values, the thermometer-coded signal may comprise a sequence of k instances of a first value (e.g. 1 or high) and a sequence of n-k sequences of a second value (e.g. 0 or low) fol lowing the sequence of k instances of the first value, wherein the sequence of k instances of the first value (always) starts at position 1 of the logical sequence). As a result, to determine, whether digital to analog conversion units should be dumped, fixed pairwise comparisons can be used, e.g. by comparing signal components located at symmetrical positions within the logical sequence of binary values (e.g. as shown in Fig. 3e).

With other quantizers, e.g. voltage controlled oscillator (VCO)-based quantizers, the starting position of the sequences may shift depending on the signals previously generated by the quantizer. With such an input signal, comparisons of symmetrical positions within the logical sequence of binary values might not yield all pairs of digital to analog conversion units that might be mutually dumped. The concept is shown in more detail in connection with Figs. 3a to 3e.

At least some examples may provide a conversion circuitry or means for converting that is suitable for providing a signal (e.g. an output signal) for digital to analog conversion units of a digital to analog converter based on a thermometer-coded input signal with a thermometer- code with a variable starting position.

Figs la and lb show examples of a conversion circuitry 10 or of a means for converting 10 for a digital to analog conversion circuit 100 or for a digital to analog conversion means 100. Figs la shows the digital to analog conversion circuit 100 or digital to analog conversion means 100 comprising the conversion circuitry 10 or the means for converting 10 and n digital to analog converter units 20. Alternatively, the conversion circuitry 10 or means for convert ing 10 may be separate from the digital to analog conversion circuit 100 or the digital to analog conversion means 100, as shown in Fig. lb. Figs la and lb further show a Delta- Sigma-modulator 1000 or a Delta-Sigma-modulation means 1000 comprising the digital to analog conversion circuit 100 or digital to analog conversion means 100 and/or the conversion circuitry 10 or the means for converting 10. The components of the means for converting 10, the digital to analog conversion means 100 and/or the Delta-Sigma-modulation means 1000 are defined as component means, which correspond to the respective structural components of the conversion circuitry 10, of the digital to analog conversion circuit 100 and/or of the Delta-Sigma-modulator 1000.

The conversion circuitry 10 or means for converting 10 is suitable for converting a thermom eter-coded input signal with a logical sequence of n binary values into an output signal with n ternary values. The output signal is operable (i.e. suitable) for the n digital to analog con verter units 20 of a digital to analog conversion circuit 100. The conversion circuitry 10 is configured to generate the output signal based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values. An offset between a first binary value and a second binary value is the same for the plurality of pairwise comparisons based on the logical sequence of n binary values.

Using a fixed offset may enable using a dumping scheme with a thermometer-coded input signal that has a variable starting point of the thermometer code. This may enable a reduction of noise in such circuits, as digital to analog conversion units, that otherwise might contribute to signal noise, may be dumped from the generation of the signal.

The conversion circuit is configured to determine the output signal based on the thermometer- coded input signal. For example, the thermometer-coded input signal may comprise n input signal components. The n input signal components may be associated with the logical se quence of n binary values, e.g. a logical first input signal component of the input signal may correspond to (e.g. be associated with) a first binary value of the logical sequence of n binary values, a logical second input signal component of the input signal may correspond to (e.g. be associated with) a second binary value of the logical sequence of n binary values. Each signal component may take on one of two values, e.g. a first value or a second value, thus representing a binary value of the logical sequence of n binary values. For example, the first value may be 1 (or“high” or“positive”) and the second value may be 0 or -1 (or“neutral”, “ground”,“low” or“negative”). Alternatively, the first value may be 0 or -1 and the second value may be 1.

The thermometer-coded input signal comprises a thermometer code. The thermometer code may be spread over the logical sequence of binary values. The thermometer code may be represented by a sequence of instances of the first value, e.g. by a sequence of Is or“high” values. The remaining binary values or signal components of the input signal may comprise the second value. Within the logical sequence of signal components, subsequent signal com ponents may have the same value, except at the position or positions within the logical se quence, at which the thermometer-code transitions (e.g. from high to low, from low to high, from 1 to 0 or from 0 to 1). In some thermometer-coded input signals, there may be zero transitions, e.g. if the entire logical sequence of binary values has the same value (e.g. 0 or 1, high or low). In some thermometer-coded input signals, there may be one transition, e.g. if the thermometer-code starts at the first position of the logical sequence or if the thermometer- code ends at the last position of the logical sequence. In some thermometer-coded input sig nals, there may be two transitions, e.g. if the thermometer-code comprises at least one first value and if the first and the last binary value of the logical sequence of binary values both have the first value (and are part of the thermometer-code) or both have the second value. The thermometer code may wrap around at the end of the logical sequence of binary values.

For example, the thermometer-coded input signal may be a thermometer-coded input signal with a variable starting position of the thermometer code. This may enable using the conver sion circuitry and/or the means for converting with an input signal generated by a voltage controlled oscillator-based analog to digital converter. For example, the thermometer code may have a variable starting position. The thermometer code may be a rotating thermometer code. The thermometer-coded input signal may be a thermometer-coded input signal with a rotating thermometer code. For example, the thermometer code might not necessarily start at the first logical position of the logical sequence of binary values. For example, the starting position of the thermometer code within the logical sequence of binary values may depend on at least one preceding state of the input signal. For example, the starting position of the ther mometer code within the logical sequence of binary values may correspond to a position within the logical sequence of binary values succeeding an ending position of a previous ther mometer code within a (directly) preceding state of the input signal.

In at least some examples, as shown in Fig. lb, the conversion circuitry 10 comprises one or more inputs 12 or input means 12 configured to obtain the input signal from a voltage-con trolled oscillator-based quantizer. Such quantizers may be used for high resolution over- sampling ADCs, as they allow one additional order of noise shaping. An input 12 or input means 12 may correspond to an interface for receiving information, which may be in digital (bit) values according to a specified code, within a module, between modules or between modules of different entities.

The output signal comprises n ternary values. Each ternary value of the n ternary values of the output signal may correspond to and/or be associated with a digital to analog converter unit of the n digital to analog conversion units. For example, a ternary value of the output signal may be coupled (e.g. electronically connected) to a digital to analog conversion unit of the n digital to analog converter units it is associated with, e.g. via an output 14 or output means 14. Each binary value of the n binary values of the thermometer-coded input signal may correspond to and/or be associated with a digital to analog converter unit of the n digital to analog conversion units and/or to or with a ternary value of the n ternary values of the output signal. For example, a logical first binary value of the thermometer-coded input signal may correspond to or be associated with a logical first ternary value of the output signal, and may correspond to or be associated with a logical first digital to analog conversion unit of the n digital to analog conversion units.

The n ternary values may e.g. correspond to a positive value, a negative value and a neutral value. The neutral value may be used to“dump” a digital to analog converter unit of the n digital to analog converter units. The output signal is operable (i.e. suitable) for n digital to analog converter units 20 of the digital to analog conversion circuit 100. For example, the output signal may be operable/suitable for controlling the n digital to analog converter units 20 of the digital to analog conversion circuit 100.

In some examples, the conversion circuitry may be configured to generate a differential output signal. The signal previously denoted output signal may be a first polarity component of the differential output signal. The conversion circuitry may be configured to generate a second polarity component of the output signal. The conversion circuitry may be configured to gen erate the second polarity component inverse to the first polarity component of the differential output signal. For example, both the first polarity component and the second polarity compo nent may comprise n ternary values. For each positive value of the first polarity component, the second polarity component may comprise a negative value at the corresponding position within the second polarity component. For each negative value of the first polarity component, the second polarity component may comprise a positive value at the corresponding position within the second polarity component. For each neutral value of the first polarity component, the second polarity component may comprise a neutral value at the corresponding position within the second polarity component.

Alternatively, the differential signal may be generated by the digital to analog conversion units based on a single output signal (e.g. the output signal). For example, the n digital to analog conversion units may be n differential digital to analog conversion units. Each digital to analog conversion unit of the n digital to analog conversion units may be configured to obtain one ternary value (e.g. one signal component of the output signal corresponding to the ternary value) from the conversion circuitry. The n digital to analog conversion units may each be configured to provide a positive voltage or positive current on a first output terminal (e.g. a“p” output terminal for a first polarity component of a differential output signal) of the digital to analog conversion unit and a negative voltage or negative current on a second output terminal (e.g. a“n” output terminal for a second polarity component of the differential output signal) of the digital to analog conversion unit if the ternary value is a positive value. The n digital to analog conversion units may each be configured to provide a negative voltage or negative current on the first output terminal of the digital to analog conversion unit and a positive voltage or positive current on the second output terminal of the digital to analog conversion unit if the ternary value is a negative value. The n digital to analog conversion units may each be configured to provide a ground or common mode voltage or a zero current via both the first and the second terminals if the ternary value is a neutral value.

In at least some examples, the output signal comprises either positive or negative values. The output signal might not comprise both positive and negative values. The output signal may further comprise zero or more neutral values. For example, the output signal may be provided to the n digital to analog conversion units of the digital to analog conversion circuit. As shown in Fig. lb, the conversion circuitry 10 may comprise one or more outputs 14 or output means 14 configured to provide the output signal to the n digital to analog converter units 20 of the digital to analog conversion circuit 100. An output, e.g. the output 14 or the output means 14, may correspond to an interface for transmitting information, which may be represented by digital (bit) values according to a specified code or protocol, within a module, between mod ules, or between modules of different entities. For example, the digital to analog conversion circuit 100 may be a digital to analog conversion circuit 100 of the Delta-Sigma-modulator 1000

The conversion circuitry 10 is configured to generate the output signal based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values. For example, the plurality of pairwise comparisons may determine, whether a first binary value is different from/unequal to the second binary value, e.g. whether the first binary value is a logical 1 value (e.g. a“high” value) and the second binary value is a logical 0 or logical -1 value (e.g. a“low” value) or whether the second binary value is a logical 1 value (e.g. a“high” value) and the first binary value is a logical 0 or logical -1 value (e.g. a“low” value), e.g. to determine, whether the first binary value and the second binary value would mutually cancel themselves out. If this is the case, a neutral value may be generated for the output signal, e.g. to affect a dumping of one or both of the digital to analog conversion units corresponding to the first and/or second binary values.

For example, the n binary values may be represented by a first value and a second value. The conversion circuitry 10 may be configured to determine, whether the first binary value and the second binary value are unequal values e.g. whether the first binary value is a logical 1 value (e.g. a“high” value) and the second binary value is a logical 0 or logical -1 value (e.g. a“low” value) or whether the second binary value is a logical 1 value (e.g. a“high” value) and the first binary value is a logical 0 or logical -1 value (e.g. a“low” value).

The conversion circuitry 10 may be configured to generate a neutral value for the ternary value of the n ternary values corresponding to the first binary value or to the second binary value if the first binary value and the second binary value are unequal values.

For example, n may be an even number. The n digital to analog conversion units may com prise an even number of digital to analog conversion units. The offset between the first binary value and the second binary value may be n/2. For example, if the n digital to analog conver sion units correspond to 16 digital to analog conversion units, the offset may be 8. For exam ple, n/2 pairwise comparisons may be performed. The conversion circuitry may be configured to generate a neutral value for the ternary value of the n ternary values corresponding to the first binary value and to the second binary value if the first binary value and the second binary value are unequal values. As all n binary values may be compared with just n/2 comparisons if n is an even number, these comparisons may suffice and both digital to analog conversion units corresponding to the first and second binary value may be dumped (e.g. their corre sponding ternary values may be set to the neutral value).

Alternatively, n may be an odd number. The offset between the first binary value and the second binary value may be the ceiling function of n/2. For example, if the n digital to analog conversion units correspond to 15 digital to analog conversion units (as shown in Figs. 4a and 4b), the offset may be 8. The plurality of pairwise comparisons may correspond to n pairwise comparisons. This may be necessary to perform pairwise comparisons on all binary values. The conversion circuitry 10 may be configured to generate a neutral value for the ternary value of the n ternary values corresponding either to the first binary value or to the second binary value if the first binary value and the second binary value are unequal values.

The conversion circuitry may be configured to generate a positive or negative value for the ternary value of the n ternary values corresponding (either) to the first binary value or to the second binary value if the second binary value are equal values, e.g. a positive value if both have the first value and a negative value if both have the second value. If n is even, the con version circuitry may be configured to generate a positive or negative value for the ternary value of the n ternary values corresponding to the first binary value and to the second binary value if the second binary value are equal values, e.g. a positive value if both have the first value and a negative value if both have the second value. If the first and second binary value are equal (e.g. they do not cancel out), the ternary values of the n ternary values may reflect the binary values of the n binary values corresponding to the ternary values.

The offset between a first binary value and a second binary value is the same for the plurality of pairwise comparisons based on the logical sequence of n binary values. For example, the offset may be a logically static offset for the plurality of pairwise comparisons. For example, the logical sequence of the thermometer-coded input signal may provide an enumeration of the positions/components of the thermometer-coded input signal. The conversion circuitry 10 or means for converting may be configured to select the first and second binary for the pair wise comparison based on the offset, e.g. based on the enumeration of the positions/compo nents of the thermometer-coded input signal. For example, if n = 15, the offset may be 8. The logical first binary value within the logical sequence of binary values may be pairwise com pared with the logical ninth binary value within the logical sequence of binary values, the logical second binary values may be pairwise compared with the logical tenth binary value etc.

The offset between the first binary value and the second binary value may wrap around at the end of the logical sequence of n binary values. This may enable using the conversion circuitry and/or the means for converting with an input signal generated by a voltage controlled oscil lator-based quantizer. For example, if n = 15, the offset may be 8. The logical seventh binary value may be pairwise compared with the logical fifteenth binary value and the logical eighth binary value may be pairwise compared with the logical first binary value.

In at least some examples, the offset between the first binary value and the second binary value is the ceiling function of n/2. This may enable an identification of suitable digital to analog conversion units that can be dumped.

For example, n may be an odd number. The plurality of pairwise comparisons may correspond to n pairwise comparisons. The n pairwise comparisons may be performed in parallel. This may avoid introducing delays in the generation of the output signal. For example, the conver sion circuitry may comprise n parallel comparison circuits for the plurality of pairwise com parisons, e.g. n XOR (exclusive OR)-based or XNOR (exclusive Negative OR)-based com parison circuits.

Alternatively, n may be an even number. The offset between the first binary value and the second binary value may be n/2. This may enable dumping both digital to analog conversion units associated with the compared binary values. The plurality of pairwise comparisons may correspond to (only) n/2 pairwise comparisons. The n/2 pairwise comparisons may be per formed in parallel. This may avoid introducing delays in the generation of the output signal. For example, the conversion circuitry may comprise (only) n/2 parallel comparison circuits for the plurality of pairwise comparisons, e.g. n/2 XOR-based or XNOR-based comparison circuits. As only n/2 pairwise comparisons might be used, the circuitry required for the com parisons may be reduced.

Figs la and lb further show a Delta-Sigma-modulator 1000 or a Delta-Sigma-modulation means 1000 comprising the conversion circuitry 10 or the means for converting 10. The out put signal may be operable (i.e. suitable) for n digital to analog converter units 20 of a digital to analog conversion circuit 100 the Delta-Sigma-modulator 1000 or Delta-Sigma-modulation means 1000. Within the Delta-Sigma-modulator 1000, the conversion circuitry may be used to convert the signal provided by the (VCO-based) quantizer to the digital to analog converter of the Delta-Sigma-modulator.

In at least some examples, as further shown in Fig. lb, the Delta-Sigma-modulator 1000 com prises a voltage-controlled oscillator-based quantizer 30 or a voltage-controlled oscillator- based quantizing means 30. The voltage-controlled oscillator-based quantizer 30 or the volt- age-controlled oscillator-based quantizing means 30 may be configured to provide the input signal to the conversion circuitry 10. The voltage-controlled oscillator-based quantizing means 30 may correspond to or be implemented by the voltage-controlled oscillator-based quantizer 30. As further shown in Fig. lb, the Delta-Sigma-modulator 1000 or Delta-Sigma- modulation means 1000 may comprise a digital to analog conversion circuit 100 or digital to analog conversion means 100. The digital to analog conversion circuit 100 or digital to analog conversion means 100 may comprise the conversion circuitry 10 or the means for converting 10. Alternatively, the digital to analog conversion circuit 100 or digital to analog conversion means 100 may be separate from the conversion circuitry 10 or the means for converting 10. The digital to analog conversion circuit 100 may comprise the n digital to analog converter units 20. The conversion circuitry 10 or means for converting 10 may be configured to provide the output signal to the n digital to analog converter units 20 of the digital to analog conversion circuit 100 or of the digital to analog conversion means 100.

In at least some examples, as shown in Fig. la, the digital to analog conversion circuit 100 or the digital-to-analog conversion means 100 comprises the n digital to analog converter units 20 and the conversion circuitry 10 or the means for converting 10. The conversion circuitry 10 or the means for converting 10 may be configured to provide the output signal to the n digital to analog converter units 20 of the digital to analog conversion circuit 100 or the digi- tal-to-analog conversion means 100. In examples the conversion circuitry 10 or of the means for converting 10 may be imple mented using one or more circuit gates, one or more transistors, one or more conversion units, one or more means for converting, one or more processing units, any means for processing, such as a processor, a computer or a programmable hardware component being operable with accordingly adapted software. In other words, the described function of the conversion cir cuitry 10 or of the means for converting 10 may as well be implemented in software, which is then executed on one or more programmable hardware components. Such hardware com ponents may comprise a general purpose processor, a Digital Signal Processor (DSP), a mi cro-controller, etc.

More details and aspects are mentioned in connection with the examples described above or below. The examples shown in Figs la or lb may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below (e.g. Fig. lc to 4b).

Fig. lc shows a flow chart of a conversion method. The conversion method is suitable for converting a thermometer-coded input signal with a logical sequence of n binary values into an output signal with n ternary values. The output signal is operable (i.e. suitable) for n digital to analog converter units 20 of a digital to analog conversion means 100 or of a digital to analog converter 100. The conversion method comprises generating 120 the output signal based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values. An offset between a first binary value and a second binary value is the same for the plurality of pairwise comparisons based on the logical sequence of n binary values.

The method may further comprise further features as shown in connection with the conversion circuitry or means for converting of Figs la or lb. For example, as shown in Fig. lc, the conversion method may comprise obtaining 110 the input signal from a voltage-controlled oscillator-based quantizing means or voltage-controlled oscillator-based quantizer. The con version method may comprise providing 130 the output signal to n digital the analog con verter units 20 of the digital to analog conversion means 100. In at least some examples, the n binary values are represented by a first value and a second value. The conversion method may comprise determining 122, whether the first binary value and the second binary value are unequal values. The conversion method may comprise gen erating 124 a neutral value for the ternary value of the n ternary values corresponding to the first binary value or to the second binary value if the first binary value and the second binary value are unequal values.

For example, n may be an even number. The offset between the first binary value and the second binary value may be n/2. n/2 pairwise comparisons may be performed. The method may comprise performing the plurality of pairwise comparisons, e.g. the n/2 pairwise com parisons. The conversion method may comprise generating 124 a neutral value for the ternary value of the n ternary values corresponding to the first binary value and to the second binary value if the first binary value and the second binary value are unequal values.

Alternatively, n may be an odd number. The offset between the first binary value and the second binary value may be the ceiling function of n/2. The plurality of pairwise comparisons may correspond to n pairwise comparisons. The conversion method may comprise generating 124 a neutral value for the ternary value of the n ternary values corresponding either to the first binary value or to the second binary value if the first binary value and the second binary value are unequal values.

More details and aspects are mentioned in connection with the examples described above or below. The example shown in Fig. lc may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above (e.g. Fig. la or lb) or below (e.g. Fig. 2 to 4b).

Fig. 2 shows a block diagram of an example of a mobile device, communication device or mobile terminal 200 comprising a Delta-Sigma-modulator 1000 or a Delta-Sigma-modulation means 1000 and/or of a base station transceiver 250 comprising a Delta-Sigma-modulator 1000 or a Delta-Sigma-modulation means 1000. The Delta-Sigma-modulator 1000 or the Delta-Sigma-modulation means 1000 may be implemented similar to the Delta-Sigma-mod- ulator 1000 or the Delta-Sigma-modulation means 1000 described in connection with Figs la to lc. Such a mobile device, communication device or mobile terminal 200 and/or base station transceiver 250 may use a Delta-Sigma-modulator with a VCO-based quantizer and a dumping scheme-based digital-to-analog converter, which may provide both an additional order of noise shaping provided by the VCO-based quantizer and additional low-noise oper ation enabled by the dumping scheme.

More details and aspects are mentioned in connection with the examples described above or below. The example shown in Fig. 2 may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above (e.g. Fig. la to lc) or below (e.g. Fig. 3a to 4b).

At least some examples may provide a dumping concept for fully-differential DACs (Digital- to-Analog Converter, e.g. the digital-to-analog conversion circuit or the digital-to-analog con version means) for a rotating thermometer code input signal format (e.g. of the thermometer- coded input signal).

At least some examples may relate to a multi-bit Sigma-Delta modulator (e.g. the Delta- Sigma-modulator 1000 and/or the Delta-Sigma modulation means 1000) based Analog-to- Digital converter (ADC, Fig. 3a). Fig. 3a shows a simplified principle of multi-bit Sigma- Delta modulator based ADC. The converter comprises of a Loop filter 302, a multibit ADC 304 and a multibit DAC 306. The n-bit ADC may have a relatively low resolution (e.g. 1 to about 6 bits) and might be realized by a flash type ADC. The connection 305 between the ADC and the DAC might be realized in a thermometer code representation of 2 ^N lines rather than in a binary weighted format. This thermometer code representation may be used to drive the DAC cells inside the n-bit DAC, i.e. each of the ADC digital output lines drives one of the DAC cells.

The multi-bit differential DAC (Fig. 3b) comprises a number M of identical DAC slices (e.g. the n digital to analog conversion units). Fig. 3b shows a simplified schematic diagram of a multi-bit differential DAC. The output signals I _p 310 and I _n 312 of (all) the slices may be connected together. Depending on the digital input code of the DAC, a certain number of Iceii _p 314 cells and I _C eii_n 316 cells are connected to the positive output I _p 310. The opposite number of I _ce ii _P cel Is and i _C eii_n cells are connected to the negative output I _n 312. Switches 318 may be used to select, whether I _{ceii p} 3 14 cells and/or I _¥h-h 316 are connected to the outputs. Fig. 3c shows an exemplary switching scheme of a Multi-bit differential DAC (e.g. the digital to analog conversion circuit 100) that is driven by a monotonic ADC (e.g. Flash- ADC), e.g. driven by a thermometer code type ADC. Fig. 3c may show an example of the switching schema for a 4 bit DAC for all possible input code combinations. In the first column 320, the input code is shown. Columns 2 to 16 322 show the individual input signal components for DAC cells 1 to 15. The last column 324 shows the sum of the addition of the signal compo nents for DAC cells 1 to 15. For the maximum code of 15 (denoted by reference sign 326) all positive current sources are connected to the positive output. The sum of the currents is 15. For a code of 14 (denoted by reference sign 328), only 14 positive current sources and 1 negative current source are connected to the positive output. Therefore one of the positive currents is compensated by one negative current, resulting only in 13 effective positive cur rents at the output, and so on. For a given digital input signal, the selected DAC cells may always the same ones, i.e. only dependent on the digital code. Independent of the input code, (all) DAC cells may be connected and may contribute noise to the output.

In order to avoid this, a dumping scheme, as shown in Fig. 3d, may be used. Fig. 3d shows a simplified schematic diagram of a multi-bit differential DAC with dumping circuitry. The output signals I _p 330 and I _n 332 of (all) the slices may be connected together. Depending on the digital input code of the DAC, a certain number of I _ce ii _p 334 cells and I _ce ii_n 336 cells are connected to the positive output I _p 330 and the negative output I _n 332. Switches 338 may be used to select, whether I _ce ii _p 334 cells and/or I _ce ii_n 336 are connected to the outputs. Here cells, of which currents are compensated, are pairwise disconnected from the DAC output nodes and dumped to a common mode voltage. In this way, (only) the current sources which contribute to the output current might generate noise at the output.

The corresponding switching scheme is shown in Fig. 3e. Fig. 3e shows an exemplary dump ing switching scheme of a Multi-bit differential DAC that is driven by a monotonic ADC (e.g. Flash- ADC), e.g. driven by a thermometer code type ADC. In the first column 340, the input code is shown. Columns 2 to 16 342 show the individual input signal components for DAC cells 1 to 15. The last column 344 shows the sum of the addition of the signal components for DAC cells 1 to 15. For the maximum code of 15 (as denoted by reference sign 346) all positive current sources may be connected to the positive output. The sum of the currents is 15. For a code of 14 (as denoted by reference sign 348) only 13 positive current sources might be con nected to the positive output. One positive and one negative current source (shown in columns 2 and 16) may be dumped out. The resulting output current is still 13 as in the conventional switching scheme. The dumping may be performed by pairwise comparison of fixed cell pairs, [Celll, Cell 15], [Cell2, Cell 14], ... , [Cell7, Cell9] If these cells drive the opposite current, they may be dumped. 7 comparisons may be necessary in the example in Fig 3e.

In at least some examples, VCO (Voltage-Controlled Oscillators) based quantizers (e.g. the voltage controlled oscillator-based quantizer 30) may be used in multi-bit Sigma-Delta mod ulators, as this may allow one additional order of noise shaping, which may increase the res olution of the modulator. The output format of VCO quantizer based ADCs (e.g. the ther mometer-coded input signal) may have thermometer codes too, but the thermometer code might have no fixed starting point. The starting point may depend on the previous output value.

So for a given digital input signal the selected DAC cells might not always be the same ones and the known dumping schema might not work.

At least some examples may use a knowledge of signal properties of the VCO based ADC output code in order to combine this information to generate a dumping scheme that fits to this code. This may enable using the DAC noise reduction of the dumping concept in combi nation with VCO based ADCs.

Fig. 4a may show a conventional switching scheme of a Multi-bit differential DAC driven by a VCO type ADC. Fig. 4a may show an example of the switching scheme for a 4 bit multi-bit differential digital-to-analog converter driven by a voltage-controlled oscillator type analog- to-digital converter for all possible input code combinations. In the first column 400, the input code is shown. Columns 2 to 16 402 show the individual input signal components for DAC cells 1 to 15. The last column 404 shows the sum of the addition of the signal components for DAC cells 1 to 15. For the maximum code of 15 (reference sign 406) all positive current sources are connected to the positive output. The Sum of the currents is 15. For a code of 14 (reference sign 408) only 14 positive current sources and 1 negative current source are con nected to the positive output. Therefore 1 of the positive currents is compensated by a negative current, resulting only in 13 effective currents at the output, and so on. In contrast to Fig. 3c where the selected DAC cells have been identical for a given input code, now only the number of selected DAC cells might be identical, but the position of the cells may depend on the last input code. The connected DAC cells may start with the next position compared to the previous selected cells. This pointer might rotate from cell 15 down to cell 1 in this example and might continue from cell 15, and so on. The example shows an example of selected cells for decreasing DAC input code from 15 to 0.

Fortunately, the“Ones” and the“Minus Ones” in this representation are still successional, assuming pointer rotation from Cell 15 to CellO. This property might be used for efficient generation of dumping codes for this signal representation.

Fig. 4b shows an exemplary dumping switching scheme of a Multi-bit differential DAC driven by a VCO type ADC (e.g. the Delta-Sigma-modulator 1000). The switching scheme of at least some examples may be shown in Fig. 4b. In the first column 410, the input code is shown. Columns 2 to 16 412 show the individual input signal components for DAC cells 1 to 15. The last column 414 shows the sum of the addition of the signal components for DAC cells 1 to 15.

In the example, each time 15 operations may be performed (e.g. by the conversion circuitry 10) in order to find out which of the cells can be dumped. The logical operation of at least some examples is the following:

If Cell 1 and Cell9 cancel out ((Cell 1=1 Cell9=-1) OR (Celll=-1 Cell9=l) ) dump Celll .

If Cell2 and CelllO cancel out ((Cell2=l Cell 10=- 1) OR (Cell2=-1 Cell 10=1) ) dump Cell2.

If Cell7 and Cell 15 cancel out ((Cell7=l Cell 15=- 1) OR (Cell7=-1 Celll 5=1) ) dump Cell7. If Cell8 and Celll cancel out ((Cell8=l Cell 1=-1) OR (Cell8=-1 Celll=l) ) dump Cell8.

If Cell 15 and Cell8 cancel out ((Cell 15=1 Cell8=-1) OR (Cell 15=- 1 Cell8=l) ) dump Cell 15.

The dumping may be done by pairwise comparison (e.g. the plurality of pairwise compari sons) of fixed cell pairs (e.g. the first and second binary values) with a constant offset (e.g. the offset between the first binary value and the second binary value), which may be realized by fast XOR logic gates. In case the DAC based ADC has an even number of cells the logic might be further simplified. In this case, two DAC cells might be dumped for each XOR operation. E.g. for a 16 cell DAC it may result in the following logic:

If Cell 1 and Cell9 cancel out ((Cell 1=1 Cell9=-1) OR (Cell 1=-1 Cell9=l) ) dump Cell 1 and Cell9.

If Cell2 and Cell 10 cancel out ((Cell2=l Cell 10=- 1) OR (Cell2=-1 Cell 10=1) ) dump Cell2 and Cell 10 .

If Cell8 and Cell 16 cancel out ((Cell8=l Cell 16=- 1) OR (Cell8=-1 Cell 16=1) ) dump Cell8 and Cell 16.

In the example, each time 8 operations might be performed.

More details and aspects of examples are mentioned in connection with the proposed concept or one or more examples described above (e.g. Fig. la to 2b). The examples may comprise one or more additional optional features corresponding to one or more aspects of the proposed concept or one or more examples described above or below.

The aspects and features mentioned and described together with one or more of the previously detailed examples and figures, may as well be combined with one or more of the other exam ples in order to replace a like feature of the other example or in order to additionally introduce the feature to the other example.

Example 1 relates to a conversion circuitry 10 for converting a thermometer-coded input sig nal with a logical sequence of n binary values into an output signal with n ternary values, wherein the output signal is operable (i.e. suitable) for n digital to analog converter units 20 of a digital to analog conversion circuit 100, wherein the conversion circuitry 10 is configured to generate the output signal based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values, wherein an offset between a first bi nary value and a second binary value is the same for the plurality of pairwise comparisons based on the logical sequence of n binary values. In example 2, the subject matter of example 1 or any of the Examples described herein may further include, that the offset between the first binary value and the second binary value is the ceiling function of -

In example 3, the subject matter of one of the previous Examples or any of the Examples described herein may further include, that n is an odd number, wherein the plurality of pair wise comparisons correspond to n pairwise comparisons, wherein the n pairwise compari sons are performed in parallel.

In example 4, the subject matter of example 2 or any of the Examples described herein may further include, that n is an even number, and wherein the offset between the first binary value and the second binary value is -

In example 5, the subject matter of example 4 or any of the Examples described herein may

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further include, that the plurality of pairwise comparisons correspond to - pairwise compari-

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sons, wherein the - pairwise comparisons are performed in parallel.

In example 6, the subject matter of one of the examples 1 to 5 or any of the Examples de scribed herein may further include, that the n ternary values correspond to a positive value, a negative value and a neutral value.

In example 7, the subject matter of example 6 or any of the Examples described herein may further include, that the n binary values are represented by a first value and a second value, wherein the conversion circuitry 10 is configured to determine, whether the first binary value and the second binary value are unequal values, wherein the conversion circuitry 10 is con figured to generate a neutral value for the ternary value of the n ternary values corresponding to the first binary value or to the second binary value if the first binary value and the second binary value are unequal values.

In example 8, the subject matter of example 7 or any of the Examples described herein may further include, that n is an even number, and wherein the offset between the first binary value and the second binary value is - wherein - pairwise comparisons are performed, wherein the conversion circuitry 10 is configured to generate a neutral value for the ternary value of the n ternary values corresponding to the first binary value and to the second binary value if the first binary value and the second binary value are unequal values.

In example 9, the subject matter of example 7 or any of the Examples described herein may further include, that n is an odd number, and wherein the offset between the first binary value and the second binary value is the ceiling function of- wherein the plurality of pairwise comparisons correspond to n pairwise comparisons, wherein the conversion circuitry 10 is configured to generate a neutral value for the ternary value of the n ternary values correspond ing either to the first binary value or to the second binary value if the first binary value and the second binary value are unequal values.

In example 10, the subject matter of one of the examples 1 to 9 or any of the Examples de scribed herein may further include, that the thermometer-coded input signal is a thermometer- coded input signal with a variable starting position of the thermometer code.

In example 11, the subject matter of one of the examples 1 to 10 or any of the Examples described herein may further include, that the offset between the first binary value and the second binary value wraps around at the end of the logical sequence of n binary values.

In example 12, the subject matter of one of the examples 1 to 11 or any of the Examples described herein may further include, that the conversion circuitry 10 includes one or more inputs 12 configured to obtain the input signal from a voltage-controlled oscillator-based quantizer.

In example 13, the subject matter of one of the examples 1 to 12 or any of the Examples described herein may further include, that the conversion circuitry 10 includes one or more outputs 14 configured to provide the output signal to the n digital to analog converter units 20 of the digital to analog conversion circuit 100.

In example 14, the subject matter of one of the examples 1 to 13 or any of the Examples described herein may further include, that the output signal is operable/suitable for n digital to analog converter units 20 of a digital to analog conversion circuit 100 of a Delta-Sigma- modulator 1000. Example 15 relates to a Delta-Sigma-modulator 1000 including the conversion circuitry 10 according to one of the examples 1 to 14 or any of the Examples described herein.

In example 16, the subject matter of example 15 or any of the Examples described herein may further include a voltage-controlled oscillator-based quantizer 30, wherein the voltage-con trolled oscillator-based quantizer is configured to provide the input signal to the conversion circuitry 10.

In example 17, the subject matter of one of the examples 15 or 16 or any of the Examples described herein may further include a digital to analog conversion circuit 100, wherein the digital to analog conversion circuit 100 includes n digital to analog converter units 20, wherein the conversion circuitry 10 is configured to provide the output signal to the n digital to analog converter units 20 of the digital to analog conversion circuit 100.

Example 18 relates to a digital to analog conversion circuit 100 including n digital to analog converter units 20 and the conversion circuitry 10 according to one of the examples 1 to 15, wherein the conversion circuitry 10 is configured to provide the output signal to the n digital to analog converter units 20 of the digital to analog conversion circuit 100.

Example 19 relates to a mobile device including the Delta-Sigma-modulator 1000 according to one of the examples 15 to 17 or any of the Examples described herein.

Example 20 relates to a communication device including the Delta-Sigma-modulator 1000 according to one of the examples 15 to 17 or any of the Examples described herein.

Example 21 relates to a base station transceiver including the Delta-Sigma-modulator 1000 according to one of the examples 15 to 17 or any of the Examples described herein.

Example 22 relates to a means for converting 10, suitable for converting a thermometer-coded input signal with a logical sequence of n binary values into an output signal with n ternary values, wherein the output signal is operable for n digital to analog converter units 20 of a digital to analog conversion means 100, wherein the means for converting 10 is configured for generating the output signal based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values, wherein an offset between a first binary value and a second binary value is the same for the plurality of pairwise compar isons based on the logical sequence of n binary values.

In example 23, the subject matter of example 22 or any of the Examples described herein may further include, that the offset between the first binary value and the second binary value is the ceiling function of -

In example 24, the subject matter of one of the examples 22 or 23 or any of the Examples described herein may further include, that n is an odd number, wherein the plurality of pair wise comparisons correspond to n pairwise comparisons, wherein the n pairwise compari sons are performed in parallel.

In example 25, the subject matter of example 24 or any of the Examples described herein may further include, that n is an even number, and wherein the offset between the first binary value and the second binary value is -

In example 26, the subject matter of example 25 or any of the Examples described herein may

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further include, that the plurality of pairwise comparisons correspond to - pairwise compari-

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sons, wherein the - pairwise comparisons are performed in parallel.

In example 27, the subject matter of one of the examples 22 to 26 or any of the Examples described herein may further include, that the n ternary values correspond to a positive value, a negative value and a neutral value.

In example 28, the subject matter of example 27 or any of the Examples described herein may further include, that the n binary values are represented by a first value and a second value, wherein the means for converting 10 is configured for determining, whether the first binary value and the second binary value are unequal values, wherein the means for converting 10 is configured for generating a neutral value for the ternary value of the n ternary values corre sponding to the first binary value or to the second binary value if the first binary value and the second binary value are unequal values. In example 29, the subject matter of example 28 or any of the Examples described herein may further include, that n is an even number, and wherein the offset between the first binary value and the second binary value is - wherein - pairwise comparisons are performed, wherein the means for converting 10 is configured for generating a neutral value for the ternary value of the n ternary values corresponding to the first binary value and to the second binary value if the first binary value and the second binary value are unequal values.

In example 30, the subject matter of example 28 or any of the Examples described herein may further include, that n is an odd number, and wherein the offset between the first binary value and the second binary value is the ceiling function of- wherein the plurality of pairwise comparisons correspond to n pairwise comparisons, wherein the means for converting 10 is configured for generating a neutral value for the ternary value of the n ternary values corre sponding either to the first binary value or to the second binary value if the first binary value and the second binary value are unequal values.

In example 31, the subject matter of one of the examples 22 to 30 or any of the Examples described herein may further include, that the thermometer-coded input signal is a thermom eter-coded input signal with a variable starting position of the thermometer code.

In example 32, the subject matter of one of the examples 22 to 31 or any of the Examples described herein may further include, that the offset between the first binary value and the second binary value wraps around at the end of the logical sequence of n binary values.

In example 33, the subject matter of one of the examples 22 to 32 or any of the Examples described herein may further include, that the means for converting 10 includes one or more input means 12 configured for obtaining the input signal from a voltage-controlled oscillator- based quantizer.

In example 34, the subject matter of one of the examples 22 to 33 or any of the Examples described herein may further include, that the means for converting 10 includes one or more output means 12 configured for providing the output signal to n digital the analog converter units 20 of the digital to analog conversion means 100. In example 35, the subject matter of one of the examples 22 to 34 or any of the Examples described herein may further include, that the output signal is operable for n digital to analog converter units 20 of a digital to analog conversion means 100 of a Delta-Sigma-modulation means 1000.

Example 36 relates to a Delta-Sigma-modulation means 1000 including the means for con verting 10 according to one of the examples 22 to 35 or any of the Examples described herein.

In example 37, the subject matter of example 36 further includes a voltage-controlled oscilla tor-based quantizing means 30, wherein the voltage-controlled oscillator-based quantizing means 30 is configured for providing the input signal to the means for converting 10.

In example 38, the subject matter of one of the examples 36 or 37 further includes a digital to analog conversion means 100, wherein the digital to analog conversion means 100 includes n digital to analog converter units 20, wherein the means for converting 10 is configured for providing the output signal to the n digital to analog converter units 20 of the digital to analog conversion means 100.

Example 39 relates to a digital to analog conversion means 100 including n digital to analog converter units 20 and the means for converting 10 according to one of the examples 22 to 35, wherein the means for converting 10 is configured for providing the output signal to the n digital to analog converter units 20 of the digital to analog conversion means 100.

Example 40 relates to a mobile device including the Delta-Sigma-modulation means 1000 according to one of the examples 36 to 38 or any of the Examples described herein.

Example 41 relates to a communication device including the Delta-Sigma-modulation means 1000 according to one of the examples 36 to 38 or any of the Examples described herein.

Example 42 relates to a base station transceiver including the Delta-Sigma-modulation means 1000 according to one of the examples 36 to 38 or any of the Examples described herein. Example 43 relates to a conversion method, suitable for converting a thermometer-coded in put signal with a logical sequence of n binary values into an output signal with n ternary val ues, wherein the output signal is operable for n digital to analog converter units 20 of a digital to analog conversion means 100, wherein the conversion method includes generating 120 the output signal based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values, wherein an offset between a first binary value and a second binary value is the same for the plurality of pairwise comparisons based on the logical sequence of n binary values.

In example 44, the subject matter of example 43 or any of the Examples described herein may further include, that the offset between the first binary value and the second binary value is the ceiling function of -

In example 45, the subject matter of one of the examples 43 or 44 or any of the Examples described herein may further include, that n is an odd number, wherein the plurality of pair wise comparisons correspond to n pairwise comparisons, wherein the n pairwise compari sons are performed in parallel.

In example 46, the subject matter of example 45 or any of the Examples described herein may further include, that n is an even number, and wherein the offset between the first binary value and the second binary value is -

In example 47, the subject matter of example 46 or any of the Examples described herein may

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further include, that the plurality of pairwise comparisons correspond to - pairwise compari-

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sons, wherein the - pairwise comparisons are performed in parallel.

In example 48, the subject matter of one of the examples 43 to 47 or any of the Examples described herein may further include, that the n ternary values correspond to a positive value, a negative value and a neutral value.

In example 49, the subject matter of example 48 or any of the Examples described herein may further include, that the n binary values are represented by a first value and a second value, wherein the conversion method includes determining 122, whether the first binary value and the second binary value are unequal values, wherein the conversion method includes gener ating 124 a neutral value for the ternary value of the n ternary values corresponding to the first binary value or to the second binary value if the first binary value and the second binary value are unequal values.

In example 50, the subject matter of example 7 or any of the Examples described herein may further include, that n is an even number, and wherein the offset between the first binary value and the second binary value is - wherein - pairwise comparisons are performed, wherein the conversion method includes generating 124 a neutral value for the ternary value of the n ter nary values corresponding to the first binary value and to the second binary value if the first binary value and the second binary value are unequal values.

In example 51, the subject matter of example 48 or any of the Examples described herein may further include, that n is an odd number, and wherein the offset between the first binary value and the second binary value is the ceiling function of- wherein the plurality of pairwise comparisons correspond to n pairwise comparisons, wherein the conversion method includes generating 124 a neutral value for the ternary value of the n ternary values corresponding either to the first binary value or to the second binary value if the first binary value and the second binary value are unequal values.

In example 52, the subject matter of one of the examples 43 to 51 or any of the Examples described herein may further include, that the thermometer-coded input signal is a thermom eter-coded input signal with a variable starting position of the thermometer code.

In example 53, the subject matter of one of the examples 43 to 52 or any of the Examples described herein may further include, that the offset between the first binary value and the second binary value wraps around at the end of the logical sequence of n binary values.

In example 54, the subject matter of one of the examples 43 to 53 or any of the Examples described herein may further include, that the conversion method includes obtaining 110 the input signal from a voltage-controlled oscillator-based quantizing means.

In example 55, the subject matter of one of the examples 43 to 54 or any of the Examples described herein may further include, that the conversion method includes providing 130 the output signal to n digital the analog converter units 20 of the digital to analog conversion means 100.

In example 56, the subject matter of one of the examples 43 to 55 or any of the Examples described herein may further include, that the output signal is operable for n digital to analog converter units 20 of a digital to analog conversion means 100 of a Delta-Sigma-modulation means 1000.

Examples may further be or relate to a computer program having a program code for perform ing one or more of the above methods, when the computer program is executed on a computer or processor. Steps, operations or processes of various above-described methods may be per formed by programmed computers or processors. Examples may also cover program storage devices such as digital data storage media, which are machine, processor or computer readable and encode machine-executable, processor-executable or computer-executable programs of instructions. The instructions perform or cause performing some or all of the acts of the above- described methods. The program storage devices may comprise or be, for instance, digital memories, magnetic storage media such as magnetic disks and magnetic tapes, hard drives, or optically readable digital data storage media. Further examples may also cover computers, processors or control units programmed to perform the acts of the above-described methods or (field) programmable logic arrays ((F)PLAs) or (field) programmable gate arrays ((F)PGAs), programmed to perform the acts of the above-described methods.

The description and drawings merely illustrate the principles of the disclosure. Furthermore, all examples recited herein are principally intended expressly to be only for illustrative pur poses to aid the reader in understanding the principles of the disclosure and the concepts con tributed by the inventor(s) to furthering the art. All statements herein reciting principles, as pects, and examples of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.

A functional block denoted as“means for ...” performing a certain function may refer to a circuit that is configured to perform a certain function. Hence, a“means for s.th.” may be implemented as a“means configured to or suited for s.th.”, such as a device or a circuit con figured to or suited for the respective task. Functions of various elements shown in the figures, including any functional blocks labeled as“means”,“means for providing a signal”,“means for generating a signal.”, etc., may be implemented in the form of dedicated hardware, such as“a signal provider”,“a signal pro cessing unit”,“a processor”,“a controller”, etc. as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the func tions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which or all of which may be shared. However, the term“processor” or“controller” is by far not limited to hardware exclusively capable of executing software, but may include digital signal processor (DSP) hardware, network pro cessor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage. Other hardware, conventional and/or custom, may also be included.

A block diagram may, for instance, illustrate a high-level circuit diagram implementing the principles of the disclosure. Similarly, a flow chart, a flow diagram, a state transition diagram, a pseudo code, and the like may represent various processes, operations or steps, which may, for instance, be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. Meth ods disclosed in the specification or in the claims may be implemented by a device having means for performing each of the respective acts of these methods.

It is to be understood that the disclosure of multiple acts, processes, operations, steps or func tions disclosed in the specification or claims may not be construed as to be within the specific order, unless explicitly or implicitly stated otherwise, for instance for technical reasons. Therefore, the disclosure of multiple acts or functions will not limit these to a particular order unless such acts or functions are not interchangeable for technical reasons. Furthermore, in some examples a single act, function, process, operation or step may include or may be broken into multiple sub-acts, -functions, -processes, -operations or -steps, respectively. Such sub acts may be included and part of the disclosure of this single act unless explicitly excluded.

Furthermore, the following claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. While each claim may stand on its own as a separate example, it is to be noted that - although a dependent claim may refer in the claims to a specific combination with one or more other claims - other examples may also include a combination of the dependent claim with the subject matter of each other de pendent or independent claim. Such combinations are explicitly proposed herein unless it is stated that a specific combination is not intended. Furthermore, it is intended to include also features of a claim to any other independent claim even if this claim is not directly made dependent to the independent claim.