CASTILLE KYLE (US)
AN QUANG-DIEU (US)
AGARWALA SANJIVE (US)
CASTILLE KYLE (US)
AN QUANG-DIEU (US)
| US6681270B1 | 2004-01-20 | |||
| US5898895A | 1999-04-27 | |||
| US3491341A | 1970-01-20 | |||
| US4748588A | 1988-05-31 |
CLAIMS
1. A method for data transfer between selected a source and destination pair of a plurality of ports comprising the steps of: sending a source read request to a specified source port of said plurality of ports; receiving read data from said source port; storing received read data in a buffer memory; sending a destination write request to a specified destination port of said plurality of ports; receiving a read response signal from said source port in response to said read request; issuing a new read request to said source port upon receipt of said read response and before receiving read data in response to a prior read request; and issuing a write request to a write port sending recalled data from said buffer memory.
2. The transfer method of Claim 1 , wherein: assigning each source read request a channel and a priority; and issuing a new read request to a read port regardless of pending transfer and priority if said read buffer memory has storage capacity.
3. The transfer method of Claim 1, wherein: storing read data from plural channels in said buffer memory.
4. The transfer method of Claim 1 , wherein: storing read responses from plural read ports in said buffer memory; matching stored read responses to corresponding write requests; directing said stored read data from said buffer memory to a write data buffer for the corresponding destination channel.
5. The transfer method of Claim 4, wherein: tracking empty space in said write data buffer by adding to a space count when data is stored in said write data buffer and subtracting from said space count when data is transferred from said write data buffer to said write port.
6. A data transfer controller comprising: a plurality of data ports, a first plurality of said data ports capable of supplying read data in response to a data read request and a second plurality of said data port capable of storing write data in response to a write request; a plurality of channel parameter registers, each storing fixed parameters of a corresponding data transfer channel; a plurality of port parameter regitsers, each storing fixed parameters of a corresponding one of said plurality of data ports; a plurality of channel registers, each storing parameters variable parameters of a corresponding data transfer channel; a source pipeline operable to generate a read request for read data from one of said first plurality of data ports according to an assigned channel; a write data buffer connected to said first plurality of data ports for storing read data returned from one of said first plurality of data ports in response to a read request; a read response buffer connected to said first plurality of data ports for storing read responses returned from one of said first plurality of data ports in response to a read request; a destination pipeline connected to said write data buffer and said read response buffer operable to generate a write request to request a write of data stored in said write data buffer to one of said second plurality of data ports according to an assigned channel; and a request queue manager connected to said channel parameter registers, said port parameter registers, said channel registers, said source pipeline and said destination pipeline, said request queue manager operable to store and prioritize received data transfer requests, issue stored data transfer requests to open channels by separately assigning a corresponding read request to said source pipeline and a corresponding write request to said destination pipeline, including issuing a new read request upon receipt of a read response to a prior read request.
7. The data transfer controller of Claim 6, wherein: said request queue manager is further operable to assign a channel and a priority to each source read request, and issue a new read request to a read port regardless of any pending transfer and priority if said write buffer has storage capacity.
8. The data transfer controller of Claim 6, wherein: said buffer memory element stores read data from plural channels.
9. The date transfer controller of Claim 6, wherein: said request queue manager is further operable to direct read responses from plural read ports to direct read data from plural read ports to said write data buffer for corresponding destination channels.
10. The data transfer controller of Claim 9, wherein: said write data buffer includes a counter tracking empty space in said write data buffer, said counter adding to a count stored therein upon storage of additional data stored and subtracting from a count upon data transfer of data from said write data buffer to said write port. |
CONCURRENT READ RESPONSE ACKNOWLEDGE
ENHANCED DIRECT MEMORY ACCESS UNIT
This invention relates to direct memory access units in data processing devices. BACKGROUND Current microprocessor designs need to centralize data transfer operations under control of integrated functional units known as data transfer access units or enhanced direct memory access (EDMA) units. EDMA is of most interest here and specifically of interest are EDMA designs employing hub-and-port style architecture. Such EDMAs feature a hub unit, which maintains a queue of transfer requests and provides priority protocol and proper interfacing for the handling of a large number of such requests. Secondly hub-and-port
EDMAs have one or more hub interface units (HIU), which each provide a seamless interface between the EDMA hub and its ports. Ports are typically external application units (AU) otherwise known as peripheral units. Internal memory ports are also included among the EDMA ports. FIG. 1 illustrates the essentials of a microprocessor system having EDMA 100 and central processing unit (CPU) 101. EDMA 100 includes transfer controller 102 and hub interface units (HIU) 104, 105, and 106. Communication between the transfer controller hub unit 102 and HIUs 104, 105, and 106 employs buses 103, 107, 108, 109, and 110. Each HIU provides interface to a single port. Peripheral unit 114 and 115 communication with corresponding HIUs 104 and 105 via respective paths 111 and 112. Each EDMA port also includes the internal memory port device 116 which communications with HIU 106 via path 113. The EDMA 100 responds to transfer requests not only from CPU 101 but also from any of the ports it services. Transfer requests (TR) handled by transfer controller (TC) hub unit 102 involve transfer of data from one port to another. Transfer commands reside in transfer request packets that give all the detailed parameters of a transfer.
FIG. 2 illustrates the functional units of the transfer controller portion of EDMA 200. The transfer request processor 201 receives transfer requests from CPU 230 and from one or more HIU 210 via path 228. Transfer request processor passes these requests to queue manager 202. Queue manager 202 receives data transfer request packets (TRP), places them in queue manager RAM 203 and assigns them to one of the P channel priority levels. It is
helpful to distinguish TRPs stored in the queue manager RAM 203 as being in the queue, and TRPs stored in the channel registers block 204 as being active. For example, for N=32, EDMA 200 could have four channel priorities and channel register block 204 could hold eight active transfer packets at each priority level. At any given time channel register block 204 could hold up to 32 total TRPs.
If there is no channel available for direct processing of a TRP coming into queue manager 202, it is stored in queue manager random access memory (RAM) 203. The TRP is then submitted to the channel registers 204 at a later time when a channel becomes available. Source ready signal 213 and destination ready signal 215 indicate availability of a channel space within the channel registers 204. Channel registers 204 interface with source pipeline 205 and destination pipeline 206. Source pipeline 205 and destination pipeline 206 are address calculation units for source (read) and destination (write) operations. These pipelines broadcast outputs to M ports of EDMA 200 through M hub interface units 210, which drive the M possible external ports units. FIG. 2 illustrates just one port 229 as an example. When source pipeline space is available, source pipeline 204 passes source ready signal 216 to the channel registers 204, which passes source ready signal 213 to queue manager 202. When destination pipeline space is available, destination pipeline 206 passes ready signal 219 to the channel registers 204, which passes ready signal 215 to queue manager 202. Queue manager block 202 passes source read commands developed from the transfer packets to channel registers 204 via path 214 and hence to source pipeline 205 via path 217. Queue manager block 202 passes destination write commands developed from the transfer packets to channel registers 204 via path 214 and hence to destination pipeline 205 via path 220. Source valid signal 218 and destination valid signal 221 from channel registers 204 alert the respective pipelines that a valid transfer is ready to be processed. Signals broadcast from transfer controller (TC) to the hub interface units (HIU) 210 and returning from the HIU to the TC include: source read command 222; destination write command 223; destination write data 224; read response information 227 from HIU to read response FIFO buffer 212; read return data from ports 225 to be stored in write data first- in first-out (FIFO) buffer 211; TC acknowledge flag 226 from response acknowledge logic 209 to HIU 210.
SUMMARY
The enhanced direct memory access (EDMA) operation of this invention provides an enhancement feature of earlier EDMA devices. In the invention, EDMA issues a read command to the source port to request data. The port returns the data along with response information, which contains the channel and valid byte count. The EDMA stores the read data into the write buffer and acknowledges to the source port to inform that the EDMA can accept more data. The read response and data can come from more than one port and belong to different channels. Formerly, the EDMA would prioritize the processing channels and only the channel with the highest priority could be processed. All the other pending channels would wait, which results in idling the ports, which already have data ready to send back to the EDMA. Removing channel prioritizing according to this invention allows the EDMA to store read data in the write buffer the EDMA then can acknowledge the port read response concurrently across all channels and this improves the EDMA inbound and outbound data flow dramatically. BRIEF DESCRIPTION OF THE DRAWINGS
These and other aspects of this invention are illustrated in the drawings, in which: FIG. 1 (Prior Art) illustrates the high level functional diagram of an enhanced direct memory access unit (EDMA) with hub-and-port architecture driven by a central processor unit and having a transfer controller interfacing with several hub interface units driving peripheral unit functions;
FIG. 2 (Prior Art) illustrates in a functional block diagram the basic principal features of the EDMA;
FIG. 3 illustrates the queue manager interface to the EDMA source and destination pipelines; and FIG. 4 illustrates the block diagram of the concurrent read response acknowledge
EDMA of this invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
FIG. 3 illustrates the queue manager 300 and its interface to the EDMA hub unit boundaiy and particularly the queue manager communications with channel registers 315, channel parameter registers 301 and port parameter registers 302. Channel parameters
registers 301 and port parameters registers 302 store critical data regarding for example, types of transfers, mode information, status, and much other information critical to the transfer process.
Channel registers 315 pass information used in source pipeline 305 for generation of read commands 322. Similarly channel registers 315 pass information used in destination pipeline 306 for generation of write command 324 directing passage of write data 323 to the HIU. Read response information 327 from the ports is returned to destination pipeline 306 via data router unit 310. Data router unit 310 includes the two FIFOs : write data FIFO buffer 311; and read response FIFO buffer 312. Response acknowledge logic 309 supplies response acknowledge signal 326 to the HIU indicating the data read has been received.
If a channel in the EDMA is idle and the queue manager 300 has another EDMA entry for that channel, then it reads out the transfer request packet via path 320 for that transfer and sends it to channel registers 315. This information is saved, and that channel is activated inside the EDMA, to begin transferring data. During the transfer, source pipeline 305 and destination pipeline 306 incrementally modify some of the transfer parameters, and channel registers 315 handle updating channel parameter registers 301 and port parameters registers 302. Source pipeline 305 and destination pipeline 306 then send out updated values to the rest of the EDMA. Once the EDMA finishes processing that channel, channel registers 315 will generate a source ready signal 318 or a destination ready signal 319. Queue manager 300 detects completion of a transfer and sends another request to channel registers 315.
Consider the example extended direct memory access (EDMA) unit illustrated in FIG. 3. This example EDMA has eight priority channels and four ports, hi typical operation, once a read command has been executed no additional read commands can be executed until the corresponding write operations have been concluded. The EDMA delays additional reads until the completion of the pending write. The concurrent read response EDMA of this invention eliminates this limit on the flow of read data to the EDMA.
The concurrent read response acknowledge enhanced DMA of this invention accepts the read response and data from the source ports concurrently across all channels. As long as the EDMA write buffer has enough space, the source port can always return data whenever
ready. The source port buffer is not be blocked and the EDMA can write the data to the destination port in real time. Utilization of the EDMA bandwidth is maximized.
The invention operates on this sequence. The EDMA issues read command to a source port A to request data. Port A returns the data along with response information. This response information contains the channel and valid byte count. The EDMA stores the read data in the write buffer and acknowledges to the source ports that the EDMA can accept more data. The read response and data can now come from more than one port and belong to different channels. The EDMA prioritizes the processing channels and only the channel with highest priority can proceed. All the other pending channels await which results in idling the ports, which already have data ready to send back to EDMA. Removing channel prioritizing according to this invention allows the EDMA to store additional read data from other channels in the write buffer. The EDMA can then acknowledge to multiple ports and receive read response concurrently across all channels. This improves the EDMA inbound and outbound data flow dramatically. FIG. 4 illustrates the concurrent read response acknowledge of this invention. Port read response 401 from a specific source port (e.g. source port A) containing the channel and valid data byte information for a specific transfer is stored in read response FIFO buffer 402. The EDMA then generates an acknowledge (ACK) signal 403 back to port A signifying that the data will in fact be processed. In order to process a new response every cycle, multiple three-entry read response
FIFOs are provided for each port. The EDMA meanwhile receives a source port valid signal 410 for a given channel and combines this information with the channel number from the read response. The EDMA generates a source ready 411 to determine which channel has read data ready to be processed. Read data 420 from all the ports are multiplexed in data multiplexer 416 to retrieve the data 418 from the responding port for that channel. This data 418 is input to the write data FIFO buffer 404.
Each channel has its own write data FIFO buffer 417. Write pointer 421 identifies the buffer location to be updated and read pointer 407 points to the data to be output to the destination port 419. Write buffer space counter 408 keeps track of the empty space in write data FIFO buffer 404 that is available for additional stored data. The write buffer space
counter 408 is updated by: (1) adding the number of bytes written into the buffer; and (2) subtracting by the number of bytes output to the destination port 419. Response acknowledge logic block 406 compares write buffer space counter 408 value with byte count of the port read response. If there is enough space, response acknowledge logic 406 issues a response acknowledge 403 to the source port. The source port in turn can send another read response back if available.
By providing additional write data FIFO buffers 417 one for each channel and additional read response FIFO buffers 402, one for each port the bottleneck in data throughput is greatly relieved. Multiple reads may be processed even before the corresponding pending writes have been completed.