FIELD

Embodiments as described herein relate to a field of electronic device manufacturing, and in particular, to fin based electronic devices manufacturing.

BACKGROUND

Generally, in a fin based transistor architecture (e.g., FinFET, Trigate, Gate- Ail-Around (GAA)), a transistor channel is surrounded by one or more gates on multiple surfaces that increases electrical control over the channel. Typically, a non-planar transistor has a transistor channel formed on a fin on a substrate.

Typically, in modern integrated circuits silicon is used to build transistors. Silicon, however, has some limitations that may affect the device performance. Many techniques have been developed to manufacture transistors comprising non-Si materials, e.g., Ge, silicon germanium (SiGe), or III-V materials on a silicon substrate.

Germanium (Ge) layers grown on a silicon (Si) substrate can be used to fabricate electronic devices to increase mobility of the charge carriers as compared to Si. The large lattice mismatch of about 4 % between Ge and Si, however, causes formation of defects (e.g., misfit and threading dislocations, threading segments, and other defects) in the Ge layer. Generally, the defects in the Ge layer reduce the carrier mobility, increase current leakage and signal noise that adversely affects the quality and performance of the electronic devices.

Typically, conventional techniques use a SiGe layer as a buffer layer between a Ge layer and a Si substrate to reduce the adverse effects of the lattice mismatch. Conventional techniques, however, cannot control strain in the Ge layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention may be best understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:

Figure 1 is a cross-sectional view of an electronic device structure to provide strain control according to one embodiment.

Figure 2 is a view similar to Figure 1 after a subfin layer is deposited according to one embodiment. Figure 3 is a view similar to Figure 2 after a fin layer is deposited on the subfin layer according to one embodiment.

Figure 4 is a view similar to Figure 3, after a portion of insulating layer is recessed and a capping layer is deposited according to one embodiment.

Figure 5 is a view similar to Figure 4, after a portion of the insulating layer is recessed to expose the subfin portion according to one embodiment.

Figure 6 is a view similar to Figure 5, illustrating an annealing of the exposed subfin portion in an oxygen environment according to one embodiment.

Figure 7 is a view similar to Figure 6, after depositing an insulating layer on the condensed subfin portion, removing the capping layer and depositing a gate electrode layer on a gate dielectric layer on the fin portion according to one embodiment.

Figure 8 is a view similar to Figure 7, after a protective layer is deposited on the fin, and a gate electrode layer is deposited on a gate dielectric layer on another fin portion according to one embodiment.

Figure 9 is a view 900 similar to Figure 8, after the protective layer is removed according to one embodiment.

Figure 10 is a perspective view of the electronic device structure according to one embodiment.

Figure 11 illustrates an interposer that includes one or more embodiments of the invention.

Figure 12 illustrates a computing device in accordance with one embodiment of the invention.

DETAILED DESCRIPTION

Methods and apparatuses to provide condensation for strain control are described.

In one embodiment, a fin is disposed on a substrate. The fin comprises a fin portion on a subfin portion. The fin portion of the fin comprises a first semiconductor material. The subfin portion of the fin comprises a second semiconductor material that is condensed. The subfin portion of the fin has a width smaller than a width of the fin portion. In one embodiment, the first

semiconductor material is germanium, and the second semiconductor material is silicon germanium. In another embodiment, the first semiconductor material is silicon germanium and the second semiconductor material is silicon germanium. A concentration of germanium in the first semiconductor material is greater than a concentration of germanium in the second semiconductor material. In one embodiment, the subfin portion comprises edge portions and a middle portion between the edge portions. A concentration of germanium in at least one of the edge portions of the subfin portion is greater than a concentration of germanium in the middle portion of the subfin portion.

In one embodiment, a strained Ge fin is deposited on a SiGe subfin. A protective layer is deposited on the strained Ge fin to expose the SiGe subfin to oxydation. A condensation approach is used for the SiGe subfin to control the amount of stress in the Ge fin. The Ge condensation in the exposed SiGe subfin caused by oxidation changes the amount of Ge in the SiGe subfin that in turn changes the amount of stress in the Ge fin. In one embodiment, the amount of strain on the Ge fins is selectively changed by changing the amount of Ge in the SiGe subfins using a condensation technique, as described in further detail below. In one embodiment, as the condensation consumes a portion of the SiGe subfin, the width of the SiGe subfin is reduced relative to the Ge fin deposited thereon. In one embodiment, as the condensation consumes some amount of the SiGe in the SiGe subfin that is underneath the Ge fin, the amount of SiGe in the SiGe subfin that has been subjected to condensation is smaller than the amount of SiGe in the SiGe subfin that has not been subjected to condensation.

Generally, to enhance hole mobility the Ge fins for the p-type metal oxide semiconductor (PMOS) transistor devices have higher strain than that of the Ge fins for n-type metal oxide semiconductor (NMOS) transistor devices. In one embodiment, Ge fins having substantially similar stress are formed on SiGe subfins on a substrate, and the strain of one set of the Ge fins is selectively reduced using a condensation technique to enhance electron mobility for the NMOS transistor devices, while the strain of the other set of the Ge fins is not reduced to maintain enhanced hole mobility for PMOS transistor devices, as described in further detail below.

In one embodiment, a condensation technique is used to selectively decrease the amount of strain in a group of the Ge fins by increasing the amount of Ge in the respective SiGe subfins.

Conventional techniques use different raised source/drain stressors or change the composition of the SiGe at growth to change the amount of strain in the Ge fin based transistor devices. Currently, there are no techniques that would change the amount of strain in the Ge fin based transistor devices after growth. Embodiments described herein use the condensation techniques to control the amount of strain in the Ge fin based transistor devices.

In one embodiment, the condensation technique is used to selectively reduce stress in one or more fin based transistors while other fin based transistors are protected. In one embodiment, the condensation technique is used to tune one or more fin based transistors to a predetermined amount of strain, as described in further detail below. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations .

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention; however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

While certain exemplary embodiments are described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive, and that the embodiments are not restricted to the specific constructions and arrangements shown and described because modifications may occur to those ordinarily skilled in the art.

Reference throughout the specification to "one embodiment", "another embodiment", or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrases, such as "one embodiment" and "an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Moreover, inventive aspects lie in less than all the features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment. While the exemplary embodiments have been described herein, those skilled in the art will recognize that these exemplary embodiments can be practiced with modification and alteration as described herein. The description is thus to be regarded as illustrative rather than limiting.

Figure 1 is a cross-sectional view 100 of an electronic device structure 100 to provide strain control according to one embodiment. An insulating layer 102 is deposited on a substrate 101. A plurality of trenches, such as a trench 103 and a trench 104 are formed in the insulating layer 102 to expose portions of substrate 101. In an embodiment, the substrate 101 comprises a semiconductor material, e.g., silicon (Si). In one embodiment, substrate 101 is a monocrystalline Si substrate. In another embodiment, substrate 101 is a poly crystalline silicon substrate. In yet another embodiment, substrate 101 is an amorphous silicon substrate. In alternative

embodiments, substrate 101 includes silicon, germanium ("Ge"), silicon germanium ("SiGe"), a III-V materials based material e.g., gallium arsenide ("GaAs"), or any combination thereof.

In one embodiment, substrate 101 comprises a group IV material layer. Generally, the group IV material refers to a semiconductor material comprising one or more elements of the group IV of the periodic table, e.g., carbon (C), silicon (Si), germanium (Ge), tin (Sn), lead (Pb), or any combination thereof. In another embodiment, substrate 101 comprises a III-V material layer. Generally, the III-V material refers to a compound semiconductor material that comprises at least one of group III elements of the periodic table, e.g., boron ("B"), aluminum ("Al"), gallium ("Ga"), indium ("In"), and at least one of group V elements of the periodic table, e.g., nitrogen ("N"), phosphorus ("P"), arsenic ("As"), antimony ("Sb"), bismuth ("Bi").

In an embodiment, substrate 101 is a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise any material listed above, e.g., silicon. In various implementations, the substrate can be, e.g., an organic, a ceramic, a glass, or a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) may be built falls within the spirit and scope of embodiments of the present invention.

In one embodiment, the substrate includes one or more buffer layers to accommodate for a lattice mismatch between the substrate 101 and one or more layers above substrate 101 and to confine lattice dislocations and defects. In one embodiment, substrate 101 includes one or more metallization interconnect layers for integrated circuits. In at least some embodiments, the substrate 101 includes interconnects, for example, vias, configured to connect the metallization layers. In at least some embodiments, the substrate 101 includes electronic devices, e.g., transistors, memories, capacitors, resistors, optoelectronic devices, switches, and any other active and passive electronic devices that are separated by an electrically insulating layer, for example, an interlay er dielectric, a trench insulation layer, or any other insulating layer known to one of ordinary skill in the art of the electronic device manufacturing.

Insulating layer 102 can be any material suitable to insulate adjacent devices and prevent leakage. In one embodiment, electrically insulating layer 102 is an oxide layer, e.g., silicon dioxide, or any other electrically insulating layer determined by an electronic device design. In one embodiment, insulating layer 102 is an interlayer dielectric (ILD). In one embodiment, insulating layer 102 is a low-k dielectric that includes, but is not limited to, materials such as, e.g., silicon dioxide, silicon oxide, carbon doped oxide ("CDO"), e.g., carbon doped silicon dioxide, porous silicon dioxide, silicon nitride, or any combination thereof. In one embodiment, insulating layer 102 includes a dielectric material having k-value less than 5. In one embodiment, insulating layer 102 includes a dielectric material having k-value less than 2. In at least some embodiments, insulating layer 102 includes a nitride, oxide, a polymer, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), other electrically insulating layer determined by an electronic device design, or any combination thereof. In at least some embodiments, insulating layer 102 may include polyimide, epoxy, photodefinable materials, such as benzocyclobutene (BCB), and WPR-series materials, or spin-on-glass. In one embodiment, insulating layer 102 is a shallow trench isolation (STI) layer to provide field isolation regions that isolate one fin from other fins on substrate 101. In one embodiment, the thickness of the insulating layer 102 is at least 10 nm. In one embodiment, the thickness of the layer is in an approximate range from about 10 nm to about 2 microns (μιη).

In an embodiment, insulating layer 102 is deposited on substrate 101 using one of deposition techniques, such as but not limited to a chemical vapour deposition ("CVD"), a physical vapour deposition ("PVD"), molecular beam epitaxy ("MBE"), metalorganic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), spin-on, or other insulating layer deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the trenches are formed in the insulating layer 102 using patterning and etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

As shown in Figure 1, trench 103 has a bottom 105 and opposing sidewalls 121 and 122. In one embodiment, bottom 105 is the exposed portion of the substrate 101. Trench 203 has a depth 123 and a width 124. In one embodiment, depth 214 is determined by the thickness of the insulating layer 102. In one embodiment, the thickness of the insulating layer 102 is defined by the thickness of the subfin layer and fin layer deposited later on in a process. In an embodiment, the width of the trench 103 is determined by the width of the fin for the electronic device. The electronic device can be for example a fin based transistor architecture (e.g., FinFET, Trigate, GAA, a nanowire based device, a nanoribbons based device, or any other electronic device). In one embodiment, the width 124 of the trenches is from about 2 nanometers (nm) to about 300nm. In one embodiment, the width 124 of the trenches is from about 5 nm to about 30 nm. In an embodiment, the aspect ratio of the trench (D/W) is at least 1.5.

Figure 2 is a view 200 similar to Figure 1 after a subfin layer is deposited in the trenches according to one embodiment. As shown in Figure 2, the subfin layer includes a subfin portion 107 that is deposited within trench 103 and a subfin portion 108 that is deposited within trench 104 on the exposed portions of the substrate. As shown in Figure 2, subfin portion 107 is deposited onto the exposed portion 105 of the substrate 101 between the sidewalls of the trench 103 and subfin portion 108 is deposited onto the exposed portion 106 of the substrate 101 between the sidewalls of the trench 104.

In at least some embodiments, a buffer layer (not shown) is deposited on the exposed portions of the substrate 101 within trenches 103 and 104 underneath each of the subfin portions 107 and 108. Generally, the buffer layer is deposited to accommodate for a lattice mismatch between the substrate and one or more layers above the buffer layer and to confine lattice dislocations and defects. In an embodiment, the buffer layer has a lattice parameter between the lattice parameter of the substrate 101 and the subfin layer which is formed thereon. Generally, a lattice parameter refers to a distance between unit cells in a crystal lattice. In one embodiment, the buffer layer including the buffer layer portion that is deposited between the subfin portion 107 and exposed portion 105 of the substrate and the buffer layer portion that is deposited between the subfin portion 108 and exposed portion 106 of the substrate comprises a group IV material layer. In another embodiment, the buffer layer including the buffer layer portion that is deposited between the subfin portion 107 and exposed portion 105 of the substrate and the buffer layer portion that is between the subfin portion 108 and exposed portion 106 of the substrate comprises comprises a III-V material layer.

In an embodiment, the thickness of the buffer layer is such that most defects originated from the lattice mismatch are trapped within the buffer layer and are prevented from being propagated into the subfin layer above the buffer layer using an aspect ratio trapping (ART). In one embodiment, the thickness of the buffer layer is at least about 5 nm. In one embodiment, the thickness of the buffer layer is from about 5 nm to about 500 nm. In various embodiments the buffer layer may have different numbers of layers or simply be a single layer.

In at least some embodiments, the buffer layer is deposited through trenches 103 and 104 onto the exposed portions 105 and 106 of substrate 101 using one of selective epitaxial techniques, such as but not limited to a CVD, a PVD, MBE, MOCVD, ALD, spin-on, or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

In one embodiment, the subfin layer including the subfin portions 107 and 108 includes at least two components. In one embodiment, one of the components (e.g., a first component) of the subfin layer is a semiconductor material of the fin layer deposited thereon later on in a process, and the other one of the components (e.g., a second component) of the subfin layer is a semiconductor material that is other than the semiconductor material of the fin layer. In one embodiment, the second component of the subfin layer is a semiconductor material of the layer that is underneath the subfin layer, e.g., substrate 101, the buffer layer, or other semiconductor material.

In one embodiment, the subfin layer including the subfin portions 107 and 108 is a group IV semiconductor layer. In one embodiment, the at least two components of the subfin layers

107 and 108 are group IV semiconductors. In one embodiment, the first component of the subfin portions 107 and 108 is germanium, and the second component of the subfin portions 107 and

108 is silicon.

In one embodiment, each of the subfin portions 107 and 108 is a SiGe layer and substrate is a silicon substrate. In one embodiment, each of the subfin portions 107 and 108 is a Sii_ _x Ge _x alloy, where x is any number greater than 0 and less than 1. In more specific embodiment, each of the subfin portions 107 and 108 is a Sii_ _x Ge _x alloy, where x is from about 0.2 to about 0.8.

In another embodiment, at least one of the subfin portions 107 and 108 comprises a III-V material e.g. gallium arsenide (GaAs), gallium phosphide (GaP), aluminum arsenide (AlAs), aluminum phosphide (A1P), aluminum arsenic antimonide (AlAsSb), indium gallium arsenide (InGaAs), aluminum gallium indium phosphide (AlInGaP) or other III-V material.

In one embodiment, the thickness of each of the subfin portion 107 and subfin portion

108 is at least about 5 nanometers (nm). In one embodiment, the thickness of each of the subfin portion 107 and subfin portion 108 is from about 20 nm to about 300 nm. In more specific embodiment, the thickness of each of the subfin portion 107 and subfin portion 108 is from about 20 nm to about 250 nm. In one embodiment, the width of each of the subfin portion 107 and subfin portion 108 is from about 2 nm to about 300nm. In one embodiment, the width of each of the subfin portion 107 and subfin portion 108 is from about 5 nm to about 30 nm.

In at least some embodiments, the subfin portion 107 and subfin portion 108 are deposited to a predetermined thickness using a selective area epitaxy. In at least some embodiments, the subfin portion 107 and subfin portion 108 are locally grown directly on the exposed portions of the substrate 101 through the trenches in the insulating layer 102 to a predetermined thickness. In at least some embodiments, the subfin portion 107 and subfin portion 108 are locally grown on the buffer layer through the trenches in the insulating layer 102 to a predetermined thickness. In at least some embodiments, the subfin layer portions 108 and 109 are selectively deposited using one of epitaxial techniques, such as but not limited to a CVD, a PVD, MBE, MOCVD, ALD, spin-on, or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

Figure 3 is a view 300 similar to Figure 2 after a fin layer is deposited on the subfin layer according to one embodiment. As shown in Figure 2 the fin layer includes a fin portion 109 that is deposited on the subfin portion 107 and a fin portion 111 that is deposited on subfin portion 108. A protective layer 112 is deposited on the fin portion 111, as shown in Figure 3. In one embodiment, the material of the fin layer including portions 109 and 111 includes a

semiconductor that is the first component of the subfin layer, as described above. In one embodiment, each of the fin portions 109 and 111 is a strained semiconductor layer that has a lattice mismatch relative to the corresponding underlying subfin portion. In one embodiment, the strain in at least one of the fin portions 109 and 111 is a compressive strain. In one embodiment, the strain in at least one of the fin portions 109 and 111 is a tensile strain. In one embodiment, the fin portions 109 and 111 have substantially similar strain. As shown in Figure 3, protective layer 112 is selectively deposited to cover a portion of the insulating layer 102 comprising trench 104 having fin portion 111 while leaving a portion of the insulating layer 102 comprising trench 103 having fin portion 109 exposed. Protective layer 112 is deposited to protect the fin portion 111 from oxidation.

In one embodiment, the fin layer including the fin portion 109 and fin portion 111 is a group IV semiconductor layer. In one embodiment, each of the fin portion 109 and fin portion 111 comprises Si, Ge, SiGe, carbon, other group IV semiconductor material, or any combination thereof. In one embodiment, the fin portion 109 comprises an n-type group IV semiconductor material. In one embodiment, the fin portion 111 comprises a p-type group IV semiconductor material. In another embodiment, fin portion 109 comprises a p-type group IV semiconductor material. In another embodiment, the fin portion 111 comprises an n-type group IV semiconductor material. In one embodiment, fin portion 109 comprises an n-type germanium. In one embodiment, fin portion 111 comprises a p-type germanium. In one embodiment, the fin portions 109 and 111 are germanium layers, and subfin portions 107 and 108 are silicon germanium layers. In another embodiment, the fin portions 109 and 111 are silicon germanium layers and the subfin portions 107 and 108 are silicon germanium layers that have the germanium concentration smaller than that of the fin portions 109 and 111. In yet another embodiment, the fin portions 109 and 111 are silicon germanium layers and the subfin portions 107 and 108 are silicon germanium layers that have the germanium concentration greater than that of the fin portions 109 and 111. In yet another embodiment, at least one of the fin portion 109 and fin portion 111 comprises a III-V material, GaAs, InP, GaP, InGaAs, InAsSb, InGaAs, or other III-V material.

In one embodiment, the fin portion 109 is a part of an n-type metal oxide semiconductor fin based field effect transistor (NMOS FinFET) device, and the fin portion 111 is a part of a p- type metal oxide semiconductor fin based field effect transistor (PMOS FinFET) device. In another embodiment, the fin portion 111 is a part of NMOS FinFET device, and the fin portion 109 is a part of PMOS FinFET device.

In one embodiment, the thickness of each of the fin portions 109 and 111 is determined by design. In one embodiment, the thickness of each of the fin portions 109 and 111 is at least about 2 nm. In one embodiment, the thickness of each of the fin portions 109 and 111 is from about 2 nm to about 500 nm. In one embodiment, the thickness of each of the fin portions 109 and 111 is from about 2 nm to about 60 nm.

In one embodiment, protective layer 112 is a silicon dioxide, a silicon nitride, a metal oxide, other suitable hard mask material, or any combination thereof.

In an embodiment, the fin portions 107 and 109 are deposited to a predetermined thickness using a selective area epitaxy. In at least some embodiments, the fin portions 107 and 109 are locally grown on the corresponding subfin portion to a predetermined thickness through trenches. In one embodiment, the fin portions 109 and 111 are selectively deposited using one of epitaxial techniques known to one of ordinary skill in the art of microelectronic device manufacturing, such as but not limited to a CVD, a PVD, MBE, MOCVD, ALD, spin-on, or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

In one embodiment, protective layer 112 is selectively deposited using one of epitaxial techniques known to one of ordinary skill in the art of microelectronic device manufacturing, such as but not limited to a CVD, a PVD, MBE, MOCVD, ALD, spin-on, or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

Figure 4 is a view 400 similar to Figure 3, after a portion of insulating layer 102 is recessed and a capping layer is deposited on the fin portion 109 according to one embodiment. As shown in Figure 4, insulating layer 102 is recessed to form a fin portion 401 that is a portion of the fin portion 109 that protrudes from the top surface of insulating layer 102. Fin portion 401 comprises a top portion 402 and opposing sidewalls 403. As shown in Figure 4, a capping layer 113 is deposited on the top portion 402 and opposing sidewalls 403. The capping layer 113 is used to protect the fin portion 401 from oxidation. In one embodiment, capping layer 113 is a silicon dioxide, a silicon nitride, a metal oxide, other suitable hard mask material, or any combination thereof. In one embodiment, the thickness of the capping layer 113 is determined by the amount of oxidation that is performed later on in a process. In one embodiment, the thickness of the capping layer 113 is from about 2 nm to about 100 nm.

Fin portion 401 has a width 404, a height 405 and a length (not shown). In one embodiment, the length of the fin portion 401 is substantially greater than the width 404. In one embodiment, the dimensions of the fin portion 401 are determined by design. In one

embodiment, the height 405 is at least about 2 nm. In one embodiment, the height 405 is from about 2 nm to about 500 nm. In one embodiment, the height 405 is from about 2 nm to about 60 nm. In one embodiment, the width 404 defines the length of the nanowire device. In one embodiment, the width 404 is from about 2 nm to about 300nm. In one embodiment, the width 404 is from about 2 nm to about 50 nm.

As shown in Figure 4, the exposed portion of the insulating layer 102 is recessed down to an interface 114 between the fin portion 109 and subfin portion 107. In one embodiment, forming fin portion 401 involves depositing a patterned hard mask (not shown) onto fin portion 109 and then recessing insulating layer 102 to interface 114 to expose fin portion 109. In one embodiment, insulating layer 102 is recessed by a selective etching technique, such as but not limited to a wet etching, a dry etching, or any combination thereof techniques using a chemistry that has substantially high selectivity to the fin material. In one embodiment, after recessing the insulating layer 102, the patterned hard mask is removed by a chemical mechanical polishing (CMP) process as known to one of ordinary skill in the art of microelectronic device

manufacturing.

In another embodiment, forming fin portion 401 involves forming a fin stack comprising fin portion 109 on subfin portion 107 on the optional buffer layer on substrate 101 and depositing an insulating layer to a predetermined thickness on the portions of sidewalls of the fin stack on the substrate using deposition and patterning techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

Figure 5 is a view 500 similar to Figure 4, after a portion of the insulating layer 102 is recessed to expose the subfin portion 107 according to one embodiment. As shown in Figure 5, the exposed portion of the insulating layer 102 is recessed to expose the subfin portion 107 while leaving the capping layer 113 on the fin portion 401. In one embodiment, insulating layer 102 is recessed by a selective etching technique, such as but not limited to a wet etching, a dry etching, or any combination thereof techniques using a chemistry that has substantially high selectivity to the subfin material.

Figure 6 is a view 600 similar to Figure 5, illustrating an annealing of the exposed subfin portion 107 in an oxygen environment according to one embodiment. As shown in Figure 6, the exposed subfin portion 107 is subjected to annealing in the oxygen environment at a temperature Tox for a predetermined time. As shown in Figure 6, an oxide layer 118 is formed on the exposed side walls of the subfin portion 107 and exposed portions of the substrate 101 by annealing in the oxygen environment. Annealing of the subfin portion 107 in the oxygen environment causes a portion of the atoms of the second component of the subfin portion 107 to decouple from the atoms of the first component of the subfin portion 107 and causes the decoupled atoms of the second component of the subfin portion 107 to couple with the oxygen to form oxide layer 118. The decoupled atoms of the first component diffuse back to the subfin portion 107 ("condense") thereby increasing the concentration of atoms of the first component in the subfin portion, so that the condensed subfin portion 601 is formed. As the side wall portions of the subfin portion 107 are consumed by the oxide layer 118, the condensed subfin portion 601 has a width 117 that is smaller than the width of the subfin portion 107 prior to the condensation, as shown in Figures 5 and 6. As shown in Figure 6, the width 117 of the condensed subfin portion 601 is smaller than a width 119 of the fin portion 401.

In one embodiment, condensation of the first component of the subfin portion 107 changes the lattice mismatch between the fin portion 401 and the subfin portion 107 thereby adjusting the strain in the fin portion 401, so that an adjusted fin portion 604 is formed. In one embodiment, the fin portion 604 has the strain that is different from the strain of the fin portion 401. In one embodiment, for the fin portion 401 that has the concentration of atoms of the first component greater than that of in the subfin portion 107 (e.g., the fin portion 401 has Ge concentration greater than the Ge concentration in the subfin portion 107), increasing the concentration of atoms of the first component in the subfin portion 107 by condensation decreases the lattice mismatch between the fin portion 401 and the subfin portion 107, so that the strain of the fin portion 604 is less than the strain of the fin portion 401. In another embodiment, for the fin portion 401 that has the concentration of atoms of the first component smaller than that of the subfin portion 107 (e.g., the fin portion 401 is a SiGe fin having Ge concentration smaller than the Ge concentration in the subfin portion 107), increasing the concentration of atoms of the first component in the subfin portion 107 by condensation increases the lattice mismatch between the fin portion 401 and the subfin portion 107, so that the strain of the fin 604 is greater than the strain of the fin portion 401.

In one embodiment, the subfin portion 107 is SiGe, the first component of the subfin portion 107 is germanium, the second component of the subfin portion 107 is silicon, and the oxide layer 118 is a silicon oxide. In one embodiment, the oxygen consumes a portion of Si atoms from the exposed portion of the SiGe subfin, and the Ge atoms that have been decoupled from the oxidized Si atoms diffuse back into the SiGe subfin ("condense") thereby increasing the concentration of Ge atoms in the SiGe subfin. In a non-limiting example, the oxidation and condensation process for the SiGe subfin can be symbolically represented as SiGe+02 - Si02+Ge, where Si02 is a silicon oxide formed by coupling a portion of the Si atoms of the SiGe subfin to oxygen, and Ge represents a portion of Ge atoms that diffuse back into the SiGe subfin.

In one embodiment, the thickness of the oxide layer 118 depends on the concentration of the atoms of the second component in the subfin portion 107. In one embodiment, the thickness of the oxide layer 118 increases with the increase of the concentration of atoms of the second component in the subfin portion 107. In one embodiment, the thickness of the oxide layer 118 is from about 1 nm to about 20 nm.

As shown in Figure 6, subfin portion 107 has opposing sidewalls and edge portions 602 along the sidewalls. Subfin portion 107 has a middle portion 603 between the edge portions 602. In one embodiment, a gradient of concentration of atoms of the first component along the width of the fin portion 401 is generated by the condensation. In one embodiment, after the condensation, the concentration of atoms of the first component in the edge portions 602 is higher than in the middle portion 603. In more specific embodiment, after the condensation, the Ge concentration in the edge portions 602 of the subfin portion of SiGe is higher than the Ge concentration in the middle portion 603. In one non-limiting example, after the condensation, the Ge concentration in the middle portion 603 of the SiGe subfin is about 20% and the Ge concentration in the edge portions 602 of the SiGe subfin is about 80%. It is appreciated that the concentration percentages used herein refer to atomic fractions. In another embodiment, after the condensation the concentration of atoms of the first component along the width 117 of the subfin 107 is substantially uniform. In another embodiment, after the condensation the concentration of atoms of the first component in each of the portions 602 and middle portion 603 is substantially the same. In another embodiment, after the condensation the Ge concentration is substantially uniform in the SiGe subfin portion 107. In one embodiment, the width of each of the edge portions 602 and middle portion 603 is determined by the amount of condensation. In at least some embodiments, the width of each of the edge portions 602 and middle portion 603 is in an approximate range of about 1 % to about 50% of the width of the subfin 107.

In one embodiment, the uniformity of the concentration profile of the atoms of the first component in the subfin 107 is adjusted by adjusting the temperature Tox, the time of the annealing, a rate of oxygen flow, an amount of oxygen in the flow, or any combination thereof. In one embodiment, the uniformity of the concentration profile of the atoms of the first component in the subfin 107 is increased by increasing the temperature Tox, the time of the annealing, a rate of oxygen flow, an oxygen content, or any combination thereof. In one embodiment, after the condensation, the concentration profile of the atoms of the first component along the subfin thickness (from the top of the subfin 107 towards the substrate 101) is relatively constant.

In one embodiment, the concentration of Ge in the SiGe subfin portion increases by the condensation process thereby decreasing the lattice mismatch between the Ge fin and the SiGe subfin that reduces the strain in the Ge fin. In one embodiment, the amount of the condensation of atoms of the first component in the subfin portion 107 is adjusted to tune the amount of the strain in the fin portion 401. In one embodiment, the amount of condensation of the atoms of the first component of the subfin portion 107 is adjusted by changing the temperature Tox, the time of the annealing, a rate of oxygen flow, an oxygen content, or any combination thereof. In one embodiment, the condensation of the atoms of the first component of the subfin portion 107 is increased by increasing the temperature Tox, the time of the annealing, an amount of oxygen, or any combination thereof.

In one embodiment, increasing the initial (e.g., prior to condensation) concentration of the Ge atoms in the SiGe subfin portion decreases the annealing temperature Tox needed to obtain a predetermined amount of Ge condensation. In one non-limiting example, the SiGe subfin portion having about 30% Ge and 70% of Si is annealed in the oxygen gas at the temperature from about 800 degrees C to about 900 degrees C to obtain the condensed SiGe subfin portion having about 90% Ge and about 10% Si. In another non- limiting example, SiGe subfin portion having about 70% Ge and 30% of Si is annealed in the oxygen gas at the temperature from about 600 degrees C to about 700 degrees C to obtain the condensed SiGe subfin portion having about 90% Ge and about 10% Si. In one embodiment, a percentage of the strain reduction in the fin portion 401 after the condensation comparing to that of prior to the condensation is from about 1% to about 20 %.

In one embodiment, the oxygen environment comprises an oxygen gas, e.g., O2, ozone (O ₃ ), other oxygen containing gas, or any combination thereof. In one embodiment, the oxygen environment is a gas containing of about 100% of oxygen. In one embodiment, the annealing temperature Tox is at least about 600 degrees C. In one embodiment, the annealing temperature Tox is from about 600 degrees C to about 900 degrees C. In one embodiment, the annealing of the subfin portion is performed in a rapid thermal annealing (RTA) chamber, a tube furnace, or other annealing chamber. In one embodiment, the annealing of the exposed subfin SiGe portion is performed at a room pressure (about 1 atmosphere (atm)).

Figure 7 is a view 700 similar to Figure 6, after depositing an insulating layer 701 on the sidewalls of the condensed subfin portion 601, removing capping layer 113 and depositing a gate electrode layer 703 on a gate dielectric layer 702 on the fin portion 604 according to one embodiment.

As shown in Figure 7, a portion 705 of the electronic device structure includes gate electrode layer 703 on gate dielectric layer 702 on fin portion 604 on the condensed subfin portion 601. Figure 10 is a perspective view 1000 of the electronic device structure after a spacer layer 1001 is deposited on the gate electrode 703 and source and drain regions are formed at the opposite sides of the gate electrode 703 according to one embodiment. The cross-sectional view of the portion 705 along an axis A-A' without the spacer layer is shown in Figure 7.

In one embodiment, the insulating layer 701 can be any material suitable to insulate adjacent devices and prevent leakage. In one embodiment, insulating layer 701 represents insulating layer 102. As shown in Figure 7, the insulating layer 701 is deposited on the exposed portions of the substrate 101 and sidewalls of the condensed subfin portion 601. In one embodiment, the thickness of the insulating layer 701 is such that the top surface of the insulating layer 701 is evened out with the interface 114. As shown in Figure 7, fin portion 604 protrudes from the top surface of insulating layer 701. In one embodiment, insulating layer 701 includes oxide layer 118. As shown in Figure 7, the width 117 of the subfin portion 601 is smaller than the width 119 of the fin portion 604. In one embodiment, a difference between the width 117 and the width 119 is determined by the amount of the condensation of the subfin portion 107. In one embodiment, the capping layer 113 is removed using one or more of etching, CMP, or any other hard mask removal process as known to one of ordinary skill in the art of microelectronic device manufacturing.

As shown in Figure 7, gate dielectric layer 702 is deposited on a top portion 605 and opposing sidewalls 606 of the fin portion 604. Gate electrode layer 703 is deposited on gate dielectric layer 702. In one embodiment, gate dielectric layer 702 is a high-k dielectric material having a dielectric constant greater than the dielectric constant of silicon dioxide, such as but not limited to a metal oxide dielectric, e.g., tantalum silicon oxide (TaSiOx); pentaoxide (T&2 O5), titantium oxide (T1O2), zirconium oxide (ZrC^), hafnium oxide (HfC^), lanthanum oxide (La20 ₄ ), lead zirconium titanate (PZT), other high-k dielectric material, or any combination thereof. In an embodiment, the gate dielectric layer 703 is a silicon dioxide (S1O2), silicon oxynitride (SiO _x N _y ), a silicon nitride (S13 N ₄ ), or any combination thereof. In an embodiment, the thickness of the gate dielectric layer 703 is in an approximate range from about lnm to about 20 nm, and more specifically, between about 1 nm to about 10 nm.

As shown in Figure 7, gate electrode layer 703 is formed on and around the gate dielectric layer 702. As shown in Figure 7, gate electrode layer 703 has a top portion and laterally opposite sidewalls separated by a distance which defines the length of the channel of the fin device. Gate electrode 703 can be formed of any suitable gate electrode material. In an embodiment, the gate electrode 703 is a metal gate electrode, such as but not limited to, tungsten, tantalum, titanium, and their nitrides. It is to be appreciated that the gate electrode 703 can be a single material or a composite stack of thin films, such as but not limited to a polycrystalline silicon/metal electrode or a metal/polycrystalline silicon electrode.

In at least some embodiments, the gate dielectric layer 702 is deposited using one of gate dielectric layer deposition techniques, such as but not limited to a CVD, a PVD, MBE, MOCVD, ALD, spin-on, or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

In one embodiment, the gate electrode 703 is formed using one or more gate electrode patterning and etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

A source region 903 and a drain region 904 are formed at opposite sides of the gate electrode 703 in fin portion 604.

In one embodiment, forming the source and drain regions involves removing portions of the fin portion 604 at opposite sides of the gate electrode 703 to form recesses, e.g., by etching, and depositing the source/drain material into the recesses using one of the source/drain material deposition techniques. In another embodiment, forming the source and drain regions involves directly depositing the source/drain material on portions of the fin portion 604 at opposite sides of the gate electrode 703. In yet another embodiment, the source region and drain region wrap around portions of the fin portion 604 at opposite sides of the gate electrode 703. In one embodiment, source region 903 and drain region 904 are formed as faceted overgrowth regions, as shown in Figure 10.

In one embodiment, the spacer layer 1001 is patterned and etched using patterning and etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing to form spacers. In one embodiment, the spacers are nitride spacers (e.g., silicon nitride), oxide spacers, carbide spacers (e.g., silicon carbide), or other spacers. In one embodiment, the source/drain regions are formed on the areas of the fin portion 604 defined by the spacers at opposite sides of the gate electrode 703 using one of the source/drain forming techniques known to one of ordinary skill in the art of electronic device manufacturing.

In another embodiment, a dummy (sacrificial) gate electrode is deposited on the dielectric layer on the fin portion 604 prior to deposition of the final gate electrode layer. In one embodiment, the dummy gate electrode, or the dummy electrode and the underlying dummy dielectric are removed and replaced with a final gate electrode stack after source/drain regions are formed later in the process. Example dummy gate dielectric materials include silicon dioxide, and example dummy gate electrode materials include poly silicon, although any suitable dummy/sacrificial gate dielectric and/or electrode materials can be used. In one embodiment, the spacers are formed on the opposite sidewalls of the dummy gate electrode stack. In one embodiment, source/drain regions are grown on the areas of the fin portion 604 defined by the spacers at opposite sides of the dummy gate electrode, and then the dummy gate electrode is replaced by the final gate electrode, as known to one of ordinary skill in the art of electronic device manufacturing.

In one embodiment, the portion 705 is a non-planar transistor structure, and the fin portion

604 is configured for a non-planar transistor (e.g., a tri-gate transistor, all around gate transistor, or other non-planar transistor). In one embodiment, the fin portion 604 has three sides including a top side and opposing sidewalls configured for a tri-gate transistor. In another embodiment, the fin portion 604 includes a nanowire for a nanowire transistor. In yet another embodiment, the fin 604 portion includes a nanoribbon for a nanoribbon transistor.

In one embodiment, the source and drain regions are formed of the same conductivity type such as N-type or P-type conductivity. In an embodiment, the source and drain regions have a doping concentration of between lxlO ^A 19 and lxlO ^A 21 atoms/cm ^A 3. The source and drain regions can be formed of uniform concentration or can include sub-regions of different concentrations or doping profiles such as tip regions (e.g., source/drain extensions). In an embodiment, the source and drain regions have the same doping concentration and profile. In an embodiment, the doping concentration and profile of the source and drain regions can vary to obtain a particular electrical characteristic. The portion of the fin portion 604 located between the source region and drain regions, defines a channel region of the transistor.

The channel region can also be defined as the area of the semiconductor fin portion 604 surrounded by the gate electrode 703. At times however, the source/drain region may extend slightly beneath the gate electrode through, for example, diffusion to define a channel region slightly smaller than the gate electrode length (Lg). In an embodiment, the channel region is intrinsic or undoped. In an embodiment, the channel region is doped, for example to a conductivity level of between lxl 0 ^A 16 to lxlO ^A 19 atoms/cm ^A 3. In an embodiment, when the channel region is doped it is typically doped to the opposite conductivity type of the source/drain region. For example, when the source and drain regions are N-type conductivity the channel region would be doped to a p type conductivity. Similarly, when the source and drain regions are P type conductivity the channel region would be N-type conductivity. In this manner the portion 705 of the electronic device structure can be formed into either a NMOS transistor or a PMOS transistor respectively.

Channel regions can be uniformly doped or can be doped non-uniformly or with differing concentrations to provide particular electrical and performance characteristics. For example, channel regions can include halo regions, if desired. In one embodiment, portion 705 is a tri-gate transistor having gate dielectric 702 and gate electrode 703 surrounding the fin portion 604 on three sides that provides three channels on the fin portion 604, one channel extends between the source and drain regions on one sidewall of the fin, a second channel extends between the source and drain regions on the top surface of the fin, and the third channel extends between the source and drain regions on the other sidewall of the fin.

In an embodiment, the source region 903 is electrically coupled to higher levels of metallization (e.g., metal 1, metal 2, metal 3 , and so on ) to electrically interconnect various transistors of the array into functional circuits. In one embodiment, the drain region 904 is coupled to higher levels of metallization (e.g., metal 1, metal 2, metal 3, and so on ) to electrically interconnect various transistors of the array together into functional circuits.

Figure 8 is a view 800 similar to Figure 7, after a protective layer 704 is deposited on gate electrode layer 703, protective layer 112 is removed, a portion of the insulating layer 102 is recessed and a gate electrode layer 802 is deposited on a gate dielectric layer 801 on the fin portion 111 according to one embodiment. As shown in Figure 8, a portion 807 of the electronic device structure includes gate electrode layer 802 on gate dielectric layer 801 on fin portion 803 on the subfin layer 108. Figure 10 is a perspective view 1000 of the electronic device structure after a spacer layer 1002 is deposited on the gate electrode 802 and source and drain regions are formed at the opposite sides of the gate electrode 802 according to one embodiment. The cross-sectional view of the portion 807 along an axis B-B' without the spacer layer is shown in Figure 8.

A protective layer 704 is selectively deposited on the portion 705 that includes electrode layer 703. Protective layer 704 is deposited to protect the portion 705 while portion 807 is processed. In one embodiment, protective layer 704 is a silicon dioxide, a silicon nitride, a metal oxide, other suitable hard mask material, or any combination thereof.

In one embodiment, protective layer 704 is selectively deposited using one of epitaxial techniques known to one of ordinary skill in the art of microelectronic device manufacturing, such as but not limited to a CVD, a PVD, MBE, MOCVD, ALD, spin-on, or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

In one embodiment, the protective layer 112 is removed using one or more of etching,

CMP, or any other hard mask removal process as known to one of ordinary skill in the art of microelectronic device manufacturing. As shown in Figure 8, insulating layer 102 is recessed down to an interface 806 between the fin portion 111 and the subfin portion 108 to form a fin portion 803 that is a portion of the fin portion 111 that protrudes from the top surface of insulating layer 102. Fin portion 803 comprises a top portion 804 and opposing sidewalls 805, as shown in Figure 8.

Fin portion 803 has a width, a height and a length. In one embodiment, the width, height and length of the fin 803 are represented by the width, height and the length of the fin portion 401. In one embodiment, forming fin portion 803 involves depositing a patterned hard mask (not shown) onto fin portion 111 and then recessing insulating layer 102 down to interface 806 to expose fin portion 111. In one embodiment, insulating layer 102 is recessed by a selective etching technique, such as but not limited to a wet etching, a dry etching, or any combination thereof techniques using a chemistry that has substantially high selectivity to the fin material. In one embodiment, after recessing the insulating layer 102, the patterned hard mask is removed by a chemical mechanical polishing (CMP) process as known to one of ordinary skill in the art of microelectronic device manufacturing.

In another embodiment, forming fin portion 803 involves forming a fin stack comprising fin portion 111 on subfin portion 108 on the optional buffer layer on substrate 101 and depositing an insulating layer to a predetermined thickness on the portions of sidewalls of the fin stack on the substrate using deposition and patterning techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

As shown in Figure 8, gate dielectric layer 801 is deposited on top portion 804 and opposing sidewalls 805 of the fin portion 803. Gate electrode layer 802 is deposited on gate dielectric layer 801. In one embodiment, gate dielectric layer 801 is represented by one or more of the gate dielectric layers described above with respect to gate dielectric layer 702. As shown in Figure 8, gate electrode layer 802 is formed on and around the gate dielectric layer 801. As shown in Figure 8, gate electrode layer 802 has a top portion and laterally opposite sidewalls separated by a distance which defines the length of the channel of the fin device. In one embodiment, gate electrode layer 802 is represented by one or more of the gate electrode layers described above with respect to gate electrode layer 703. In one embodiment, the gate electrode 802 is formed using one or more gate electrode patterning and etching techniques, as described above.

As shown in Figure 10, a source region 905 and a drain region 906 are formed at opposite sides of the gate electrode 802 in fin portion 803. In one embodiment, the source region 905 and drain region 906 are formed using one or more of the source/drain forming techniques, as described above with respect to source/drain regions 903 and 904.

In one embodiment, the spacer layer 1002 is patterned and etched using one or more spacer patterning and etching techniques known to one of ordinary skill in the art of

microelectronic device manufacturing as described above with respect to spacer layer 1001.

In one embodiment, the portion 807 is a non-planar transistor structure, and the fin portion

803 is configured for a non-planar transistor (e.g., a tri-gate transistor, all around gate transistor, or other non-planar transistor). In one embodiment, the fin portion 803 has three sides including a top side and opposing sidewalls configured for a tri-gate transistor. In another embodiment, the fin portion 803 includes a nanowire for a nanowire transistor. In yet another embodiment, the fin portion 803 includes a nanoribbon for a nanoribbon transistor. The portion of the fin portion 803 located between the source region and drain regions, defines a channel region of the transistor.

The channel region can also be defined as the area of the semiconductor fin portion 803 surrounded by the gate electrode 802. At times however, the source/drain region may extend slightly beneath the gate electrode through, for example, diffusion to define a channel region slightly smaller than the gate electrode length (Lg). In an embodiment, the channel region is intrinsic or undoped. In an embodiment, the channel region is doped, for example to a

conductivity level of between lxl 0 ^A 16 to lxlO ^A 19 atoms/cm ^A 3. In an embodiment, when the channel region is doped it is typically doped to the opposite conductivity type of the source/drain region. For example, when the source and drain regions are N-type conductivity the channel region would be doped to a p type conductivity. Similarly, when the source and drain regions are P type conductivity the channel region would be N-type conductivity. In this manner the portion 807 of the electronic device structure can be formed into either a NMOS transistor or a PMOS transistor respectively. In one embodiment, portion 705 is an NMOS transistor structure and portion 807 is a PMOS transistor structure. In another embodiment, portion 705 is a PMOS transistor structure and portion 807 is an NMOS transistor structure.

Channel regions can be uniformly doped or can be doped non-uniformly or with differing concentrations to provide particular electrical and performance characteristics. For example, channel regions can include halo regions, if desired. In one embodiment, portion 807 is a tri-gate transistor having gate dielectric 801 and gate electrode 802 surrounding the fin portion 803 on three sides that provides three channels on the fin portion 803, one channel extends between the source and drain regions on one sidewall of the fin, a second channel extends between the source and drain regions on the top surface of the fin, and the third channel extends between the source and drain regions on the other sidewall of the fin.

In an embodiment, the source region 905 is electrically coupled to higher levels of metallization (e.g., metal 1, metal 2, metal 3 , and so on ) to electrically interconnect various transistors of the array into functional circuits. In one embodiment, the drain region 906 is coupled to higher levels of metallization (e.g., metal 1, metal 2, metal 3, and so on ) to electrically interconnect various transistors of the array together into functional circuits.

Figure 9 is a view 900 similar to Figure 8, after protective layer 704 is removed according to one embodiment. In one embodiment, the protective layer 704 is removed using one or more of etching, CMP, or any other hard mask removal process as known to one of ordinary skill in the art of microelectronic device manufacturing. As shown in Figure 9, the electronic device structure includes portion 705 and portion 807, as described above. View 900 is a cross- sectional view of the electronic device structure along axis A-A' and axis B-B' without the spacer layers depicted in Figure 10. In one embodiment, the electronic device structure 900 is complementary metal oxide semiconductor (CMOS) structure. In one embodiment, portion 705 includes an n-type metal oxide semiconductor field effect transistor (MOSFET), and portion 807 includes a p-type MOSFET.

Figure 11 illustrates an interposer 1100 that includes one or more embodiments of the invention. The interposer 1100 is an intervening substrate used to bridge a first substrate 1102 to a second substrate 1104. The first substrate 1102 may be, for instance, an integrated circuit die that includes transistors, diodes, or other semiconductor based devices having the strain that is controlled by condensation, as described herein. The second substrate 1104 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die that includes transistors, diodes, or other semiconductor based devices having the strain that is controlled by condensation, as described herein. Generally, the purpose of an interposer 1100 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1100 may couple an integrated circuit die to a ball grid array (BGA) 1106 that can subsequently be coupled to the second substrate 1104. In some embodiments, the first and second substrates 1102/1104 are attached to opposing sides of the interposer 1100. In other embodiments, the first and second substrates 1102/1104 are attached to the same side of the interposer 1100. And in further embodiments, three or more substrates are interconnected by way of the interposer 1100.

The interposer 1100 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 1108, vias 1110 and through-silicon vias (TSVs) 1112. The interposer 1100 may further include embedded devices 1114, including passive and active devices that have the strain that is controlled by condensation as described herein. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1100. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer 1100.

Figure 12 illustrates a computing device 1200 in accordance with one embodiment of the invention. The computing device 1200 may include a number of electronic device components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard. The components in the computing device 1200 include, but are not limited to, an integrated circuit die 1202 and at least one communication chip 1208. In some implementations the communication chip 1208 is fabricated as part of the integrated circuit die 1202. The integrated circuit die 1202 may include a processor 1204 such as a central processing unit (CPU), an on-die memory 1206, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM).

Computing device 1200 may include other electronic device components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, a volatile memory 1210 (e.g.,

DRAM), a non-volatile memory 1212 (e.g., ROM or flash memory), a graphics processing unit 1214 (GPU), a digital signal processor 1216 (DSP), a crypto processor 1242 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 1220, an antenna 1222, a display or a touchscreen display 1224, a touchscreen display controller 1226, a battery 1228 or other power source, a global positioning system (GPS) device 1244, a power amplifier (PA), a compass, a motion coprocessor or sensors 1232 (that may include an accelerometer, a gyroscope, and a compass), a speaker 1234, a camera 1236, user input devices 1238 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 1240 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 1208 enables wireless communications for the transfer of data to and from the computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1208 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1200 may include a plurality of communication chips 1208. For instance, a first communication chip 1208 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1208 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. One or more electronic device components (e.g., integrated circuit die 1202, communication chip 1208, GPU 1214, cryptoprocessor 1242, DSP 1216, chipset 1220), and other components may be formed in accordance with embodiments of the invention. In further embodiments, another electronic device component housed within the computing device 1200 may be formed in accordance with embodiments of the invention.

In various embodiments, the computing device 1200 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1200 may be any other electronic device that processes data.

The above description of illustrative implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

The following examples pertain to further embodiments:

In Example 1, an electronic device comprises a fin portion on a subfin portion, the fin portion comprising a first semiconductor material, the subfin portion comprising a second semiconductor material, the subfin portion having a width smaller than a width of the fin portion.

In Example 2, the subject matter of Example 1 can optionally include that the first semiconductor material is germanium, and the second semiconductor material is silicon germanium.

In Example 3, the subject matter of any of Examples 1-2 can optionally include that the first semiconductor material is silicon germanium and the second semiconductor material is silicon germanium, wherein a concentration of germanium in the first semiconductor material is greater than a concentration of germanium in the second semiconductor material.

In Example 4, the subject matter of any of Examples 1-3 can optionally include that the subfin portion comprises edge portions and a middle portion between the edge portions, wherein the second semiconductor material comprises silicon germanium and wherein a concentration of germanium in at least one of the edge portions is greater than a concentration of germanium in the middle portion.

In Example 5, the subject matter of any of Examples 1-4 can optionally include a second fin comprising a second fin portion having the first semiconductor material on a second subfin portion, wherein the fin portion has a strain that is smaller than the strain of the second fin portion.

In Example 6, the subject matter of any of Examples 1-5 can optionally include a second fin comprising a second fin portion having the first semiconductor material on a second subfin portion, wherein a width of the second subfin portion is greater than a width of the subfin portion.

In Example 7, the subject matter of any of Examples 1-6 can optionally include that an oxide layer is formed on sidewalls of the subfin portion, the oxide layer comprising silicon from the second semiconductor material.

In Example 8, the subject matter of any of Examples 1-7 can optionally include that the fin portion comprises a channel portion and a source/drain portion, and wherein a gate dielectric layer is deposited on the channel portion of the fin portion; and a gate electrode layer is deposited on the gate dielectric layer.

In Example 9, a data processing system comprises a chip including an electronic device comprising a fin comprising a fin portion on a subfin portion, the fin portion comprising a first semiconductor material, the subfin portion comprising a second semiconductor material, the subfin portion having a width smaller than a width of the fin portion.

In Example 10, the subject matter of Example 9 can optionally include that the first semiconductor material is germanium, and the second semiconductor material is silicon germanium.

In Example 11, the subject matter of any of Examples 9-10 can optionally include that the first semiconductor material is silicon germanium and the second semiconductor material is silicon germanium, wherein a concentration of germanium in the first semiconductor material is greater than a concentration of germanium in the second semiconductor material.

In Example 12, the subject matter of any of Examples 9-11 can optionally include that the subfin portion comprises edge portions and a middle portion between the edge portions, wherein the second semiconductor material comprises silicon germanium and wherein a concentration of germanium in at least one of the edge portions is greater than a concentration of germanium in the middle portion. In Example 13, the subject matter of any of Examples 9-12 can optionally include a second fin comprising a second fin portion having the first semiconductor material on a second subfin portion, wherein the first fin portion has a strain that is smaller than the strain of the second fin portion.

In Example 14, the subject matter of any of Examples 9-13 can optionally include a second fin comprising a second fin portion having the first semiconductor material on a second subfin portion, wherein a width of the second subfin portion is greater than the width of the subfin portion.

In Example 15, the subject matter of any of Examples 9-14 can optionally include that an oxide layer is formed on sidewalls of the subfin portion, the oxide layer comprising silicon from the second semiconductor material.

In Example 16, the subject matter of any of Examples 9-15 can optionally include that the fin portion comprises a channel portion and a source/drain portion, and wherein the electronic device further comprises a gate dielectric layer on the channel portion; and a gate electrode layer on the gate dielectric layer.

In Example 17, the subject matter of any of Examples 9-16 can optionally include that the first semiconductor material is an n-type semiconductor material.

In Example 18, a method to manufacture an electronic device comprises forming a fin comprising a fin portion on a subfin portion, the fin portion comprising a first semiconductor material, the first subfin portion comprising a second semiconductor material, depositing a capping layer on the fin portion, wherein the subfin portion is not covered by the capping layer; and annealing the subfin portion in an environment comprising oxygen to condense the second semiconductor material in the subfin portion to control a strain in the fin portion.

In Example 19, the subject matter of Example 18 can optionally include that the strain in the fin portion is decreased by annealing.

In Example 20, the subject matter of any of Examples 18-19 can optionally include that the first semiconductor material is germanium and the second semiconductor material is silicon germanium.

In Example 21, the subject matter of any of Examples 18-20 can optionally include that the first semiconductor material is silicon germanium and the second semiconductor material is silicon germanium, wherein a concentration of germanium in the first semiconductor material is greater than a concentration of germanium in the second semiconductor material. In Example 22, the subject matter of any of Examples 18-21 can optionally include depositing a protective layer on a second fin comprising a second fin portion on a second subfin portion.

In Example 23, the subject matter of any of Examples 18-22 can optionally include that the annealing temperature is from 600 degrees C to 900 degrees C.

In Example 24, the subject matter of any of Examples 18-23 can optionally include adjusting the strain in the fin portion by adjusting a temperature of the annealing, a time of the annealing, or any combination thereof.

In Example 25, the subject matter of any of Examples 18-24 can optionally include depositing an insulating layer on a substrate; forming a trench in the insulating layer to expose a portion of the substrate; depositing the subfin portion on the exposed portion of the substrate; and recessing the insulating layer.

In Example 26, the subject matter of any of Examples 18-25 can optionally include depositing a gate dielectric layer on a channel portion of the fin portion; and depositing a gate electrode layer on the gate dielectric layer.

In Example 27, the subject matter of any of Examples 18-26 can optionally include that an oxide layer is formed on sidewalls of the subfin portion by annealing, the oxide layer comprising silicon from the second semiconductor material.

In Example 28, the subject matter of any of Examples 18-27 can optionally include that the second semiconductor material includes silicon germanium, and a gradient of concentration of germanium is formed in the subfin portion by annealing.

In Example 29, the subject matter of any of Examples 18-28 can optionally include that the first semiconductor material is an n-type semiconductor material.

In Example 30, a method to manufacture an electronic device comprises depositing a protective layer on a first fin comprising a first fin portion on a first subfin portion, wherein a second fin comprising a second fin portion on a second subfin portion is not covered by the protective layer, each of the first fin portion and the second fin portion comprising a first semiconductor material, each of the first subfin portion and the second subfin portion comprising a second semiconductor material; depositing a capping layer on the second fin portion, wherein the second subfin portion is not covered by the capping layer; and annealing the second subfin portion in an environment comprising oxygen.

In Example 31, the subject matter of Example 30 can optionally include that the first semiconductor material is germanium and the second semiconductor material is silicon germanium. In Example 32, the subject matter of any of Examples 30-31 can optionally include that the first semiconductor material is silicon germanium, and the second semiconductor material is silicon germanium, wherein a concentration of germanium in the first semiconductor material is greater than a concentration of germanium in the second semiconductor material.

In Example 33, the subject matter of any of Examples 30-32 can optionally include depositing an insulating layer on a substrate; forming a trench in the insulating layer to expose a portion of the substrate; depositing the first subfin portion on the exposed portion of the substrate; and recessing the insulating layer.

In Example 34, the subject matter of any of Examples 30-33 can optionally include that an oxide layer is formed on sidewalls of the second subfin portion by annealing, the oxide layer comprising silicon from the second semiconductor material.

In Example 35, the subject matter of any of Examples 30-34 can optionally include depositing a gate dielectric layer on a channel portion of the second fin portion; and depositing a gate electrode layer on the gate dielectric layer.

In the foregoing specification, methods and apparatuses have been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of embodiments as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.