JP2014075717 | DOHERTY AMPLIFIER |
JP2004015319 | TRANSMISSION POWER ADJUSTMENT METHOD AND TRANSMISSION POWER ADJUSTMENT APPARATUS |
JP7031751 | Doherty amplifier |
GUSTAFSSON DAVID (SE)
WO2020182305A1 | 2020-09-17 | |||
WO2020089405A1 | 2020-05-07 |
EP3522371A1 | 2019-08-07 | |||
US20120105147A1 | 2012-05-03 |
A. M. M. MOHAMED ET AL.: "Doherty Power Amplifier With Enhanced Efficiency at Extended Operating Average Power Levels", IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, vol. 61, no. 12, December 2013 (2013-12-01), XP011532016, DOI: 10.1109/TMTT.2013.2288604
Claims 1. A power amplifier arrangement (100, 400, 500) comprises: a first power amplifier (P1, Dm) having an input (InM) and an output (OutM), which is a main amplifier in a Doherty power amplifier (110), and a second power amplifier (P2, Da) having an input (InA) and an output (OutA), which is an auxiliary amplifier in the Doherty power amplifier (110); an input power splitter (PS) having an input (Pin) and a first output (Out1) and a second output (Out2); a quadrature coupler (120) having an input port (QC1), a through port (QC2), a coupled port (QC3) and an isolated port (QC4), wherein the quadrature coupler (120) comprises two coupled transmission lines (TL1/TL2), a first terminal of the first transmission line (TL1) is the input port (QC1), a second terminal of the first transmission line (TL1) is the through port (QC2), a first terminal of the second transmission line (TL2) is the coupled port (QC3) and a second terminal of the second transmission line (TL2) is the isolated port (QC4); an output impedance matching network (IMN) having an input (IMNin) and an output (IMNout); and wherein the input (InM) of the first power amplifier (P1, Dm) is coupled to the first output (Out1) of the input power splitter (PS); the output (OutM) of the first power amplifier (P1, Dm) is coupled to the coupled port (QC3) of the quadrature coupler (120); the input (InA) of the second power amplifier (P2, Da) is coupled to the second output (Out2) of the input power splitter (PS); the output (OutA) of the second power amplifier (P2, Da) is coupled to the through port (QC2) of the quadrature coupler (120); the input port (QC1) of the quadrature coupler (120) is coupled to the input (IMNin) of the output impedance matching network (IMN); the output (IMNout) of the impedance matching network (IMN) is coupled to a load; and the isolated port (QC4) of the quadrature coupler (120) is coupled to an Alternating Current, AC, ground (gnd); and wherein a current of the second power amplifier (P2, Da) and an input impedance (RL) of the output impedance matching network (IMN) are tunable such that an efficiency of the power amplifier arrangement (100) is configurable for different output power back-off levels by changing the current of the second power amplifier (P2, Da) and the input impedance (RL) of the output impedance matching network (IMN). 2. The power amplifier arrangement (100, 400, 500) according to claim 1, wherein a characteristic impedance of the two coupled transmission lines (TL1/TL2) is determined based on a desired load resistance of the first power amplifier (P1, Dm) and a coupling coefficient of the two coupled transmission lines (TL1/TL2), wherein at the desired load resistance, the first power amplifier (P1, Dm) delivers a maximum output power. 3. The power amplifier arrangement (100, 400, 500) according to claim 2, wherein the characteristic impedance of the two coupled transmission lines (TL1/TL2) is determined by an equation where Z0 is the characteristic impedance of the coupled transmission lines, is the desired load resistance of the first power amplifier, and k is the coupling coefficient of the two coupled transmission lines (TL1/TL2). 4. The power amplifier arrangement (100, 400, 500) according to any one of claims 1-3, wherein the input impedance (RL) of the output impedance matching network (IMN) is determined based on a desired load resistance of the first power amplifier (P1, Dm), a coupling coefficient of the two coupled transmission lines (TL1/TL2) and an output power backoff level. 5. The power amplifier arrangement (100, 400, 500) according to claim 4, wherein the input impedance (RL) of the output impedance matching network (IMN) is determined by an equation wherein RL is the input impedance of the output impedance matching network, Ropt,m is the desired load resistance of the first power amplifier (P1, Dm) and κ is the coupling coefficient of the two coupled transmission lines (TL1/TL2) represents an output voltage level at which the second amplifier is at an onset, which is related to the output power backoff level by an equation wherein is the output power backoff level. 6. The power amplifier arrangement (100, 400, 500) according to any one of claims 1-5, wherein a maximum current of the second power amplifier (P2, Da) is determined based on a maximum current of the first power amplifier (P1, Dm) and an output power backoff level. 7. The power amplifier arrangement (100, 400, 500) according to claim 6, wherein the maximum current of the second power amplifier (P2, Da) is determined by an equation wherein is the maximum current of the second power amplifier (P2, Da), is the maximum current of the first power amplifier (P1, Dm), represents an output voltage level at which the second amplifier (P2, Da) is at onset, which is related to the output power backoff level by an equation , wherein is the output power backoff level. 8. The power amplifier arrangement (100, 400, 500) according to any one of claims 1-7, wherein the input of the first power amplifier (P1, Dm) is coupled to the first output of the input power splitter (PS) via a first input impedance matching network (IMN0). 9. The power amplifier arrangement (100, 400, 500) according to any one of claims 1-8, wherein the input of the second power amplifier (P2, Da) is coupled to the second output of the input power splitter (PS) via a second input impedance matching network (IMN1). 10. The power amplifier arrangement (100, 400, 500) according to any one of claims 1-9, wherein the output impedance matching network (IMN) comprises multiple switchable impedance matching networks (IMN11, IMN21, IMN31) and the input impedance of the output impedance matching network (IMN) is changed by selecting different impedance matching network. 11. The power amplifier arrangement (100, 400, 500) according to any one of claims 1-10, wherein the second power amplifier (P2, Da) comprises multiple transistors with different sizes for changing the current of the second power amplifier (P2, Da). 12. The power amplifier arrangement (100, 400, 500) according to any one of claims 1-10, wherein the second power amplifier (P2, Da) comprises a transistor, and wherein gate or base voltage of the second power amplifier is tuned for changing the current of the second power amplifier (P2, Da). 13. An electronic device (1000) comprising a power amplifier arrangement (100, 400, 500) according to any one of claims 1-12. 14. The electronic device (100) according to claim 13 is any one of a transmitter, a transceiver, a base station, a mobile device, a user equipment, a wireless communication device for a communication system. |
In the flowing, how to design the power amplifier arrangement 100 for any choice of OPBO levels will be described with reference to Figure 2.
Figure 2 shows a simplified schematic of the power amplifier arrangement 100, wherein the quadrature coupler 120 comprising two coupled transmission lines TL1 and TL2 is shown, and the main and auxiliary amplifiers P1 , P2 are represented by a voltage controlled current source, Im and la, respectively. The isolation port QC4 is grounded and the input port QC1 is terminated by a resistor R L , which represents the input impedance of the impedance matching network IMN.
The length of the two coupled transmission lines TL1 , TL2 may be a quarter- wavelength at a centre frequency of an RF signal. At the through port QC2 and coupled port QC3 connected to the outputs of the main and the auxiliary amplifiers P1, P2, the impedance matrix is given by
Where, V m and I m are the magnitude of the fundamental output voltage and current of the main amplifier P1 , V a and I a are the magnitude of the fundamental output voltage and current of the auxiliary amplifier P2. To combine currents from the main and the auxiliary amplifiers P1 , P2 constructively, the current from the auxiliary amplifier P2 should 90° ahead the current from the main amplifier P1, thus, I a and V a are multiplied by a negative imaginary number - j in equation (1).
Z ij is given by )
Where, Z oe and Z 00 represent the characteristic impedance of even and odd modes of the coupled transmission lines TL1/TL2, respectively. They are related to the characteristic impedance Z 0 of the coupled transmission lines TL1/TL2, Z 0 = √Z oe Z oo , and coupling coefficient ^^ of the coupled transmission lines TL1/TL2, 0 < ^^ < 1, by equations: Even and odd modes are the two main modes of propagation of a signal through a pair of coupled transmission lines. Odd mode impedance is defined as impedance of a single transmission line when the two coupled transmission lines are driven differentially with signals of the same amplitude and opposite polarity. Even mode impedance is defined as impedance of a single transmission line when the two coupled transmission lines are driven with a common mode signal of the same amplitude and the same polarity. A Doherty PA has two drain efficiency ( ^^) peaks, one peak at the maximum output power, and another one at an output power back-off level, as shown in Figure 3, where the drain efficiency versus different output power back-off levels OPBO 1 = 10.5 dB, OPBO 2 = 8 dB, and OPBO 3 = 6 dB is shown. The different output power back-off levels are associated with different output voltage levels represented by ξ b which is a ratio of the actual output voltage V out to the maximum output voltage V out,max , ^^ ^^ = V out /V out,max , 0<ξb<1. For examples, for OPBO1 = 10.5 dB, ξ b = 0.3, for OPBO2 = 8 dB, ξ b = 0.4, and for OPBO3 = 6 dB, ξ b = 0.5. That is the output voltage level ξ b is related to the output power back-off level by an equation ^ . As shown in Figure 3, the efficiency of the power amplifier arrangement 100 is configurable for different output power back-off levels. There are drain efficiency peaks at the power back-off levels of 10.5 dB, 8 dB and 6 dB. At the output voltage level ξ b , the auxiliary amplifier P2 is at an onset, i.e., the auxiliary amplifier P2 is just about to turn on or is just getting started, the current of the auxiliary amplifier P2 is 0, i.e. Ia = 0, and the load impedance of the main amplifier P1 should be At PAE peak of the maximum output power, where and represent the magnitudes of the maximum fundamental output voltage and current from the main amplifier P1, respectively, and represent the magnitudes of the maximum fundamental output voltage and current from the auxiliary amplifier P2, respectively. From equations (1), (4)-(6), obtaining From equations (2)-(7), obtaining When the main amplifier’s R opt,m and , as well as OPBO ( ξ b ) are determined, the maximum current of the auxiliary amplifier is determined by equation (5). The equations above describe how to build a quadrature coupler based DPA which has efficiency peak for any choice of output power back-off OPBO levels. When the main amplifier’s R opt,m and, as well as the output power back-off level OPBO ( ξ ) are b determined, the maximum current of the auxiliary amplifier is determined by equation (5). Assuming the maximum current I max is proportional to the size of transistor, the ratio of the size of the auxiliary and the main amplifier transistors can be determined too. The load of the quadrature coupler, i.e., the input impedance R L of the impedance matching network IMN can be calculated according to equation (9), then the impedance matching network IMN is designed, which has the impedance transfer ratio R L /50, assuming a 50 Ω interface to an antenna. For example, consider three quadrature coupler based Doherty power amplifiers (QC DPAs) having the same main amplifier size and current, but different efficiencies at output power back-off level, all having R opt,m equals to 50 Ω and I m,max equals to 1 A. The quadrature coupler is the same for all three cases with κ = 0.85 and Z 0 = 80.7 Ω, while the auxiliary amplifier has different sizes, i.e., different I a,max depending on OPBO levels, see the parameters in three cases in Table 1. Table 1 Parameters of the QC DPAs As seen from Table 1, the deeper the OPBO level is, the larger is the maximum current of the auxiliary amplifier, thus, the larger is the maximum output power of the QC DPA. Furthermore, the load of the quadrature coupler R L is varied for different OPBO levels. The deeper the OPBO level is, the larger is R L . Figure 3 is a plot showing simulated drain efficiencies (DE) versus output power for the power amplifier arrangement 100, where the current of the auxiliary amplifier P2 and the input impedance R L of the output impedance matching network IMN are configured with the values of three QC DPAs shown in Table 1. The power amplifier arrangement 100 has DE peaks at OPBO levels of 6 dB, 8 dB, as well as 10.5 dB. That is the efficiency of the power amplifier arrangement 100 is configurable for different output power back-off levels and may have different efficiency at the output power back-off region when Ia,max and R L are changed simultaneously. The power amplifier arrangement 100 may be configurable in varies ways with respect to the current of the second power amplifier P2/Da and input impedance R L of the output impedance matching network IMN. According to some embodiments herein, the output impedance matching network IMN may comprise multiple switchable impedance matching networks and the input impedance of the output impedance matching network IMN is changed by selecting different impedance matching network. According to some embodiments herein, the second power amplifier P2/Da may comprise a transistor. Gate or base voltage of the second power amplifier P2/Da may be tuned for changing the current of the second power amplifier P2/Da. Figure 4 shows an example of configurable power amplifier arrangement 400 according to embodiments herein. The configurable power amplifier arrangement 400 comprises multiple switchable impedance matching networks IMN11, IMN21, IMN31 and the input impedance R L of the output impedance matching network IMN may be changed by selecting different impedance matching networks. The power amplifier arrangement 400 has two amplifier devices, a main amplifier device Dm and an auxiliary amplifier device Da, both shown as a field-effect transistor (FET). The device size of the auxiliary amplifier Da should be large enough to deliver Ia,max for the PAE peak at the deepest output power back-off level. I a,max is tuned by changing a gate voltage Vga of the auxiliary amplifier device Da, letting the I a,max varying from 1 A to 2.33 A, corresponding to 6 dB to 10.5 dB of OPBO levels. Meanwhile, R L can be changed by selecting different impedance matching networks IMNi1, i=1,2,3, which has different impedance transformation ratios , assuming the load impudence of the power amplifier arrangement 400 is 50 Ω. For instance, when switch S1 is switched on, IMN11 which transfers R L =72.2 Ω into 50 Ω is selected. In this case, the DE peak is at 6 dB of OPBO level, see Table 1. When switch S2 is switched on, IMN21 which transfers R L =90.3 Ω into 50 Ω is selected, and the DE peak moves to 8 dB of OPBO level. When switch S3 is switched on, IMN31 which transfers R L =120.4 Ω into 50 Ω is chosen, and the DE peak is at 10.5 dB of OPBO level. In the configurable power amplifier arrangement 400, shunted inductors LD at drains of Dm and Da are AC chokes and capacitors CD are AC coupling capacitors to block DC. RG at gates of Dm and Da are bias resistors. IMN0 and IMN1 are impedance matching networks at the inputs of the main and auxiliary amplifiers respectively. Therefore, according to some embodiments herein, the input of the first or main power amplifier P1/Dm may be coupled to the first output of the input power splitter PS via a first input impedance matching network IMN 0 and the input of the second or auxiliary power amplifier P2/Da may be coupled to the second output of the input power splitter PS via a second input impedance matching network IMN 1 . The topology of the configurable power amplifier arrangement 400 is also applicable to a conventional DPA. Namely the quadrature coupler may be replaced by a quarter- wavelength TL or other kinds of couplers, for instance, branch-line coupler. According to some embodiments herein, the second power amplifier P2/Da may comprise multiple transistors with different sizes for changing the current of the second power amplifier P2/Da. Figure 5 shows another example of configurable power amplifier arrangement 500 according to embodiments herein. The power amplifier arrangement 500 has a main amplifier device Dm and a number of auxiliary amplifier devices Da1, Da2, Da3…, all shown as a field-effect transistor (FET). The maximum current of auxiliary amplifier can be changed by turning “on” or selecting different devices Dai, i=1,2,3 which has different sizes. Da2 and Da3 are 1.5 and 2.33 times as large as Da1, respectively. Da1, Da2 and Da3 are able to deliver a maximum current of 1A, 1,5A and 2,33 A, respectively. IMNi0, i=1,2,3 are impedance matching networks at gates of auxiliary amplifier devices Dai, i=1,2,3, respectively. To demonstrate the performance and advantages of the power amplifier arrangement 100, 400, 500 according to embodiments herein, simulations have been performed for a QC DPA designed according to embodiments herein and a conventional DPA. The QC DPA according to embodiments herein has a main amplifier with and equal to 50 Ω and 1 A, respectively, and an auxiliary amplifier with a maximum current I a,max of 1.81 A. The quadrature coupler has a coupling coefficient κ of 0.8 and characteristic impedance Z 0 of 66.6 Ω. R L for the QC DPA is 90.2 Ω. R L for the conventional DPA is 17.7 Ω. The QC DPA in this example is configured for DE peak at 9 dB output power back-off level, i.e. ξ b = 0.355. Figure 6 shows the simulated drain efficiency versus output power at different normalized frequencies f0, f0=f/fc, from 0.7 to 1.3 with a step of 0.1, where the solid lines are the simulated drain efficiency for the QC DPA according to embodiments herein and the dash lines are the simulated drain efficiency for the conventional DPA. The center frequency fc in this example is fc=4 GHz. As can be seen from Figure 6, at the centre frequency fc equal to 4GHz, i.e., the normalized frequency f0=1, the DE curves of two DPAs are overlapped completely. As the frequency departs from the centre frequency, the efficiency of the QC DPA will decrease. However, as the frequency deviates from the centre frequency, the QC DPA according to embodiments herein has a better DE than the conventional DPA at output power back-off. Figure 7 shows the simulated DE versus normalized frequency f0 for the QC DPA according to embodiments herein (solid line) and the conventional DPA (dotted line). The normalized frequency bandwidth for DE larger than 50 % is about 0.4 for the QC DPA according to embodiments herein and 0.18 for the conventional DPA. When the normalized frequency f0 is swept from 0.7 to 1.3, the maximum output powers of the QC DPA and conventional DPA vary about 1 dB, from 41.3 dBm to 42.5 dBm, as shown in Figure 6. However, the small signal gain varies 7 dB for the conventional DPA and 3.5 dB for the QC DPA, as shown in Figure 8, where the simulation results on normalized small signal gain versus normalized frequency for the QC DPA and conventional DPA are shown. The normalized 3-dB bandwidths of the QC DPA and the conventional DPA are about 0.6 and 0.32, respectively. Furthermore, the bandwidth of the QC DPA depends on the quadrature coupler’s coupling coefficient κ, as shown in Figure 9, where the simulated results of drain efficiency of the QC DPA versus the normalized frequency at different coupling coefficients are shown. In those simulations, a DE peak is at 9 dB OPBO. However, the impedance Z 0 and R L are varied for different coupling coefficients κ according to equations (8), (9). The larger the coupling coefficient κ is, the wider is the bandwidth of the QC DPA. For a DE larger than 50%, the normalized bandwidth is 0.26 and 0.7, as κ is equal to 0.7 and 0.9, respectively. Therefore, it has been demonstrated that the power amplifier arrangement 100, 400, 500 according to embodiments herein has advantages of having efficiency peak at deep power back-off levels, e.g. at OPBO levels of 8dB, 9 dB, 10.5 dB etc., i.e. OPBO>6 dB; having wider bandwidth than the conventional DPA; having reconfigurable efficiency at different output power back-off levels. The power amplifier arrangement 100, 400, 500 according to embodiments can also adapt to the variations of the PAPR of the different modulated RF signals. To summarize, the power amplifier arrangement 100, 400, 500 according to embodiments herein is a quadrature coupler based DPA, which can be designed to have efficiency peak at deep OPBO levels. The quadrature coupler 120 may be realized by two coupled transmission lines TL1/TL2 with a length of a quarter wavelength at a centre frequency of an RF signal. The coupled transmission lines TL1/TL2 are designed based on the desired load resistance of the main power amplifier P1, Dm and the coupling coefficient κ of the two coupled transmission lines TL1/TL2. The larger is the coupling coefficient κ, the wider is the bandwidth of the quadrature coupler based DPA 100, 400, 500. The efficiency of the quadrature coupler based DPA 100, 400, 500 at an output power back- off level is reconfigurable by changing the current of the auxiliary amplifier P2, Da, as well as the input impedance R L of the output impedance matching network IMN. The power amplifier arrangement 100, 400, 500 according to embodiments herein may be employed in various electronic devices or apparatus etc. Figure 10 shows a block diagram for an electronic device or apparatus 1000. The electronic device or apparatus 1000 comprises a power amplifier arrangement 100, 400, 500 according to embodiments herein. The electronic device 1000 may be a transmitter, a transceiver, a base station, a mobile device, a user equipment, a wireless communication device, a radar for a communication system. The electronic device 1000 may comprise other units, where a memory 1020, a processing unit 1030 are shown. The embodiments herein are not limited to the above described preferred embodiments. Various alternatives, modifications and equivalents may be used. Those skilled in the art will understand that the power amplifier arrangement 100, 400, 500 according to embodiments herein may be implemented by any semiconductor technology, e.g. Bi-polar, N-type Metal Oxide Semiconductor (NMOS), P-type Metal Oxide Semiconductor (PMOS), Complementary Metal Oxide Semiconductor (CMOS), Silicon on Insulator (SOI) CMOS, field-effect transistor (FET), MOSFET or Micro-Electro-Mechanical Systems (MEMS) technology etc. When using the word "comprise" or “comprising” it shall be interpreted as non-limiting, i.e. meaning "consist at least of". Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the appended claims.
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