Three Dimensional integrated circuits [3D ICs] are becoming a very important technology for the fundamental advancement in manufacturing of lower cost higher performance smaller physical size integrated circuits. There are potentially a number of methods for the fabrication of 3D integrated circuits that result in the stacking of single or 2D integrated circuit layers and optionally in combination with other electronic devices such as MEMS or passive circuit layers. These methods for the stacking of individual circuit layers or die at present will typically use a circuit layer that has already been tested or qualified in some manner prior to being thinned and then cut from the semiconductor wafer upon which it was formed. Such circuit die, or as herein will subsequently be referred to as circuit layers, may at times be referred to as KGD [Known Good Die]. The KGD characterization placed a circuit layer is an indication of circuit layer yield and when KGD circuit layers are stacked to form a 3D IC, the potential yield of the resulting 3D IC is significantly enhanced.

Configurable Vertical Integration [CVI] 3D integrated circuits are fabricated by stacking individual circuit layers [die] or circuit wafers, wherein a circuit wafer typically comprises an array with some number individual circuit die. Circuit wafers can be stacked, and from this wafer stack, 3D stacked ICs are then cut or diced from the wafer stack in much the same manner as Two Dimensional [2D] ICs are diced from a single circuit wafer. A CVI IC can be described as a hardware system encapsulating a hardware system. CVI ICs are designed to operate in such a manner that a majority of circuit portions of the CVI IC can be disabled at any time during its initial manufacturing test qualification or yield determination, and or during its life cycle. The yield of the CVI IC is verified by external or internal testing methods and means by enabling the circuit portions on each CVI circuit layer by one of several potential progressive step by step test and circuit validity evaluation methods with the recording of the CVI IC defective circuit portions such that the defective circuit portions are not enabled during subsequent CVI IC use. The circuit portions are preferably designed to be smaller in area to raise their individual yield probabilities and preferably have one or more equivalent counter parts such that should one or more circuit portions be determined to be defective the CVI IC will still yield at some acceptable level of acceptable operational specification as a useful integrated circuit and economic utility. The CVI invention provides methods and means for enabling the

implementation of Fault Tolerant and High Availability 3D IC embodiments.

The yield enhancement capability of the CVI invention provides methods and means to achieve economically acceptable yields 3D ICs that have higher circuit densities than that can be achieved with from a single 2D IC. CVI ICs do not have a limitation of the number of circuit layers they may comprise. The CVI invention allows for the yield of arbitrarily large CVI ICs with the number of circuit layers exceeding 10, 30 and or 50. BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to the methods and means for yield enhancement of stacked or three dimension integrated circuits.

2. State of the Art

Two Dimensional [2D] Integrated Circuits [ICs] are in general designed without the capability for Yield Enhancement as an active or passive means incorporated into the design or operation of the 2D integrated circuit. The primary means for achieving Yield Enhancement or economically acceptable yields of 2D circuits is semiconductor process technology. There are well know exceptions, however, such as DRAM or FLASH memory circuits and FPGA [Field Programmable Gate Arrays] circuits, and in these circuits in addition to the use of process technology, Yield Enhancement is implemented through first testing the 2D IC and then by manual or external intervention means disabling defective portions of the 2D IC. The defective circuit portions may be replaced with a spare or redundant circuit portion identical to the defective portion, and such defective circuit portions eliminated from use with the 2D IC, wherein the loss of use of the defective portions does not reduce the operation capacity of the 2D IC below some preset minimum specification. The presently the primary means that enables the yield of present 2D ICs is the manufacturing processes used in the fabrication of the 2D IC. Semiconductor manufacturing process technology attempts to maximize the yield or number of defect free 2D ICs on a semiconductor wafer. The wafer is the basic unit of measure for semiconductor IC manufacturing process yield, semiconductor process yield is calculated by dividing the number of defect free 2D ICs by the total number of 2D ICs on the wafer.

The Yield Enhancement circuitry used in these 2D ICs is in general referred to as reconfiguration circuitry. This reconfiguration circuitry is used only during the testing of the IC as part of the manufacturing process, and may consist of fuse or anti-fuse circuitry that permanently change the interconnect structure of the IC such that it is able to function in a defect free manner consistent with its design specification. Reconfiguration of these ICs may also be achieved by use of a laser to cut interconnections for the purpose of isolating a defective circuit portion. In all cases, however, the reconfiguration of these ICs is accomplished by first performing functional testing the IC as a whole, wherein all circuit portions of the IC with the exception of any spare circuit portions are executed or brought into operation. It is important to note for the purposes of this discussion, that current IC test means do not test 2D ICs by testing sub-portions of the IC. The testing of a 2D IC is performed by external test equipment and the testing determines the presence of the then existing circuit defects and whether or not these defects can be corrected by the use of reconfiguration of the circuit or the substitution of the defective circuit portions with the available spare circuit portions. Once the reconfiguration process is implemented, the 2D IC is again tested. This method of test and reconfiguration of the 2D IC is a static method and only done in conjunction with external test equipment and only done as part of the manufacturing process of the IC and typically is not or cannot be repeated once the IC is installed for its intended application in an electronic assembly.

Methods of fabrication of 3D ICs and apparatus for same are disclosed in U.S. Patents 5,354,695, 5,915,167 and 7,402,897 of the present inventor and are herein incorporated by reference.

SUMMARY OF THE INVENTION

The CVI invention enables Yield Enhancement of 3D ICs. This is accomplished by the use of unique circuit design and circuit control methods and means. The CVI IC incorporates circuitry preferably per circuit layer that during IC manufacturing validity testing or during subsequent operational use of the CVI IC, allows certain circuit portions or all circuit portions of the CVI IC to be enabled or disabled from operation as needed. The circuitry of a CVI IC is broadly divided into several types of Circuit Elements [CEs] or circuit portions: Configuration Circuit Elements [CCEs]; Bus Circuit Elements [BCEs]; and Process Circuit Elements [PCEs]. The

Configuration Control Elements [CCEs] and Circuit Elements [BCEs & PCEs] herein may also be broadly referred to as circuit portions, are conventional semiconductor Integrated Circuits [IC] and made by conventional semiconductor fabrication techniques.

The Configuration Control Elements or CCEs of a CVI IC are used to form at least one network of CCEs that control the enabling and disabling of all or a plurality of the other Circuit Elements [CEs] of the CVI IC. The CCE disables a CE by gating control of clock or power interconnections to a CE or through the use of by-pass circuitry. There may be one or plurality of CCE networks in a single CVI IC. These CCE networks may operate separately of each other with each controlling distinct sets CEs, or they may overlap control of certain CEs. CCE networks may or may not have external interconnections to receive control signals. CCE networks may communicate through use of the Input/Output external wiring pads, via the optional CCE wireless facility or some other physical means such as through access to a microprocessor.

The CCE is the basic Circuit Element of the CVI yield enhancement method. At least one CCE is present on a typical CVI IC circuit layer, but it is not required that a CCE be present on every circuit layer of a CVI IC. The CCEs of a CVI IC are used to form a CCE network that spans all or some portion of the CVI IC circuit layers. A CCE network is established or formed during the initial test of a CVI IC and optionally every time the CVI IC is powered up or optionally during the useful life of the CVI IC when a circuit failure has occurred and the CE configuration CVI IC requires revision. A CCE is typically designed to enable the operation or execution of the BCE and PCE CEs of the circuit layer on which the CCE is present and the next in order CCE of the CCE network of which it is a member and which may be on the same circuit layer of another circuit layer of the CVI IC. There are certain circuit functions common to all CCEs of a CVI IC, such as self verification circuitry, next in order CCE enablement and communication circuitry, BCE and PCE enablement circuitry. The CCE network may require other circuit resources such as the use of a

microprocessor or flash memory. These CCE circuit support resources may be internal or external to the CVI IC, or these circuit resources may be incorporated into a few or all of the CCEs of a CCE network or exist as a CE.

The manufacturing qualification testing or initial testing of a CVI IC, begins with establishing the first fully functional or defect free CCE of the CCE network. This is accomplished by selection and enabling the operation of only said first CCE through the I/O pads of the CVI IC or by wireless access. Functional or operational qualification tests are performed on said first CCE to determine if it can be used in the CCE network and is sufficiently defect free. If this first CCE is determined to be defective, a subsequent first CCE is selected and the qualification test process repeated. If there are no remaining CCEs available to be the first CCE, the CVI IC is rejected or failed.

The first CCE is interconnected to one or more next in order CCEs, these CCEs are typically on a different circuit layer of the CVI IC. This next in order CCE is then enabled by the first CCE and is qualified for function or operation by tests performed through or from the first CCE. If it is determined that this next in order CCE can be used in the CCE network and there are no subsequent CCEs to be considered for the CCE network, then the CCE network is completed. If this next in order CCE failed it tests or was determined to be defective, a subsequent next in order CCE is selected and the testing process repeated. If there is not a subsequent next in order CCE for the first CCE then a subsequent first CCE is selected and the testing process repeated. If there is not a subsequent first CCE, the CVI IC is failed.

If the current next in order CCE is not the last CCE of the CCE network, then a subsequent next in order CCE is selected that is connected to the current next in order CCE. This newly selected next in order CCE is enabled and the test process of said CCE is repeated in a manner similar to that used with the current next in order CCE. The testing process for CCEs continues with the selection of next in order CCEs until the CCE network is complete or it is determined that it cannot be completed and the CVI IC is failed. Once the CCE network is completed, the CCE network used as a control means to test the BCEs and PCEs of the CVI IC.

There are preferably redundant CCEs per CVI circuit layer. This significantly raises the probability that a CCE network will yield from the available CCEs of the CVI IC. Further, the primary CCE network may have one or more CCE sub-networks. CCE sub-networks may result from a structural design decision relating to a specific subset of CVI circuit layers, such as a subset of circuit layers that are FPGA circuits or memory circuits wherein such a subset of circuit layers may be designed to function with respect to each other a in dependent manner and this may require a subset of CCEs.

A CVI IC has several potential operating modes. They range from a test mode for initial manufacturing qualification to a circuit execution mode wherein the CVI CCE network circuitry operates as a supporting subsystem providing services to the CVI IC during its normal operation.

CVI IC and CVI IC CCE network operating modes:

1. Manufacturing test circuit validation. This is an operating mode of the CVI IC wherein the CCE circuitry is used as an integral part of the final IC

manufacturing validity testing procedure. The process first determines whether a CCE network for the CVI IC can be formed and qualified, a subsequent test of the BCE and PCE CEs on an individual basis or in small groups wherein a configuration database of the functional validity and preferably performance characterization of the BCE and PCE CEs is developed, and finally, a full functional test of the CVI IC configured accordingly to said database is performed. Testing of the BCE and PCE CEs will preferably start with a BCE that is externally connected to I/O pads of the CVI IC or to a PCE that performs wireless I/O. The configuration database may contain multiple CVI IC configurations and wherein a given

configuration may have one or more sub-configurations that are static or can be dynamically initiated. The full functional test may result in further CE defect detection, and therefore, changes to the configuration database and the repeat of the full functional test procedure. Successfully completed testing will result in a permanent [single or selectable], reconfigurable

[single or selectable], or dynamically loaded circuit configuration [s].

CVI IC configuration select circuit start. This is an operating mode of the CVI IC wherein the CCE network initiates the operation or execution of the IC by selecting a configuration for the BCE and PCE CEs from the configuration database, and then transferring circuit operation to one of the CEs. The CCE network may make the selection of the CE configuration dependent upon taking into account various internal or external initial condition variables. Once the CVI IC is in CE operation, the field or user programming of CEs can command the CCE network to effect CE configuration changes or to cause the selection the initiation of a CE configuration subset from the CVI

configuration database. CE operation can make requests of the CCE network [process or task execution runtime CCE network services] to perform configuration of BCE and PCE resources to optimize the performance of dataflow or processor unit sequencing flow specific to an executing process or group of processes or specific to an instruction of a ISP [Instruction Set Processor] or FPGA directed data or information flow.

Non-CVI IC circuit start. This is an operating mode of the CVI IC wherein execution of the CVI IC starts from a single permanently proscribed CE configuration or from a selected CE configuration. The CCE network circuitry is not used as part of circuit initiation. The CE configuration selection may be effected through the use of I/O signal pads or a wireless connection. The field or user programming of CEs can not command the CCE network to effect CE configuration changes or to cause the selection of a CE configuration subset from the CVI configuration database.

4. CVI IC dynamic CCE network circuit start. This is an operating mode of the CVI IC wherein execution of the CVI IC begins with CCE network formation or rebuild, and optionally, full or partial CE validity testing, and or CE

configuration amendment such as the dedication of BCE operation. There can be a wide range of additional tasks the CCE network can be designed and directed to perform at the commands of internal or external circuitry. This CVI mode is used during the useful life of the CVI IC.

The CCE network is used as a means to perform qualification testing of all BCEs and PCEs or CCE controlled CEs of the CVI IC. The CCE network allows the incremental or one at a time testing of BCE and PCE CEs. In this manner, each BCE and PCE can be tested individually, and should a BCE or PCE be defective, it can be isolated or disabled from use. It is a preferred embodiment that there is sufficient additional equivalent BCE or PCE CEs to offset the loss of a CCE controlled CEs. A defective CE may reduce the operational capacity of the CVI IC, but not to the extent that it cannot provide an acceptable level operational capacity. If there exists CEs in the CVI IC that are not controlled or enabled by a CCE network, then such CEs would be tested as part of the full functional test of the CVI IC in one or more of the CVI IC configurations or by conventional test means.

Fig. 1 shows a circuit layer of a CVI IC comprising CCE, BCE and PCE circuitry wherein all of the BCE and PCE CEs are directly enabled or disabled by a CCE, however, not all CEs of a CVI IC are required to be controlled by the CCE network of the CVI IC. An additional function that the CCE network can optionally perform is the creation of a permanent or temporary CVI circuit configuration table comprising at a minimum the defective CEs of the CVI IC. The circuit configuration table may also comprise CE layer location, CE performance characteristics and optimum bus paths between various PCEs.

Potential internal CCE and CCE network functions:

1. Self test verification.

2. Enable and disable control of next in order CCEs during CCE network generation.

3. Selection and verification of next in order CCE in CCE network.

4. Dynamic CCE network configuration of BCE and PCE circuits and other PCE execution runtime originated commands.

5. Monitoring of BCE and PCE activity and exception or interrupt

signaling.

6. BCE and PCE operation parameter setting. The CCE network in addition to CVI IC verification test and initialization configuration functions, can also process commands originated during PCE process or task execution. These PCE originated runtime commands provide a means to dynamically make changes to the BCE and PCE resources of a CVI IC during its standard or normal operation. The CCE network may then be responsible for parallel processing data or operation sequencing conflict resolution per process or task, this might be accomplished through address monitoring or execution flow monitoring initialed by the CCE network. These CCE network executed commands may cause various permanent or temporary configuration changes of BCE transmission paths and the operational specifics of PCEs that are generic or specific to an executing process or task, or specific to an instruction of an ISP [Instruction Set Processor]; setting of process context dependent event signaling such as address read/write events; PCE fault detection through configuring parallel PCE comparison operations; PCE fault detection and correction through configuring PCE result verification through PCE voting; PCE execution initiation; or, FPGA page or segment control signaling. The circuitry of the CCEs of a CCE network can be enhanced as needed to provide additional CVI IC operational services.

The CVI invention allows for the implementation of ICs with circuit device densities that are not presently possible. The CCE network provides a novel means to dynamically allocate and configure BCE and PCE resources in a manner that is uniquely specific to the data or information algorithmic processing requirements versus current fixed microprocessor architectures for example. The CCE network's dynamic or real time BCE and PCE configuration capability provides novel circuit performance advantages when process execution is performed by FPGA circuitry rather than ISP circuitry. The incorporation of FPGA circuitry as one or more PCEs in combination with process [algorithmic] specific BCE and PCE [data path and arithmetic operation] is novel to the CVI ICs.

The Bus Circuit Elements or BCEs are information communication switching means and maybe formed as a single transmission switch circuit structure or a collection of transmission switch circuit sub-structures that can be individually enabled. A BCE has an information communication path, composed of transmission circuitry and interconnections or wires which form physical interconnections between next neighbor BCEs or immediately connected BCEs. The number of BCE communication path interconnections is its communication path width or data path width. A BCE may include fault tolerant circuitry allowing it to configure the use of its specific communication path interconnections. A BCE may be designed as a collection of individually enabled communication path circuit sub-structures increasing the potential yield of an individual BCE should one or more of these communication path sub-structures of the BCE be defective.

The Process Circuit Elements or PCEs are logic or memory circuits that are used to perform the intended data processing or control functions of the CVI IC in conjunction with the BCE CEs. PCEs may be microprocessors, arithmetic processors, ISP, FPGA circuits, register files, processor thread memory files, and ASIC circuits for example.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be further understood from the following description in conjunction with the appended drawing. In the drawing:

FIG. 1 is a top view of a CVI circuit layer.

FIG. 2a is a pictorial view of a vertically redundant CCE network structure as three layers of a CVI IC with the vertical CCE interconnections intentionally elongated for viewing emphasis.

FIG. 2b is a pictorial view of a minimal redundant CCE network structure as two layers of a CVI IC with the vertical CCE interconnections intentionally elongated for viewing emphasis.

FIG. 2c is a schematic cross-sectional view of a CVI IC showing a CCE subnetwork.

FIG. 3 is a pictorial view of a CCE network structure as three layers of a CVI IC with the vertical CCE interconnections intentionally elongated for viewing emphasis.

FIG. 4 is a pictorial view of a CCE network structure of a CVI IC with the vertical CCE interconnections intentionally elongated for viewing emphasis. FIG. 5 is a pictorial view of a CCE network structure of a CVI IC with the vertical CCE interconnections intentionally elongated for viewing emphasis.

FIG. 6 is a pictorial view of a two layer CVI IC with the vertical CCE

interconnections intentionally elongated for viewing emphasis.

FIG. 7 is a cross-sectional view of a CVI IC showing vertical busing structures.

FIG. 8 is a top view of a CVI circuit layer.

FIG. 9 is a cross-sectional view of a CVI IC showing BCE bus structure.

FIG. 10 is a cross-sectional view of a CVI IC showing BCE bus structure.

FIG. 11 is a top view of a BCE bus structure.

FIG. 12 is a top view of a BCE bus structure with transfer data processor.

FIG. 13 is a top view of a multi-port BCE bus structure.

FIG. 14 is a top view of a multi-port BCE bus structure.

FIG. 15 is a cross-sectional view of a vertical transmission line BCE bus structure through multiple CVI circuit layers.

FIG. 15a is a cross-sectional view of a vertical transmission line BCE bus structure through one CVI circuit layers.

FIG. 16 is a cross-sectional view of a vertical transmission line BCE bus structure through multiple CVI circuit layers.

FIG. 16a is a cross-sectional view of a vertical transmission line BCE bus structure through one CVI circuit layers.

FIG. 17 is a top view of a CVI circuit layer with cross-bar BCE.

FIG. 18 is a top view of a CVI circuit layer with cross-bar BCE. FIG. 19 is a top view of a CVI circuit layer with high frequency common vertical interconnection.

FIG. 20 is a top view of a CVI circuit layer with cross-bar BCE with arithmetic PCEs.

FIG. 21 is a top view of a CVI circuit layer with cross-bar BCE with register file, process threads or ISP PCEs.

FIG. 22 is a top view of a CVI circuit layer with high frequency common vertical interconnection.

FIG. 23 is a top view of a CVI circuit layer with high frequency common vertical interconnection.

ADDITIONAL ASPECTS and OBJECTIVES of the CVI INVENTION

It is an aspect and objective of the CVI invention to provide a means to make the yield of a stack integrated circuit independent of the number of circuit layers therein.

It is a further aspect and objective of the CVI invention that a CCE network control the enabling and disabling of all or a plurality of the CEs in a CVI IC.

It is a further aspect and objective of the CVI invention that a CCE enable or disable other CCEs in its network. It is a further aspect and objective of the CVl invention that the CCEs dynamically form a network in order to enable the initial production testing of the CVl IC.

It is a further aspect and objective of the CVl invention that the CCEs dynamically form a network in order to enable the reconfiguration of a CCE network should a CCE of said network fail or develop an operation defect preventing its normal operation.

It is a further aspect and objective of the CVl invention that CCEs can form a network through a wireless means.

It is a further aspect and objective of the CVl invention that CCE networks of a CVl IC can communicate with each other through a wireless means.

It is a further aspect and objective of the CVl invention that CCE networks of a CVl IC can communicate with each other through the I/O external contact pads of the CVl IC.

It is a further aspect and objective of the CVl invention that the CCE network be fault tolerant, reconfigurable and redundant.

It is a further aspect and objective of the CVl invention that CCE networks of a CVl IC can be controlled by an external test means.

It is a further aspect and objective of the CVl invention that CCE networks of a CVl IC can be controlled by an internal test means.

It is a further aspect and objective of the CVl invention that CCE networks of a CVl IC can be controlled by a hardware or software facility of the CVl IC. It is a further aspect and objective of the CVI invention that the CCE network enable the CVI IC to be tested by directed or dynamic selection of subsets BCE and PCE circuit portions.

It is a further aspect and objective of the CVI invention that the CCE network can perform fine grain testing or individualized testing for circuit defects of BCE and PCE CVI circuit portions.

It is a further aspect and objective of the CVI invention that the CCE network can perform fine grain testing or individualized testing for circuit performance of BCE and PCE CVI circuit portions.

It is a further aspect and objective of the CVI invention to enable the fabrication with economically acceptable yields 3D circuits with greater than 10 circuit layers and greater than 0 circuit layers.

It is a further aspect and objective of the CVI invention that the circuit layers of the CVI IC do not require test qualification prior to their use in producing the stacked CVI IC.

It is a further aspect and objective of the CVI invention that the Configuration Control Element circuits are fault tolerant wherein if a CCE of a CCE network should fail the CCE network can be recreated avoiding the defective CCE.

It is a further aspect and objective of the CVI invention that the CCE network can optionally be controlled by an internal CE logic or microprocessor.

It is a further aspect and objective of the CVI invention that the CCE network can enable or disable all of the remaining CEs of the CVI IC. It is a further aspect and objective of the CVI invention that the CCE network can enable or disable a plurality of the CEs of the CVI IC.

It is a further aspect and objective of the CVI invention that a CVI IC can be configured by a CCE network as a means to prevent the use of one or more defective CEs and as a means to raise the operating yield of the CVI IC.

It is a further aspect and objective of the CVI invention that the CVI IC may be composed of CEs that are spares and to be used when a similar CE fails an requires replacement.

It is a further aspect and objective of the CVI invention that the CVI IC may be composed of a plurality of CEs of an identical type all potentially in use by the CVI IC, wherein should one of said CEs fail, it will not be replaced by a spare CE, but its loss will result in reduced capacity of the CVI IC.

It is a further aspect and objective of the CVI invention that a cross-bar bus switch be implemented by a plurality of vertical structured buses or BCEs.

It is a further aspect and objective of the CVI invention to use a vertical interconnect or waveguide for the purpose of providing simultaneous transmissions made at different frequencies within a CVI IC.

It is a further aspect and objective of the CVI invention to use high bandwidth bus communication techniques to connect a plurality of circuit layers having a plurality of microprocessor functions such as ISP, arithmetic function, register file or processor threads. It is a further aspect and objective of the CVI invention to use high bandwidth bus communication techniques to connect a plurality of circuit layers having a plurality of FPGA, arithmetic function, register file or processor threads circuitry

It is a further aspect and objective of the CVI invention to provide process or algorithmic specific data path and arithmetic circuit resource configurations in combined use with FPGA process directed or execution control circuitry.

It is a further aspect and objective of the CVI invention to provide CCE network CVI IC operational process specific support services for dynamic or real time BCE and PCE configuration.

It is a further aspect and objective of the CVI invention ...

DETAILED DESCRIPTION of the CVI INVENTION and PREFERRED

EMBODIMENTS

A primary objective is the CVI invention is to provide methods and means to enhance the yield of 3D or stacked integrated circuits. There is a plurality of preferred embodiments of the CVI invention, a number of which are described herein. A CVI IC is composed of a plurality of circuit layers. Each CVI circuit layer is composed of a set of Circuit Elements [CEs]. The CEs are broadly referred to as Configuration Control Elements [CCEs], Bus Control Elements [BCEs] and Process Circuit Elements [PCEs]. It is not a requirement that the selection set of CEs of a CVI circuit layer comprise all CE types.

FIG. la through FIG. 5 show various potential implementations for the enhanced yield of a CCE network structure. The CCE network used to implement the configuration of the Circuit Elements of the CVI IC.

FIG. 1 shows an example of a CVI circuit layer 1-1. It has four CCEs l-2a, l-2b, 1- 2c, l-2d which are connected to wireless transceivers l-3a, l-3b, l-3c, l-3d, the wireless transceivers are optional if I/O pads 1-4 are used for control and input output access of the first CCE of the CCE network. Interconnects l-7a, l-7b, l-7c, 1- 7d connect CCEs and enable/disable CE circuitry l-5a, l-5b, l-6a, l-6b, l-6c, l-6d. It is a preferred embodiment that only one fully functional CCE is need per CVI circuit layer unless more than one CCE network is established. BCEs l-8a, l-8b are switching circuits for transfer of information between the PECs l-9a, l-9b, l-9c, 1- 9d of the circuit layer 1-1 and other PECs on other circuit layers of the CVI IC. PCEs l-9a, l-9b, l-9c, l-9d are connected to the BCEs by bus signal lines or interconnect wires 1-lOa, 1-lOb, 1-lOc, 1-lOd. BCEs l-9a, l-9b can transfer information between each other over intervening bus interconnections 1-11 on the circuit layer 1-1 and or through the CVI circuit layer to BCEs on a lower circuit layer and or to BCEs on a higher circuit layer of the CVI IC. FIG. 2a shows three CVI circuit layers 2a-la, 2a-lb, 2a-lc in an exploded fashion to help emphasize the vertical interconnections 2a-5a...2a-5h between the CCEs [2a- 3a, 2b-3e, 2a-3i], [2a-3b, 2b-3f, 2a-3j], [2a-3c, 2b-3g, 2a-3k], [2a-3d, 2b-3h, 2a-31] respectively of said CVI circuit layers. There are no BSE and PSE CEs shown. There are four potential CCE networks represented. Four CCE networks can be formed as shown [2a-3a, 2b-3e, 2a-3i], [2a-3b, 2b-3f, 2a-3j], [2a-3c, 2b-3g, 2a-3k], [2a-3d, 2b- 3h, 2a-31; there also could have been a lesser number of potential CCE networks for this CVI IC. There is likely a very high probability that at least one of the four CCE networks will prove to be a defect free CCE network, the yield of a CCE network will depend to a larger degree on the size of the individual CCE. This preferred embodiment of CVI invention as minimum CCE interconnection structure for CCE network formation may prove sufficient for CVI ICs with less than 6 to 8 layers.

FIG. 2b shows two CVI circuit layers 2b-la, 2b-lb in an exploded fashion to help emphasize the vertical interconnections 2b-5a, 2b-5b between the CCEs 2b-3a, 2b- 3c, 2b-3b, 2b-3d respectively of said CVI circuit layers. There are no BSE and PSE CEs shown. There are several potential CCE networks. These CCE networks begin with either first CCE 2b-3a and CCE 2b-3c via direction interconnections 2-5a or first CCE 2-3b and CCE 2b-3d via direct interconnections 2b-5b. If CCE 2b-3a is defective alternate CCE networks consist of first CCE 2b-3b and CCE 2-3d via direct interconnections 2-8b or first CCE 2b-3b and CCE 2b-3c via interconnections 2b-8a & 2b-8b. Interconnections 2b-6a between CCEs on the upper circuit layer 2b- la and interconnections 2b-6b on the lower circuit layer 2b-lb are optional. Either of the first CCEs on circuit layer 2b-la are operationally accessed through I/O contact pads 2b-2 of the upper circuit layer 2b-la or through wireless circuitry 2b-4a & 2b-4b. The CCE network is established by validating a first CCE and then a second CCE. Once a CCE network is established the BCEs and PCEs [not shown] of the circuit layers 2b-la, 2b-lb are tested and validated for functional operation. The BCEs and PCEs of the circuit layers 2b-la, 2b-lb are operationally validated preferably in a step-by-step fashion of one BCE or PCE at a time.

FIG. 2c shows a schematic cross-sectional view of a CVI IC with nine [9] circuit layers 2c-la...2c-li and a CCE sub-network 2c-3a...2c-3e connected at CCE 2c-2d by interconnection 2c-6 of a first CCE network 2c-2a...2c-2e with vertical

interconnections 2c-4a...2c-4e. A CCE sub-network may be used to assist in a selected configuration change to a subset of the CVI IC CEs. The displacement of CCE 2c-2c indicates that the EEC directly inline with 2c-2b and 2c-2d was defective and an alternate CCE was used to replace it. EEC 2c-2c is interconnected by by-pass interconnections 2c-4b and 2c-4c. By-pass interconnections are interconnections that connect two EECs that adjoin an intervening EEC.

FIG. 3 shows three circuit layers 3-la, 3-lb, 3-lc of an CVI IC in a exploded fashion to help emphasize the vertical interconnections 3-6a, 3-6b, 3-6c, 3-6d, 3-6e, 3-6f, 3-6g, 3-6h between four sets of CCEs [3-3a, 3-3e, 3-3i], [3-3b, 3-3f, 3-3j], [3-3c, 3-3g, 3-3k], [3-3d, 3-3h, 3-31]. There are no BSE and PSE CEs shown. The CCE network for the CVI IC is most likely to be formed from these said four sets of CCEs with the first CCE being associated with the top circuit layer 3-la, although this is not a limitation of the CVI invention and any CCE on any layer could. Optional wireless input output means [3-4a...3-41] for each CCE could be used as an alternative to or in conjunction with the circuit layer I/O pads 3-2. BCE and PCE CEs of the CVI IC are not shown. One design embodiment for this CVI IC could have each of CCE on a circuit layer interconnected to the enable circuitry for each BCE and PCE on the same circuit layer. The CCE network is formed by selection and qualification of a first CCE through I/O pad and or wireless means with subsequent CCEs for each circuit layer selected and qualified. In the event that CCE network for this CVI IC was composed of CCEs 3-3b, 3-3e, 3-3i, and CCE 3-3a was the first selected CCE for the CCE network, that would suggest that the CCE 3-3a was determined to be defective and that after selection of CCE 3-3b as the first CCE for the CCE network, CCE 3-32f was determined to be defective. Interconnect CCE by-pass lines 3-7f interconnecting CCEs 3-3b and 3-3e would be used to allow CCE 3-3b to enable CCE 3-3e. Vertical interconnections 3-6e would be used by CCE 3-3e to enable CCE 3-3i. It is a preferred embodiment of the CVI invention that CCE by-pass interconnections are used to avoid or by-pass a defective CCE and connect to a CCE typically on an alternate circuit layer; by-pass interconnections are interconnections that connect two EECs that adjoin an intervening EEC. The use of by-pass interconnections are not required. Interconnections 3-5a...3-51 and 3-7a...3-71 are CCE by-pass interconnections. As examples of CCE by-pass interconnection usage are: CCE bypass interconnection 3-5a interconnects CCEs 3-3a and 3-3h by-passing CCE 3-3d; and, CCE by-pass 3-7a interconnection interconnects CCEs 3-3d and 3-3e by-passing CCE 3-3a. Interconnects 3-6a...3-6d only shown on circuit layer 1-la directly connect adjacent CCEs. The 3-6 interconnection set are optional and can be used as an alternate interconnection versus use of the 3-5 & 3-7 interconnections to form a CCE network, for example the CCE network 3-3a, 3-3h, 3-31 could use

interconnection 3 -6a and vertical interconnection 3-6d rather than interconnection

3- 5a should interconnection 3-5a either be defective or not part of the CVI interconnection design. The inclusion of the 3-5, 3-6 and 3-7 interconnection sets in the design of a CVI IC is a trade off versus the desired yields for the specific CVI IC.

The CVI IC in FIG. 3 can be used for all CVI IC operational modes. It is an example of one of many potential CCE designs intended to provide an enhanced CCE network yield probability.

FIG. 4 shows three circuit layers 4-la, 4-lb, 4-lc of a CVI IC in an exploded fashion to help emphasize the vertical interconnections 4-5a...4-51. CCEs 4-3a...4-3r are connected by interconnections 4-6a...4-6r. There are no BSE and PSE CEs shown. Optional wireless input output means [4-4a...4-4d] could be used as an alternative to or in conjunction with the circuit layer I/O pads 4-2. Interconnections

4- 6a... 4-6r only connect CCEs in the same circuit layer and do not connect CCEs on alternate circuit layers, therefore, if there is a CCE failure in one of the potential vertically connected CCE networks [4-3a, 4-3g, 4-3m], [4-3b, 4-3h, 4-3n], [4-3c, 4-3i, 4-3o], [4-3d, 4-3j, 4-3p], [4-3e, 4-3k, 4-3q], [4-3f, 4-31, 4-3r] an alternate CCE will have to be used in the same circuit layer as the defective EEC, but also because of the only interconnections are CCE to CCE interconnections and there are no by-pass interconnections, a addition CCE in the layer preceding the defective CCE will be needed as a means to provide connective path to the alternate EEC. As an example if only CCE 4-3g were defective in the potential CCE network of 4-3a, 4-3g, 4-3m, then the resulting CCE network would be 4-3a, 4-3b, 4-3h, 4-3n, wherein 4-3b would serve as a connective means between CCEs 4-3a and 4-3h.

The C VI IC in Figure 4 can be used for all CVI IC operational modes. It is an example of one of many potential CCE designs intended to provide an enhanced CCE network yield probability.

Figure 5 shows three circuit layers 5-la, 5-lb, 5-lc of a CVI IC in an exploded fashion to help emphasize the vertical interconnections 5-5a...5-5h. CCEs 5-3a...5- 3p are connected by interconnections 5-6a...5-6h. There are no BSE and PSE CEs shown. Optional wireless input output means [5-4a...5-4d] could be used as an alternative to or in conjunction with the circuit layer I/O pads 5-2. The

interconnections for the CCEs are so designed that any CCE network would be on one side of the CVI IC or the other. This is the case due the limited use of by-pass interconnections as shown in Figure 5; there are no interconnections for CCEs in the same circuit layer. This design of CCEs could limits the CCE network of the CVI IC to one of the two separated sides of the CVI IC or two CCE networks could be created for configuring CEs, one for each side of the CVI IC. If two CCE networks were created, these CCE networks could be controlled through the i/O pads 5-2, wireless means 5-4a...5-4d or though use of a CE of control logic such as a microprocessor that provides interconnections to both CCE networks.

The CVI IC in Figure 5 can be used for all CVI IC operational modes. It is an example of one of many potential CCE designs intended to provide an enhanced CCE network yield probability.

FIG. 6 shows two circuit layers 6- la, 6- lb of a CVI IC in an exploded fashion to help emphasize the vertical interconnections 6-10a...6-10d. CCEs 6-3a...6-3h are interconnected 6-5a...6-5d, 6-8a, 6-8b; these CCE interconnections are coplanar interconnections used for CCE network formation. Optional wireless input output means [6-4a...6-4h] could be used as an alternative to or in conjunction with the circuit layer I/O pads 6-2. BCEs 6-9a...6-9d are enabled by CCE control circuitry 13a...13d and connect to CEs 6-lla, 6-llb via busing lines 6-12a...6-12d. The CEs 6- 11a, 6-llb are enabled for operation via interconnections 6-7a„,-6-7d and CCE control circuitry associated with the CEs 6-lla, 6-llb and not shown.

The CVI IC in Figure 6 can be used for all CVI IC operational modes. It is an example of one of many potential CVI designs intended to provide an enhanced CVI IC yield probability.

FIG. 7 shows a plurality of circuit layers 7-la, 7-lx of a CVI IC 7-1 in cross-section showing BCEs vertically interconnected 7-5a...7-5c. BCEs 7-3a...7-c are connected respectively to an adjoining BCE by vertical busing interconnections 7-4a...7-4c. The BCEs may be configurable or non-configurable, and are preferably enabled for use by a CCE network. There are three vertical bus assemblies that connect to all layers of the CVI IC 7-51, 7-5b, 7-5c. Each circuit layer will likely have one or more CEs such as shown in FIGs. 1, 8 & 19-24. The use of three vertical bus assemblies is intended to provide CVI IC yield enhancement and high bus bandwidth. The BCEs used in each bus assembly can comprises a single set of bus line transceivers or configurable BCE wherein the yield of the BCE is higher because it does not have a single point of failure that would prevent the use of the BCE.

FIG. 8 shows the top view of a CVI circuit layer 8-1. There are four CCEs 8-2a...8- 2d; CCE interconnections and CE control circuitry are not shown. There are six BCEs 8-3a...8-3f. The BCEs are connected by bus interconnections 8-4a...8-4d. There are four PCEs 8-5a...8-5d. The BCEs are connected to PCEs by

interconnections 8-6a...8-6h. Each PCE has four bus ports connecting to four different BSEs. This connection density provides for higher yield CVI IC yield and higher bus bandwidth or circuit performance. A defective BCE or PCE would be disabled by the CCE network.

The BCEs of the circuit layer in Figure 8 can be used as providing circuit communication bandwidth should none of them be defective, and as a

communication resource that can provide sufficient intra-IC communication should one or even a plurality of BCEs prove to be defective. Each BCE can be disabled via an CCE and isolated from the other circuitry of the circuit layer 8-1 and in the preferable embodiment small in area, therefore, the yield of each BCE is

independent of the adjoining circuitry of the circuit layer. The various BCEs of the circuit layer are also connected in a vertical manner as shown in Figure 7 with other BSEs. Each BCE and PCE 8-5a...8-5d are preferably small in area and electrically isolatable via a CCE, and due to this reason will have higher individual yield probability distribution than the yield of the BSEs if taken as integrated whole. In order to yield a CVI IC, any defective BCE or PCE must not be a single point circuit resource the loss of which is indispensible.

FIG. 9 and FIG. 10 are cross-sections of CVI ICs 9-1 10-1 showing portions of several vertical bus structures. Figure 9 shows CVI IC 9-1 comprising circuit layers 9-2a...9-2j and two vertical BSE bus structures 9-3a, 9-3b each composed of BSEs with vertical interconnections such as 9-4 & 9-5 respectively; other CCE and PCE CEs are not shown. Figure 10 shows CVI IC 10-1 comprising circuit layers 10- 2a...10-21 and five vertical BCE bus structures 10-3a...l0-3e each composed of BCEs with vertical interconnections such as 10-4 & 10-5 respectively; other CCE and PCE CEs are not shown. Each bus structure is composed of some number isolatable BCEs and are not limited to placement. The BSE circuit design used may be one of many possible designs, however, the preferable BCE circuit embodiment is one that does not have a design wherein a single circuit defect will prevent the use of the BCE, but rather the BSE design has fault tolerant features or is configurable wherein the defect can be isolated and the BSE can be used with diminished resource capacity. Additionally, Figures 9 and 10 are intended to show is that the BSE bus structures of the CVI invention are numerous and do not require significant circuit layer surface areas to be implemented. This is novel to the CVI invention in that using a plurality of vertical BSE structures, preferably more than two, increases both the communication or information transfer bandwidth performance of the CVI IC but also its potential yield.

FIG. 11 through FIG. 18 show BCE bus circuitry structures from minimal complexity to much greater complexity. These BCEs are all vertically

interconnected, have horizontal interconnections to other potential BSEs and PSEs per circuit layer, and include various yield enhancement techniques in addition to being enabled by a CCE.

FIG. 11 shows a BCE 11-1 with bus circuitry 11-2 for control of both vertical through circuit layer busing interconnections [vertical bus transmission lines] 11 -2a integral to the bus circuitry 11-2 and horizontal busing interconnections 11-4

[horizontal bus transmission lines], and provide such functions as transmission line arbitration or messaging control, buffering and or caching. The bus circuitry 11-2 may provide support for partitioning of the bus transmission lines and the selection for use of said bus transmission line partition. The bus circuitry 11-2 is adjacent and integrated with CCE bus circuitry 11-3. The CCE bus circuitry is connected to a CCE preferably on the same circuit layer and may have a plurality of functions in addition to the function of enabling or disabling the operation of the BSE. The CCE bus circuitry 11-3 may provide Error Correction Code processing, bus data buffering and queuing, message routing address lookup and bus use arbitration, but is not limited to these functions.

FIG. 12 shows a BCE 12-1 with bus circuitry 12-2 for control of both vertical through circuit layer busing interconnections [vertical bus transmission lines] 12-2a integral to the bus circuitry 12-2 and horizontal busing interconnections [horizontal bus transmission lines] 12-4, and provide such functions as transmission line arbitration or messaging control, buffering and or caching. The bus circuitry 12-2 may provide support for partitioning of the bus transmission lines and the selection for use of said bus transmission line partition. The bus circuitry 12-2 is adjacent and integrated with CCE bus circuitry 12-3. The CCE bus circuitry is connected to a CCE preferably on the same circuit layer and may have a plurality of functions in addition to the function of enabling or disabling the operation of the BCE. The CCE bus circuitry 12-3 may provide Error Correction Code processing, bus data buffering and queuing, message routing address lookup and bus use arbitration, but is not limited to these functions. The bus circuitry 12-5 is adjacent and integrated with CCE bus circuitry 12-3 and may provide such yield enhancement functions as defective byte or word reordering or substitution, bus line data shifting.

The BCE can be used to form a plurality of bus networks that operate separately of each other or are connected in some manner. The communication architecture of a 3D IC can have a significant impact on the overall performance of the IC. The BCE of the CVI invention can vary greatly in bandwidth or transmission capacity and can operate at least as an arbitrated continuous transmission line bus or a message passing point-to-point bus. The advantages of 3D integration do not require the high drive power electronic necessary to achieve high performance, this allows the CVI BCE to offer high circuit switching performance and much greater transmission capacity than current state-of-the-art external bus architectures implemented with discrete packaged circuitry and PCB [Printed Circuit Board] methods.

FIG. 13 shows a multi-port BCE 13-1 with bus control circuitry 13-2, vertical through circuit layer busing interconnections [vertical bus transmission lines] 13- 10a...l3-13e comprising four bus banks each dual ported with interconnections 13- 5a 13-5b and switch circuitry [bus channels] 13-6a...l3-9e, and four ported horizontal busing interconnections 13-4a...l3-4d [horizontal bus transmission lines or paths]. CCE bus circuitry 13-3 is connected to a CCE on the circuit layer and enables or disables the circuitry of the BCE 13-1. The bus controller circuitry 13-2 provides such functions as transmission line arbitration or messaging control error correction codes, transmission line switching, and or caching, but it not limited to such functions.

The BSE 13-1 shown in FIG. 13 indicates a significant redundant or fault tolerant capability, a high bandwidth capacity and a small surface area or foot print are for its implementation; the through circuit layer bus interconnections are sub-micron pitch and preferably sub-half micron pitch. The bus switch circuitry 13-6a...l3-9e preferably can be individually disabled by the bus controller circuitry 13-2 or CCE bus circuitry 13-3, this allows the BCE to continue to operate in a diminished capacity, and is a fault tolerant capability of the C VI IC. The cost in circuit layer area is small for the addition of a bus channel with 256 or 512 vertical transmission lines, and therefore, having a larger number of such BCE bus channels provides both to the fault tolerance and the performance of the BCE.

FIG. 14 shows a multi-port BCE 14-1 with bus control circuitry 14-2, vertical through circuit layer busing interconnections [vertical bus transmission lines] 14- 8a...l4-9c comprising two banks each dual ported with interconnections 14-5a 14- 5b and switch circuitry [bus channels] 14-6a...l4-7c, and two ported horizontal busing interconnections 14-2a 14-2b [horizontal bus transmission lines or paths], CCE bus circuitry 14-3 is connected to a CCE on the circuit layer and enables or disables the circuitry of the BSE 14-1. The bus controller circuitry 14-2 provides such functions as transmission line arbitration or messaging control error correction codes, transmission line switching, and or caching, but it not limited to such functions.

The BSE 14-1 shown in FIG. 14 provides a significant redundant or fault tolerant capability, a high bandwidth capacity and a small surface area or foot print are for its implementation; the through circuit layer bus interconnections are sub-micron pitch and preferably sub-half micron pitch. The bus switch circuitry 14-6a...l4-7c preferably can be individually disabled by the bus controller circuitry 14-2 or CCE bus circuitry 14-3, this allows the BCE to continue to operate in a diminished capacity, and is a fault tolerant capability of the C VI IC. The cost in circuit layer area is small for the addition of a bus channel with 256 or 512 vertical transmission lines, and therefore, having a larger number of such BCE bus channels provides both to the fault tolerance and the performance of the BCE.

If a single BCE of a vertical BCE bus structure like those shown in Fig. 9 and Fig. 10 is defective and has been disabled by the CCE of the circuit layer it is on, this may affect the use of the vertical busing interconnections for the other BCEs to which the defective BCE is connected. Fig. 15 shows vertical busing interconnections 15-1 that can be used to by-pass a defective BCE. This adds fault tolerant capability to the affected vertical BCE bus structure. Fig. 15 shows the vertical interconnection routing pattern for a single vertical interconnection for by-passing a disabled defective BCE where ever it may occur in the vertical BCE bus structure. The bypass interconnection is position independent of the placement of the circuit layers 15-2a...l5-2d. The vertical interconnection 15-3 is a continuous interconnection and should not be affected by a defective BCE if it is disabled. Interconnection 15-4 is a point-to-point bus interconnection and would be affected if the BCE circuitry 15- 6 were defective. Should that defect occur, then interconnection 15-5 would be enabled to route around the disabled BCE and providing a point-to-point transfer from the BCE below the defective BCE to the BCE above the defective BCE. A single circuit layer with the BCE interconnection pattern for routing past a defective BCE is shown in Fig. 15a. The circuit layer 15a-l comprises a transistor device layer 15a-2 with BCE circuit devices 15a-3a 15a-3b formed therein.

Continuous bus interconnection 15a-4 passes completely through the circuit layer 15a-l. Point-to-point bus interconnection 15a-5 connects the BEC circuit devices to the underside of the BCE circuit devices in the above circuit layer and would be affected should the BCE circuit devices 15a-3a be defective and disabled. BCE bus interconnection 15a-6 provides an interconnection from the BCE in the circuit layer directly below to the 15a-5 interconnection and completing a transmission path bypassing the defective BCE. The interconnection 15a-7 would be used to by-pass a defective BCE that is in the circuit layer immediately above a BCE.

If two immediately adjacent BCEs of a vertical BCE bus structure like those shown in Fig. 9 and Fig. 10 are defective and have been disabled by the CCE of the respective circuit layers they are on, this may affect the use of the vertical busing interconnections for the other BCEs to which these defective BCEs are connected. Fig. 16 shows vertical busing interconnections 16-1 that can be used to by-pass two adjacent defective BCEs. This adds fault tolerant capability to the affected vertical BCE bus structure. Fig. 16 shows the vertical interconnection routing pattern for vertical interconnections for by-passing two disabled BCEs where ever they may occur in the vertical BCE bus structure. The by-pass interconnection is position independent of the placement of the circuit layers 16-2a...l6-2d. The vertical interconnection 16-3 is a continuous interconnection and should not be affected by a defective BCE if it is disabled. Interconnection 16-4 is a point-to-point bus interconnection and would be affected if adjoining BCE circuitry 16-6 were defective. Should such defects occur, then interconnection 16-5 & 16-7 would be enabled to route around the disabled BCEs and providing a point-to-point transfer from the BCE below the defective BCEs to the BCE above the defective BCEs.

A single circuit layer with the BCE interconnection pattern for routing past two defective BCEs is shown in Fig. 16a. The circuit layer 16a-l comprises a transistor device layer 16a-2 with BCE circuit devices 16a-3a 16a-3b 16a-3c formed therein. Continuous bus interconnection 16a-4 passes completely through the circuit layer 16a-l. Point-to-point bus interconnection 16a-5 connects the BCE circuit devices to the underside of the BCE circuit devices in the above circuit layer and would be affected should the BCE circuit devices 16a-3a be defective and disabled. BCE bus interconnection 16a-6 provides an interconnection from the BCE in the circuit layer directly below to the 16a-5 interconnection and completing a transmission path bypassing the defective BCE. The interconnection 16a-7 would be used to by-pass a defective BCE that is in the circuit layer immediately above a BCE. The

interconnection 16a-8 provides an interconnection between the BCE two layers lower and the BCE immediately above. The interconnection 16a-9 provides an interconnection between the BCE one layer lower and the BCE two layers immediately above. The interconnection 16a-10 connects the BCE device circuitry 16a-3c to BCE three layers above by-passing the two immediate layers above the circuit layer 16a-l. The number of circuit layers shown in the various figures presented herein does not suggestion any limitations on the number of circuit layers of a CVI IC, wherein such CVI stacked integrated circuits can comprise any number of circuit layers such as 10, 30, 50 or more circuit layers.

CVI BCE and NOVEL CVI BUS STRUCTURE EMBODIMENTS

A vertical BCE bus structure consists primarily of CVI Bus Circuit Elements [BCEs] interconnected vertically to each other by a continuous plurality of busing interconnections [transmission paths] or vertically by a non-continuous point-to- point plurality of busing interconnections the vertical path composed of vertical wire segments that interconnect each BCE as shown in Fig. 15 and Fig.16. BCE have horizontal interconnects to BCEs of other BCE bus structures and PCEs [Processing Circuit Elements]. A CVI bus structures can operate as a continuous or point-to- point information transfer means for implementing a plurality of data and or message transfer protocols. The BCE bus structures can be multi-channel and multi- ported with channel information or data-widths that can vary up to several thousand bits wide per transfer. The BCE device circuitry can also operate at very high switching speeds consistent with the potential transistor performance that BCE is implemented. The coupling of wide bus channel data widths and high BCE device circuit performance allows CVI IC information transfer rates to exceed 10 ¹² bytes/s. The CVI IC invention allows for the novel implements other high performance bus structures. Cross-bar buses and common conductor buses are two examples.

Bus cross-bar buses implemented as an assembly of a plurality of ICs and interconnected by a PCB [Printed Circuit Board] are in common use today. Such cross-bar buses at the system level of integration provide a means to immediate and non-blocking connection among a large number of processing units for example. Cross-bars implemented in this manner are planar due to the high number of interconnections making up the various row and column buses of the cross-bar; this means the cross-bar is limited in area to one PCB. Cross-bars can be implemented without this limitation as 3D structures in CVI invention in a plurality of possible implementations. Fig. 17 and Fig. 18 show potential equivalent cross-bar bus structures of the CVI invention.

Fig. 17 shows a circuit layer 17-1 of a CVI IC. The circuit layer 17-1 comprises CCEs 17-2a...l7-2d BCEs 17-3a 17-3b, PCEs 17-4a...l7-4d, cross-bar BCEs 17- 5a...l7-5d, CCE interconnections to CEs 17-6a...l7-6f, BCE bus interconnections 17- 7a 17-7b, and cross-bar BCE interconnections 17-8. The cross-bar BCE

interconnections show multiple BCE ports and PCE ports with each PCE connected to each other PCE of the circuit layer 17-1 through the cross-bar PCEs in a redundant or multiple path 17-8 manner. The PCEs of each additional CVI circuit layer are vertically interconnected to the PCEs 17-4a...l7-4d by the cross-bar BCEs and by providing a sufficient number of bus channels to the cross-bar BCEs a non- blocking transfer path for each PCE can be attempted with the addition of ever larger numbers of PCEs. This cross-bar BCE capacity structure for large numbers of PCEs may not be implementable with conventional PCB means and typically is fixed in the number of processing elements it can accommodate. The CVI cross-bar BCE does not have to be designed for a specific number of PCEs, but a maximum wherein the maximum is reached by the addition of PCEs through the addition of CVI circuit layers. The cross-bar BCE also offers the unique advantage of local pulling of PCE information transfers at the CVI circuit layer. The variable cross-bar capacity is novel to the CVI, and only economically possible with the CVI high yield

enhancement methods and means. Preferably all of the BCEs and PCEs of this circuit layer can be individually disabled by a CCE network if so desired without affecting the continued operation of the circuit layer.

The cross-bar BCEs are preferably BCE circuitry designed and used to provide a plurality of switched bus channels to a plurality of PCEs for a plurality of CVI circuit layers, preferably wherein there are an adequate number bus channels such that an information transfer between any two PCEs can occur without a delay, also referred to as a non-blocking transfer. This non-blocking cross-bar like performance of the cross-bar BCEs 17-5a...l7-5d are can be adjusted for greater transfer capacity be adding bus channels to each of the BCEs, this has the effect of providing more non- blocking information transfer bandwidth, but also provides for higher CVI IC yields by making the loss of one or more bus channel from one of the cross-bar BCEs less likely to lower the cross-bar BCEs minimum acceptable circuit performance. The distances between all PCEs and their communication network of BCEs can be measured in microns.

Fig. 18 shows another cross-bar BCE structure. Fig. 18 shows a different placement of the busing structures. This placement is intended to show the design flexibility of the CVI cross-bar BCE in relationship to all other cross-bar bus structures.

Fig. 18 shows a circuit layer 18-1 of a CVI IC. The circuit layer 18-1 comprises CCEs 18-2a...l7-2d, BCEs 18-3a...l8-3d, PCEs 18-4a...l7-4d, cross-bar BCEs 18-5a 18-5b, CCE interconnections to CEs 18-6a...l8-6d, BCE bus interconnections 18-7a 18-7b, and cross-bar BCE interconnections 18-8. The cross-bar BCE

interconnections show multiple BCE ports and PCE ports with each PCE connected to each other PCE of the circuit layer 18-1 through the cross-bar PCEs in a redundant or multiple path 18-8 manner. . The PCEs of each additional CVI circuit layer are vertically interconnected to the PCEs 18-4a...l8-4d by the cross-bar BCEs and by providing a sufficient number of bus channels to the cross-bar BCEs a non- blocking transfer path for each PCE can be attempted with the addition of ever larger numbers of PCEs. Preferably all of the BCEs and PCEs of this circuit layer can be individually disabled by a CCE network if so desired without affecting the continued operation of the circuit layer. The CVI cross-bar bus structures provides unique performance, bandwidth capacity and power dissipation advantages over current cross-bar circuitry. The CVI cross-bar bus structures can provide a greater density point-to-point or non- blocking interconnection structure for processing and memory circuitry [PCEs] than is possible with the current state-of-the-art methods. This claim derives its support from the integration of the cross-bar bus elements with PCEs per circuit layer, the vertical interconnection density efficiency of the BCE allowing high numbers of bus channels, and the ability to yield high densities of PCEs achieved by CVI 3D integration methods.

Fig. 19 shows a top view of a CVI circuit layer using multiple high frequency serial electronic or optical transmission lines 19-6a 19-6b connected to a common vertical interconnect transmission or waveguide means 19-8. This novel aspect of the CVI invention implements point-to-point high speed information transmission over a common vertical interconnection means or waveguide. High frequency electronic or optical transmissions are sent from one PCE to another PCE at specific [filtered] transmission a frequency allowing a plurality of PCE to PCE transmissions to occur simultaneously over a common connection 19-8 each at different transmission frequencies. One or a plurality of high frequency dependent serial transmission interconnections connect each of a plurality of PCEs by connecting first to a vertical waveguide or interconnection 19-8 connecting some number of circuit layers and serving as a common connection with each PCE sending and receiving pair using a select frequency. The selection of transmission frequency per PCE pair may be dynamic or proscribed by a lookup table, potentially making of said lookup table is derived and dependent on the CCE network generated configuration database. This method and apparatus of information transfer within the CVI IC is similar in effect to a cross-bar bus structure, but requires less bus circuitry to implement and has the potential to be architecturally simpler than the CVI cross-bars presented in Fig. 17 and Fig. 18.

The CVI circuit layer 19-1 in Fig. 19 comprises CCEs 19-2a...l9-2d, BCEs 19- 3a...l9-3d, PCEs 19-4a...l9-4f, high frequency filtered serial transceivers 19-5a...l9- 51, high frequency serial transmission lines 19-6a 19-6b, BCE interconnections 19-7, and vertical common high frequency interconnection 19-8. Preferably all of the BCEs and PCEs of this circuit layer can be individually disabled by a CCE network if so desired without affecting the continued operation of the circuit layer.

Fig. 20 shows a top view of a CVI circuit layer 20-1 using a distributed cross-bar bus structure 20-8a 20-8b 20-8c. The PCEs 20-4a...20-4d are arithmetic or numerical processing circuits providing such functions as multiply, add and divide. A plurality of layers 20-1 can be used to form a dense array of such circuits for applications that require large amounts of data to be processed in a proscribed sequence of arithmetic operations. Fig. 21 shows a top view of a CVI circuit layer 21-1 intended to be stacked with the circuit layer[s] 20-1, wherein the size of and the placement of the vertical BCE interconnections align. The circuit layer 21-1 may comprise PCEs that are ISPs, FPGAs, register files or process context memory relating to processor threads. This separation of the basic microprocessor elements lends the smaller PCEs to have higher potential yield and at the same time allows what would normally be circuit functions with access restricted to the architecture of microprocessor to be shared on an as needed basis. This flexibility of PCE utilization due to the breakup of the traditional microprocessor architecture into multiple CEs is unique to the CVI invention, allows for higher CE utilization, and the implementation of software programs [algorithms] that more closely reflect their operational and data flow structures, and therefore, result in more timely execution performance. The implementation of said proscribed sequences of algorithmic arithmetic operations can be further enhanced by using CCE network services to configure the cross-bar bus channels to direct the flow of data between PCEs consistent with the data processing required.

The CVI circuit layer 20-1 in Fig. 20 comprises CCEs 20-2a...20-2d, BCEs 20- 3a...20-3d, PCEs 20-4a...20-4f, cross-bar BCE transmission lines 20-6a 20-6b, BCE to BCE interconnections 20-7, and cross-bar BCEs 20-8a...20-8c. Preferably all of the BCEs and PCEs of this circuit layer can be individually disabled by a CCE network if so desired without affecting the continued operation of the circuit layer.

The CVI circuit layer 21-1 in Fig. 21comprises CCEs 21-2a...21-2d, BCEs 21- 3a...21-3d, PCEs 21-4a...21-4f, cross-bar BCE transmission lines 21-6a 21-6b, BCE to BCE interconnections 20-7a 21-7b, and cross-bar BCEs 21-8a...21-8c. Preferably all of the BCEs and PCEs of this circuit layer can be individually disabled by a CCE network if so desired without affecting the continued operation of the circuit layer.

Fig. 22 shows a top view of a CVI circuit layer 22-1 using a frequency dependent interconnections 22-6a 22-6b and common vertical electronic or optical

interconnection or waveguide 22-9. The PCEs 20-4a...20-4f are arithmetic or numerical processing circuits providing such functions as multiply, add and divide. A plurality of layers 22-1 can be used to form a dense array of such circuits for applications that require large amounts of data to be processed in a proscribed sequence of arithmetic operations. Fig. 23 shows a top view of a CVI circuit layer 23-1 intended to be stacked with the circuit layer[s] 22-1, wherein the size of and the placement of the common vertical interconnection align. The circuit layer 23-1 may comprise PCEs that are ISPs, FPGAs, register files or process context memory relating to processor threads. This separation of the basic microprocessor elements lends the smaller PCEs to have higher potential yield and at the same time allows what would normally be circuit functions with access restricted to the architecture of microprocessor to be shared on an as needed basis. This flexibility of PCE utilization due to the breakup of the traditional microprocessor architecture into multiple CEs is unique to the CVI invention, allows for higher CE utilization, and the implementation of software programs [algorithms] that more closely reflect their operational and data flow structures, and therefore, result in more timely execution performance. The implementation of said proscribed sequences of algorithmic arithmetic operations can be further enhanced by using CCE network services to configure the cross-bar bus channels to direct the flow of data between PCEs consistent with the data processing required.

The CVI circuit layer 22-1 in Fig. 22 comprises CCEs 22-2a...22-2d, BCEs 22- 3a...22-3d, PCEs 22-4a...22-4f with integrated high frequency filtered serial transceivers, high frequency serial transmission lines 22-6a 22-6b, BCE

interconnections 22-7, BCE high frequency serial transmission lines 22-8a 22-8b, and vertical common high frequency interconnection 22-9. Preferably all of the BCEs and PCEs of this circuit layer can be individually disabled by a CCE network if so desired without affecting the continued operation of the circuit layer.

The CVI circuit layer 23-1 in Fig. 23 comprises CCEs 23-2a...23-2d, BCEs 23- 3a...23-3d, PCEs 23-4a...23-4fl with integrated high frequency filtered serial transceivers, high frequency serial transmission lines 23-6a 23-6b, BCE

interconnections 23-7a...23-7c, BCE high frequency serial transmission lines 23-8a 23-8b, and vertical common high frequency interconnection 23-9. Preferably all of the BCEs and PCEs of this circuit layer can be individually disabled by a CCE network if so desired without affecting the continued operation of the circuit layer.

FAULT TOLERANT and High AVAILABLILITY SYSTEMS CVI ICs can form Fault Tolerant and High Availability ICs. For the purpose of this discussion, Fault Tolerant circuits are those circuits that can have one or more unrecoverable defects in its circuitry that are the result of its manufacture or may develop over the useful life of the circuit that can be preferably electronically isolated in a manner that said defects have no affect on the accuracy of its continued operation or its economic utility. For the purpose of this discussion, High

Availability circuits are circuits with the attributes of Fault Tolerant circuits, but in addition the ability to detect an unrecoverable circuit failure during its normal operation, correct for the circuit failure and continue operation in a transparent manner to the task or process it was performing.

FPGA and memory circuit structures often lend themselves inherent, or designed in or natural fault tolerant facilities.

This disclosure is illustrative and not limiting; further modifications will be apparent to one skilled in the art in light of this disclosure and the appended claims.