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Title:
CONSTRUCTION OF LDPC CONVOLUTIONAL TURBO CODES
Document Type and Number:
WIPO Patent Application WO/2018/184672
Kind Code:
A1
Abstract:
The present invention relates to a device – a seed matrix generator – and a corresponding method, both configured to generate a seed matrix that is arranged to be used for encoding an information and/or for decoding an encoded information, wherein the seed matrix generator is arranged to generate the seed matrix based on at least one low-density parity-check convolutional code, LDPC-CC. The seed matrix is, according to an embodiment, a seed matrix of a LDPC convolutional turbo code, LDPC-CTC. Further, the present invention relates to an encoding device and a corresponding method, both configured to encode information by use of the seed matrix, an to a decoding device and a corresponding method, both configured to decode information by use of the seed matrix.

Inventors:
CANNALIRE, Giacomo (Munich, 80992, DE)
MANFREDI, Marco (Munich, 80992, DE)
MAZZUCCO, Christian (Munich, 80992, DE)
Application Number:
EP2017/058107
Publication Date:
October 11, 2018
Filing Date:
April 05, 2017
Export Citation:
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Assignee:
HUAWEI TECHNOLOGIES CO., LTD. (Huawei Administration Building Bantian Longgang District, Shenzhen, Guangdong 9, 518129, CN)
CANNALIRE, Giacomo (Munich, 80992, DE)
International Classes:
H03M13/11
Foreign References:
US20160173132A12016-06-16
EP2211469A12010-07-28
Other References:
CHO JUNHO ET AL: "Construction of protographs for large-girth structured LDPC convolutional codes", PROC. 2015 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS (ICC), IEEE, 8 June 2015 (2015-06-08), pages 4412 - 4417, XP033199123, DOI: 10.1109/ICC.2015.7249017
Attorney, Agent or Firm:
KREUZ, Georg (Huawei Technologies Duesseldorf GmbH Riesstr. 8, Munich, 80992, DE)
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Claims:
CLAIMS

1. A seed matrix generator to be used for encoding an information and/or for decoding an encoded information, wherein the seed matrix generator is arranged to generate a seed matrix, the seed matrix being a binary parity check matrix of at least one low-density parity-check convolutional code, LDPC-CC. 2. The seed matrix generator according to claim 1, further configured to:

mask a full exponent matrix of rate R with the generated seed matrix of a rate

R; and

expand the masked full exponent matrix with a spreading matrix to generate a cycle-free binary parity check matrix. 3. The seed matrix generator according to claim 1 or 2, wherein the seed matrix generator is arranged to generate the seed matrix by:

generating w auxiliary seed matrices for w parallel LDPC-CCs, wherein each one of the w auxiliary seed matrices is generated for one of the w parallel LDPC-CCs, wherein w is a positive integer; and

interlacing the generated w auxiliary seed matrices of the w parallel LDPC- CCs to generate the seed matrix of the LDPC-CTC. 4. The seed matrix generator according to claim 3, wherein:

for each j-th auxiliary seed matrix, j being a positive integer that is smaller than w, a parity sequence of a j-th auxiliary seed matrix of a j-th LDPC-CC is input as information sequence in a (j+l)-th auxiliary seed matrix of a (j+l)-th LDPC-CC; and each LDPC-CC of the w LDPC-CCs is generated with a corresponding code rate Rp that is different from the code rates of the further LDPC-CCs of the w LDPC- CC, wherein β is a positive integer and

5. The seed matrix generator of claim 4, wherein the corresponding code rate Rp is

determined by the following equation:

wherein the information is a sequence of information bits and b is a number of the information bits of the sequence, and wherein the encoded information is a sequence of encoded bits and c is a number of the encoded information bits. 6. The seed matrix generator according to any one of the preceding claims 3 to 5, wherein the seed matrix generator is configured to execute the interlacing by arranging rows of matrices of the w LDPC-CC codes as rows of the seed matrix of the LDPC-CTC. 7. The seed matrix generator according to any one of the preceding claims 3 to 6, wherein the seed matrix generator is configured to execute the interlacing by arranging consecutively all i-th rows of the w LDPC-CC codes as rows in the seed matrix of the LDPC-CTC, wherein i is a positive integer and is less than or equal to the number of rows of a LDPC-CC code of the w LDPC-CC codes. 8. The seed matrix generator according to claim 7,wherein the i-th rows of the w LDPC- CC codes are followed by consecutively arranged i+l-th rows of the w LDPC-CC codes in the seed matrix of the LDPC-CTC. 9. A seed matrix generation method to be used for encoding an information and/or for decoding an encoded information, wherein the seed matrix generation method comprises generating a seed matrix, the seed matrix being a binary parity check matrix of at least one low-density parity-check convolutional code, LDPC-CC. 10. An encoding device arranged to execute an encoding of an information being a

sequence of information bits, said encoding device comprising a seed matrix generator configured to generate a seed matrix that is arranged to be used for the encoding of the information and being a seed matrix generator according to any one of claims 1 to 8. 1 1. The encoding device according to claim 10, wherein the encoding device further

comprises:

an exponent parity check matrix generator configured to generate an exponent parity check matrix, wherein an initial exponent parity check matrix is masked by the seed matrix to generate the exponent parity-check matrix; and an encoder configured to encode the information by use of the generated exponent parity check matrix.

12. An encoding method configured to execute an encoding of an information being a sequence of information bits, said encoding method comprising a step of seed matrix generation for generating a seed matrix that is arranged to be used for the encoding of the information, and said step of seed matrix generation being executed by use of the seed matrix generation method according to claim 9.

13. The encoding method according to claim 12, wherein the encoding method further comprises:

a step of exponent parity check matrix generation for generating an exponent parity check matrix, wherein an initial exponent parity check matrix is masked by the seed matrix to generate the exponent parity-check matrix; and

a step of encoding the information by use of the generated exponent parity check matrix.

14. A decoding device arranged to execute a decoding of an encoded information being a sequence of encoded information bits, said decoding device comprising a seed matrix generator configured to generate a seed matrix that is arranged to be used for the decoding of the information and being a seed matrix generator according to any one of claims 1 to 8.

15. The decoding device according to claim 14, wherein the decoding device further

comprises:

an exponent parity check matrix generator configured to generate an exponent parity check matrix, wherein an initial exponent parity check matrix is masked by the seed matrix to generate the exponent parity-check matrix;

a binary parity-check matrix generator configured to generate a binary parity- check matrix, wherein the binary parity-check matrix is obtained by expanding the generated exponent parity-check matrix by means of a spreading matrix; and

a decoder configured to decode the encoded information by use of the binary parity-check matrix.

16. The decoding device according to claim 15, wherein the spreading matrix is a cyclic permutation matrix of an identity matrix.

17. A decoding method configured to execute an decoding of an encoded information being a sequence of encoded information bits, said decoding method comprising a step of seed matrix generation for generating a seed matrix that is arranged to be used for the decoding of the encoded information, and said step of seed matrix generation being executed by use of the seed matrix generation method according to claim 9.

18. The decoding method according to claim 17, wherein the decoding method further comprises:

a step of exponent parity check matrix generation for generating an exponent parity check matrix, wherein an initial exponent parity check matrix is masked by the seed matrix to generate the exponent parity-check matrix;

a step of binary parity-check matrix generation for generating a binary parity- check matrix, wherein the binary parity-check matrix is obtained by expanding the generated exponent parity-check matrix by means of a spreading matrix; and

a step of decoding for decoding the encoded information by use of the binary parity-check matrix.

19. The decoding method according to claim 18, wherein the spreading matrix is a cyclic permutation matrix of an identity matrix.

20. A computer program product including code for performing the steps on the seed matrix generation method according to claim 9, and/or the encoding method of claim 12 or 13, and/or the decoding method of any one of claims 17 to 19.

Description:
CONSTRUCTION OF LDPC CONVOLUTIONAL TURBO CODES

TECHNICAL FIELD

The present invention is directed to a device and to a method for seed matrix generation. Further, the present invention is directed to an encoding device and to an encoding method for encoding information by use of the generated seed matrix. Additionally, the present invention is directed to a decoding device and to a decoding method for decoding information by use of the generated seed matrix.

BACKGROUND

In the area of communication technology encoding and decoding of information has always been an important and challenging issue. It is desired that devices or systems are capable to exchange information in a secure way. However, encoding of information and subsequent decoding of information may lead to information losses and errors. Further, a good encoding and decoding performance is expected. Fig. 1 shows an example of a conventional communication system model where information is encoded and transmitted by an information transmitting device/system and where the encoded information is received and decoded by an information receiving device/system.

According to the exemplary conventional communication system model of Fig. 1, an information transmitting side (e.g., device or system) 11 and an information receiving side (e.g., device or system) 12 are provided. The information transmitting side 11 comprises an encoding device 111 and a modulator 112. The information receiving side 12 comprises a decoding device 121 and a demodulator 122. The input of the encoding device 111 (e.g., channel encoding device) is an information 101 being a sequence of ki bits to which a redundancy sequence of r bits is added by the encoding device 111 during the encoding process, thereby producing an encoded information 102 being a sequence of nc bits. The channel code rate R is defined as the ratio between the information bit number ki (i.e., number ki of bits of the information 101) and the encoded bit number nc (i.e., number nc of bits of the encoded information 102). Thus, R=ki/nc. The modulator 112 transforms the encoded information 102 into a modulated signal 103, which is in turn transmitted through a channel 13. Since the channel 13 is usually subject to noisy disturbance 14, the channel output 104, i.e. the encoded information received at the receiving side 12 may differ from the channel input 103, i.e. the encoded information generated and transmitted by the transmitting side 11.

At the receiving side 12, the channel output 104 is processed by the demodulator 122 which performs the MOD inverse operation of the modulator 112 and produces some likelihood ratio. The channel decoding device 121 uses the redundancy in the received encoded information 105 (output of the demodulator 122) to correct the error in the information of the received encoded information 105 and produces a decoded information 106 which is an estimate of the original information 101. Known encoding devices and/or decoding devices 111, 121 often use convolutional codes with Low Density Parity Check (LDPC) matrix as proposed, for example, in Alberto Jimenez Felstrom, Kamil Zigangirov: "Time-varying periodic convolutional codes with low density parity-check matrix", IEEE Trans. Information Theory 45 (6): 2181-2191 (1999). In the convolutional codes, the encoding device 111 contains memory and the "nc " encoder outputs 102 (i.e. the nc bits of the encoded information 102, which is a sequence of bits) at any given time unit, depend not only on the "ki" inputs 101 (i.e. the ki bits of the information 101 to be encoded, which is a sequence of bits), at that time unit, but also on "M" previous input blocks, i.e. previous M information (i.e. information bit sequences 101) that were encoded previously or before respectively.

The transposed parity-check matrix, called syndrome matrix, of a periodical binary convolutional code with memory "M", code rate "R=b/c ", code period "T=M-1 " and code period number "p " is, for example, as shown in Fig. 2. In the equation (1), shown in Fig. 2, each element

... " , wherein m and t are integers, is a binary sub-matrix with size

F

e

3x1 then the syndrome matrix H T of equation (1) of Fig. 2 becomes as shown in equation (2) of Fig. 3. The low density parity-check matrix is characterized from the following parameters

(M,Ju(Jv),K) where M determines the code period (T=M-1), Ju(Jv) are the elements to "1 " for row and "K" are the elements to "1 " for column. The parameter Ju is the row weight for the information sequence while Jv is the row weight for the parity sequence. The parameter "K" is the column weight starting from the column [

Let the information sequence be wherein:

Let the encoded sequence be wherein:

The received sequence (reference 105 in Fig. 1) will be correct if the following equation

will be satisfied:

In order that all information bits are protected from corresponding parity bits it is necessary to impose the following condition:

The systematic LDPC-CC encoding device 111 will execute encoding by implementing the following equations:

The LDPC Convolutional Codes (LDPC-CC) have been compared with the conventional FEC classes such as Convolutional Turbo Codes (CTC) and LDPC block codes (LDPC-BC); see, for example, in T. Kishigami, Y. Murakami, I. Yoshii: "LDPC Convolutional Codes for IEEE 802.16m FEC Scheme", IEEE 802.16 Broadband Wireless Access Working Group. From the result of the comparison the LDPC-CCs have advantages of encoder complexity and decoder latency: performances of LDPC-CC are as good as performances of LDPC-BC and CTC; LDPC-CC have the major advantage in enabling the decoding device 121 to adopt parallel decoding process as compared with CTC; and LDPC-CC have advantages of encoder complexity and decoding latency as compared with LDPC-BC.

Because of tail-biting, increasing the code period number that is increasing the code word length, the rates of the TB-LDPC-CC (tail-biting LDPC convolutional codes) tend

asymptotically to the construction rate of the LDPC-CC that is R=b/c=2/3.

The binary parity-check matrix construction for LDPC-CC, as shown in Alberto Jimenez Felstrom, Kamil Zigangirov: "Time-varying periodic convolutional codes with low density parity-check matrix", IEEE Trans. Information Theory 45 (6): 2181-2191 (1999), has the following properties: it has not column weight equal to "1"; the row layered decoding, already used in LDPC-BC, cannot be used. Further, a serial layered decoding, which decodes the same information sequence, leads to good performances (fast convergence of the belief propagation algorithm) but high latency. A parallel layered decoding, which decodes the same information sequence, leads to not good performances (slow convergence of the belief propagation algorithm) but low latency. Moreover, a parallel layered decoding, which decodes a different information sequence, leads to good performances (fast convergence of the belief propagation algorithm) but high latency. In addition the binary parity-check matrix construction for LDPC-CC as shown in Alberto Jimenez Felstrom, Kamil Zigangirov: "Time-varying periodic convolutional codes with low density parity-check matrix", IEEE Trans. Information Theory 45 (6): 2181-2191 (1999), is very exposed to 4-length cycles (as it is possible easily to verify by looking at the matrixes in table 1 and in table 2) which determine a performance degradation for the LDPC- CC

Consequently, further encoding and/or decoding methods are required that overcome above-mentioned drawbacks. SUMMARY

The object of the present invention is to provide improved information encoding and/or decoding. Particularly, the object of the present invention is to provide information encoding and/or decoding that overcomes at least some of the above-mentioned drawbacks.

The object of the present invention is achieved by the solution provided in the enclosed independent claims. Advantageous implementations of the present invention are further defined in the respective dependent claims, in the description, and/or in the appended figures.

According to a first aspect, a seed matrix generator is provided to be used for encoding an information and/or for decoding an encoded information, wherein the seed matrix generator is arranged to generate a seed matrix, the seed matrix being a binary parity check matrix of at least one low-density parity-check convolutional code, LDPC-CC.

In a first possible implementation according to the first aspect, the seed matrix generator if further configured to: mask a full exponent matrix of rate R with the generated seed matrix of a rate R; and expand the masked full exponent matrix with a spreading matrix to generate a cycle-free binary parity check matrix. In an embodiment, the seed matrix is a seed matrix of a LDPC convolutional turbo code, LDPC-CTC.

In a second possible implementation form according to the first aspect as such or according to the first implementation form of the first aspect, the seed matrix generator is arranged to generate the seed matrix by: generating w auxiliary seed matrices for w parallel LDPC-CCs, wherein each one of the w auxiliary seed matrices is generated for one of the w parallel LDPC-CCs, wherein w is a positive integer; and interlacing the generated w auxiliary seed matrices of the w parallel LDPC-CCs to generate the seed matrix of the LDPC-CTC. In a third possible implementation form according to the second possible implementation form of the first aspect: for each j-th auxiliary seed matrix, j being a positive integer that is smaller than w, a parity sequence of a j-th auxiliary seed matrix of a j-th LDPC-CC is input as information sequence in a (j+l)-th auxiliary seed matrix of a (j+l)-th LDPC-CC; and each LDPC-CC of the w LDPC-CCs is generated with a corresponding code rate R β that is different from the code rates of the further LDPC-CCs of the w LDPC-CC, wherein β is a positive integer and

In a fourth possible implementation form according to the third possible implementation form of the first aspect, the corresponding code rate Rp is determined by the following equation: wherein the information is a sequence of information bits and b is a number of the

information bits of the sequence, and wherein the encoded information is a sequence of encoded bits and c is a number of the encoded information bits.

In a fifth possible implementation form according to the second, third or fourth possible implementation form of the first aspect, the seed matrix generator is configured to execute the interlacing by arranging rows of matrices of the w LDPC-CC codes as rows of the seed matrix of the LDPC-CTC.

In a sixth possible implementation form according to the second, third, fourth, or fifth possible implementation form of the first aspect, the seed matrix generator is configured to execute the interlacing by arranging consecutively all i-th rows of the w LDPC-CC codes as rows in the seed matrix of the LDPC-CTC, wherein i is a positive integer and is less than or equal to the number of rows of a LDPC-CC code of the w LDPC-CC codes.

In a seventh possible implementation form according to the sixth possible implementation form of the first aspect, the i-th rows of the w LDPC-CC codes are followed by consecutively arranged i+l-th rows of the w LDPC-CC codes in the seed matrix of the LDPC-CTC.

According to a second aspect, a seed matrix generation method is provided to be used for encoding an information and/or for decoding an encoded information, wherein the seed matrix generation method comprises generating a seed matrix, the seed matrix being a binary parity check matrix of at least one low-density parity-check convolutional code, LDPC-CC. The seed matrix generation method is generally arranged to include any one or any combination of the steps executed by the seed matrix generator considered and described herein. According to a third aspect, an encoding device is provided that is arranged to execute an encoding of an information being a sequence of information bits, said encoding device comprising a seed matrix generator configured to generate a seed matrix that is arranged to be used for the encoding of the information and being a seed matrix generator described herein.

In a first possible implementation according to the third aspect, the encoding device further comprises: an exponent parity check matrix generator configured to generate an exponent parity check matrix, wherein an initial exponent parity check matrix is masked by the seed matrix to generate the exponent parity-check matrix; and an encoder configured to encode the information by use of the generated exponent parity check matrix.

According to a fourth aspect, an encoding method is provided that is configured to execute an encoding of an information being a sequence of information bits, said encoding method comprising a step of seed matrix generation for generating a seed matrix that is arranged to be used for the encoding of the information, and said step of seed matrix generation being executed by use of the seed matrix generation method described herein. The encoding method is generally arranged to comprise any one or any combination of steps executed by the encoding device described herein.

In a first possible implementation according to the fourth aspect, the encoding method further comprises: a step of exponent parity check matrix generation for generating an exponent parity check matrix, wherein an initial exponent parity check matrix is masked by the seed matrix to generate the exponent parity-check matrix; and a step of encoding the information by use of the generated exponent parity check matrix.

In a fifth aspect, a decoding device is provided that is arranged to execute a decoding of an encoded information being a sequence of encoded information bits, said decoding device comprising a seed matrix generator configured to generate a seed matrix that is arranged to be used for the decoding of the information and being a seed matrix generator described herein.

In a first possible implementation according to the fifth aspect, the decoding device further comprises: an exponent parity check matrix generator configured to generate an exponent parity check matrix, wherein an initial exponent parity check matrix is masked by the seed matrix to generate the exponent parity-check matrix; a binary parity-check matrix generator configured to generate a binary parity-check matrix, wherein the binary parity-check matrix is obtained by expanding the generated exponent parity-check matrix by means of a spreading matrix; and a decoder configured to decode the encoded information by use of the binary parity-check matrix.

In a second possible implementation according to the first possible implementation of the fifth aspect, the spreading matrix is a cyclic permutation matrix of an identity matrix. In a sixth aspect, a decoding method is provided that is configured to execute an decoding of an encoded information being a sequence of encoded information bits, said decoding method comprising a step of seed matrix generation for generating a seed matrix that is arranged to be used for the decoding of the encoded information, and said step of seed matrix generation being executed by use of the seed matrix generation method described herein. The decoding method is generally arranged to comprise any one or any combination of steps executed by the decoding device described herein.

In a first possible implementation according to the sixth aspect, the decoding method further comprises: a step of exponent parity check matrix generation for generating an exponent parity check matrix, wherein an initial exponent parity check matrix is masked by the seed matrix to generate the exponent parity-check matrix; a step of binary parity-check matrix generation for generating a binary parity-check matrix, wherein the binary parity-check matrix is obtained by expanding the generated exponent parity-check matrix by means of a spreading matrix; and a step of decoding for decoding the encoded information by use of the binary parity-check matrix.

In a second possible implementation according to first possible implementation of the sixth aspect, the spreading matrix is a cyclic permutation matrix of an identity matrix. In a seventh aspect, a computer program product is provided. The computer program product includes code for performing the steps on the seed matrix generation method according to claim 9, and/or the encoding method of claim 12 or 13, or the decoding method of any one of claims 17 to 19. BRIEF DESCRIPTION OF DRAWINGS

The above-described aspects and implementation forms of the present invention will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which

Fig. 1 shows an example of a conventional communication system model.

Fig. 2 shows a transposed parity-check matrix, called syndrome matrix, of a

periodical convolutional code.

Fig. 3 shows a transposed parity-check matrix, called syndrome matrix, of a

periodical binary convolutional code.

Fig. 4a shows an arrangement of an encoding device according to an embodiment of the present invention.

Fig. 4b shows a further arrangement of an encoding device according to an

embodiment of the present invention.

Fig. 5a shows steps of an encoding method according to an embodiment of the present invention.

Fig. 5b shows steps of an encoding method according to a further embodiment of the present invention.

Fig. 6a shows an arrangement of a decoding device according to an embodiment of the present invention.

Fig. 6b shows a further arrangement of a decoding device according to an

embodiment of the present invention. Fig. 7a shows steps of a decoding method according to an embodiment of the

present invention.

Fig. 7b shows steps of a decoding method according to a further embodiment of the present invention.

Fig. 8 shows sub-steps of the step of seed matrix generation according to an

embodiment of the present invention.

Fig. 9 shows sub-steps of the sub-step of generating w auxiliary seed matrices for w parallel LDPC-CCs according to an embodiment of the present invention.

Fig. 10 shows a more concrete arrangement of the encoding device according to an embodiment of the present invention.

Fig. 11 shows a more concrete arrangement of the encoding device according to an embodiment of the present invention.

Fig. 12 shows a portion of a generated seed matrix for LDPC-CTC according to an embodiment of the present invention.

DETAILED DESCRIPION OF EMBODIMENTS

Generally, it has to be noted that all arrangements, devices, modules, components, models, elements, units, entities, and means and so forth described in the present application could be implemented by software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionality described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and

functionalities. Even if in the following description of the specific embodiments, a specific functionality or step to be performed by a general entity is not reflected in the description of a specific detailed element of the entity which performs the specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective hardware or software elements, or any kind of combination thereof. Further, the method of the present invention and its various steps are embodied in the functionalities of the various described apparatus elements.

Moreover, any of the embodiments and features of any of the embodiments, described herein, may be combined with each other, unless a combination is explicitly excluded.

The communication system model, in which the present invention may be implemented, may be, for example, based on the communication system model shown in Fig. 1. The present invention focuses, generally, on the arrangement of the encoding device 111 and/or on the arrangement of the decoding device 121 and replaces the conventional encoding device 111 and/or decoding device 121 as shown exemplary in Fig. 1.

Fig. 4a shows an arrangement of an encoding device 4 according to an embodiment of the present invention. The encoding device 4 comprises a seed matrix generator 41 configured to generate a seed matrix that is arranged to be used for encoding information 101 and/or for decoding encoded information 105. With regard to the embodiment of Fig. 4a, the seed matrix is arranged to be used at least for encoding information 101. According to an embodiment, binary parity check matrix of a low-density parity-check convolutional code (LDPC-CC) is used as seed matrix. Conventionally, the binary parity check matrix is directly used to perform decoding process. However, said binary parity check matrix is not cycle free.

Therefore, the performance of the decoder are degraded. The present invention is based on the observation that using the binary parity check matrix of the LDPC-CC as seed matrix allows building a binary parity check matrix, which is cycle free. Using a cycle free binary parity check matrix allows to have better performances than that of the state of the art devices.

In an embodiment, a full exponent matrix is masked with the generated seed matrix and the masked full exponent matrix is expanded with a spreading matrix to generate the cycle-free binary parity check matrix. The seed matrix and its role in encoding and/or decoding processes is generally known. A seed matrix is an initial matrix, starting from which the matrix actually used for encoding and/or decoding purposes is generated. The matrix actually used for encoding and/or decoding purposes is grown or built respectively on the basis of the seed matrix. According to the present embodiment, the seed matrix is generated by the seed matrix generator 41 based on at least one low-density parity-check convolutional code (LDPC-CC). Specifically, the seed matrix is a binary parity check matrix of at least one low-density parity- check convolutional code, LDPC-CC. The LDPC-CC may for instance be the convolutional code as proposed in Alberto Jimenez Felstrom, Kamil Zigangirov: "Time- varying periodic convolutional codes with low density parity-check matrix".

The seed matrix is, according to an embodiment of the present invention, particularly a seed matrix of a LDPC convolutional turbo code (LDPC-CTC). In this way, the advantages of the LDPC-CTC can be adopted. For example, the advantage of an improved performance is adopted.

The arrangement and the implementation of the seed matrix generator 41 will be explained in more detail below.

Fig. 4b shows a further arrangement of an encoding device 4 according to an embodiment of the present invention. The embodiment of Fig. 4b is based on the embodiment of Fig. 4a. According to the embodiment of Fig. 4b, the encoding device 4 comprises further an exponent parity check matrix generator 42 configured to generate an exponent parity check matrix, wherein an initial exponent parity check matrix is masked by the seed matrix to generate the exponent parity-check matrix. Additionally, according to the embodiment of Fig. 4b, the encoding device 4 comprises an encoder 43 configured to encode the information 101 by use of the exponent parity check matrix. Via the encoding 43, encoded information 102 is obtained.

Fig. 5a shows steps of an encoding method 5 according to an embodiment of the present invention. The steps of the encoding method 5 are executed, for example, by the above- mentioned encoding device 4. According to the present embodiment, the encoding method 5 comprises a step 51 of seed matrix generation for generating 51 a seed matrix that is arranged to be used for the encoding of the information. Said step 51 of seed matrix generation is executed, according to an embodiment, by the seed matrix generator 41. As seed matrix a binary parity check matrix of at least one low-density parity-check convolutional code, LDPC-CC is taken. According to an embodiment, the seed matrix is used as a mask matrix between the full exponent parity-check matrix and the generated exponent parity-check matrix.

Fig. 5b shows steps of an encoding method 5 according to a further embodiment of the present invention. The embodiment of Fig. 5b is based on the embodiment of Fig. 5a.

According to the embodiment of Fig. 5b, the encoding method 5 further comprises a step 52 of exponent parity check matrix generation for generating an exponent parity check matrix, wherein an initial exponent parity check matrix is masked by the seed matrix to generate 52 the exponent parity-check matrix. According to an embodiment, the step 52 of exponent parity check matrix generation is executed by the exponent parity check matrix generator 42. Further, according to the embodiment of Fig. 5b, the encoding method 5 comprises a step 53 of encoding the information 101 by use of the generated 52 exponent parity check matrix. According to an embodiment, the step 53 of encoding the information 101 is executed by the encoder 43.

According to an embodiment of the present invention (combinable with any one of the embodiments described herein), the step 51 and/or the step 52, i.e. the steps of seed matrix generation 51 and/or of the exponent parity check matrix generation 52 are executed offline. In this way, hardware complexity is reduced. The generation 51, 52 of the respective matrices requires computational time and hardware. When the respective matrices are generated in advance, i.e. offline, during the execution of the encoding 5, for example, the generation 51, 52 of the respective matrices online is not necessary. During the encoding 5, the respective matrices, generated 51, 52 (in advance) offline, can be used. This leads to computational time saving and hardware saving. Consequently, a more efficient encoding 5 is enabled.

Fig. 6a shows an arrangement of a decoding device 6 according to an embodiment of the present invention. The decoding device 6 also comprises the seed matrix generator 41 configured to generate a seed matrix that is arranged to be used for encoding information 101 and/or for decoding encoded information 105. With regard to the embodiment of Fig. 6a, the seed matrix is arranged to be used at least for decoding encoded information 105.

Fig. 6b shows a further arrangement of a decoding device 6 according to an embodiment of the present invention. The embodiment of Fig. 6b is based on the embodiment of Fig. 6a. According to the embodiment of Fig. 6b, the decoding device 6 comprises further the exponent parity check matrix generator 42 configured to generate an exponent parity check matrix, wherein an initial exponent parity check matrix is masked by the seed matrix to generate the exponent parity-check matrix. Additionally, according to the embodiment of Fig. 6b, the decoding device 6 comprises a binary parity-check matrix generator 63 configured to generate a binary parity-check matrix, wherein the binary parity-check matrix is obtained by expanding the generated exponent parity-check matrix by means of a spreading matrix.

According to an embodiment, the spreading matrix is a cyclic permutation matrix of an identity matrix. Furthermore, according to the embodiment of Fig. 6b, the decoding device 6 comprises a decoder 64 configured to decode the encoded information 105 by use of the binary parity-check matrix. Via the decoding 64, decoded information 106 is obtained. The decoded information 106 is an estimate of the original information 101.

Fig. 7a shows steps of a decoding method 7 according to an embodiment of the present invention. The steps of the decoding method 7 are executed, for example, by the above- mentioned decoding device 6. According to the present embodiment, the decoding method 7 comprises the step of seed matrix generation 51 for generating a seed matrix that is arranged to be used for the encoding 43, 53 of the information. Said step of seed sequence generation 51 is executed, according to an embodiment, by the seed matrix generator 41. According to an embodiment, the seed matrix is a mask matrix between the full exponent parity-check matrix and the generated exponent parity-check matrix.

Fig. 7b shows steps of a decoding method 7 according to a further embodiment of the present invention. The embodiment of Fig. 7b is based on the embodiment of Fig. 7a. According to the embodiment of Fig. 7b, the decoding method 7 further comprises the step of exponent parity check matrix generation 52 for generating an exponent parity check matrix, wherein an initial exponent parity check matrix is masked by the seed matrix to generate the exponent parity-check matrix. According to an embodiment, the step of exponent parity check matrix generation 52 is executed by the exponent parity check matrix generator 42. Additionally, according to the embodiment of Fig. 7b, the decoding method 7 comprises a step 73 of binary parity-check matrix generation for generating a binary parity-check matrix, wherein the binary parity-check matrix is obtained by expanding the generated exponent parity-check matrix by means of a spreading matrix. According to an embodiment, the spreading matrix is a cyclic permutation matrix of an identity matrix. The step 73 of binary parity-check matrix generation is executed, for example, by the binary parity-check matrix generator 63. Further, according to the embodiment of Fig. 7b, the decoding method 7 comprises a step 74 of decoding the information 105 by use of the generated binary parity-check matrix. According to an embodiment, the step 74 of decoding the information 105 is executed by the decoder 64. Via the decoding 74, decoded information 106 is obtained. The decoded information 106 is an estimate of the original information 101.

As mentioned above, according to an embodiment of the present invention (combinable with any one of the embodiments described herein), the step 51 and/or the step 52 and/or step 73, i.e. the steps of seed matrix generation 51 and/or of the exponent parity check matrix generation 52 and/or of the binary parity-check matrix generation 73 are executed offline. In this way, hardware complexity is reduced. When the respective matrices are generated in advance, i.e. offline, during the execution of the decoding 7, for example, the generation 51, 52, 73 of the respective matrices online is not necessary. During the decoding 7, the respective matrices, generated 51, 52, 73 (in advance) offline, can be used. This leads to computational time saving and hardware saving. Consequently, a more efficient decoding 7 is enabled.

As mentioned, according to an embodiment, the seed matrix generator 41 is configured to generate a seed matrix of LDPC-CTC.

Further, according to an embodiment, the seed matrix generator 41 is configured to generate the seed matrix by executing the steps shown in Fig. 8.

Particularly, Fig. 8 shows sub-steps of the step 51 of seed matrix generation according to an embodiment of the present invention.

According to the embodiment of Fig. 8, the step 51 of seed matrix generation comprises a sub-step 511 of generating w auxiliary seed matrices for w parallel LDPC-CCs, wherein each one of the w auxiliary seed matrices is generated for one of the w parallel LDPC-CCs, wherein w is a positive integer. Further, according to the embodiment of Fig. 8, the step 51 of seed matrix generation comprises a sub-step 512 of interlacing the generated w auxiliary seed matrices of the w parallel LDPC-CCs to build the seed matrix of the LDPC-CTC. Fig. 9 shows sub-steps of the sub-step 511 of generating w auxiliary seed matrices for w parallel LDPC-CCs according to an embodiment of the present invention. Of course, according to an embodiment, the sub-steps of Fig. 9 are executed by the seed matrix generator 41.

According to Fig. 9, in sub-step 5111, each LDPC-CC of the w LDPC-CCs is generated with a corresponding code rate R β that is different from the code rates of the further LDPC-CCs of the w LDPC-CC, wherein β is a positive integer and In sub-step 5112, for each j-th

auxiliary seed matrix, j being a positive integer that is smaller than w, parity sequence of j-th auxiliary seed matrix of j-th LDPC-CC is input as information sequence in (j+l)-th auxiliary seed matrix of LDPC-CC.

According to an embodiment, the corresponding code rate ϋβ is determined by the following equation:

wherein the information is a sequence of information bits and b is a number of the

information bits of the sequence, and wherein the encoded information is a sequence of encoded bits and c is a number of the encoded information bits.

Fig. 10 shows sub-steps of the sub-step 512 of interlacing the generated w auxiliary seed matrices of the w parallel LDPC-CCs to build the seed matrix of the LDPC-CTC according an embodiment of the present invention. Of course, according to an embodiment, the sub- steps of Fig. 10 are executed by the seed matrix generator 41.

The interlacing 512 is executed, according to an embodiment, by arranging rows of matrices of the w LDPC-CC codes as rows of the seed matrix of the LDPC-CTC. Particularly, according to an embodiment the interlacing is executed by arranging consecutively all i-th rows of the w LDPC-CCs as rows in the seed matrix of the LDPC-CTC, wherein i is a positive integer and is less than or equal to the number of rows of a LDPC-CC code of the w LDPC-CC codes. According to a further embodiment, the i-th rows of the w LDPC-CC codes are followed by consecutively arranged i+l-th rows of the w LDPC-CC codes in the seed matrix of the LDPC-CTC.

The invention described herein overcomes at least some of the above-mentioned drawbacks of the known encoding and/or decoding methods by generating a seed matrix for LDPC-CTC interlacing at least two (i.e. two or more) binary parity-check matrices of the LDPC-CC. The LDPC-CC are arranged, according to an embodiment, as described, for example, in Alberto Jimenez Felstrom, Kamil Zigangirov: "Time-varying periodic convolutional codes with low density parity-check matrix", IEEE Trans. Information Theory 45 (6): 2181-2191 (1999), built with (or without) concatenated parity.

According to an embodiment, the LDPC-CTC comprises a non-concatenated parity sequence. In this case, all w LDPC-CC codes have the same code rate. For example, in the case of two parallel LDPC-CCs (w=2), 6 information bits and one parity bit are present resulting in a code rate Rl=R2=6/7 for each code. In the case of non-concatenated codes, 6 information bits and two parity bits (one for each LDPC-CC code) are present. Thus, the total code rate of the LDPC-CTC will be R=b/c=6/8=3/4.

In the description, it is sometimes focused exemplary on the LDPC-CTC with concatenated parity because LDPC-CTCs are codes enabling a better performance.

According to the present invention, a seed matrix for a specific rate R, built as described herein, masked with a full exponent matrix for a rate R and expanded with a spreading matrix (e.g., cyclic permutation matrix) produces a binary parity-check matrix for the LDPC-CTC, which leads to significant performance gains.

With the invention, as described herein, it is possible to carry-out the parallel layered decoding 64, 74 with good performances (fast convergence of the belief propagation algorithm) and low decoding latency.

The LDPC-CTC does not use an interleaver circuit because such operation is carried-out from the spreading matrixes with different exponent value for each parallel path (two or more). The skilled in the art will find the tradeoff between the wished performances and the parallel concatenated LDPC-CC number for keeping hardware complexity low.

The spreading matrix is, for example, a square binary matrix of weight equal to "I " and size wherein Z f is the spreading factor, which is tied to the code word length of the

carried-out LDPC code.

If the spreading factor is chosen, for example, then the full exponent matrix E exp

will have elements (exponents) comprised between 0 and (Z / - 1) = 47 .

The exponent matrix elements with values comprised between 0 and (Zf-l) represent cyclic permutation matrixes of the identity matrix (with weight equal to "1" for each row and for each column) with size

The value of the exponent matrix element indicates a cyclic shift to the right of the identity matrix, as shown in the matrixes below. All non-negative exponent matrix

elements have meaning, for example the zero exponent permutation matrix corresponds to the identity matrix.

Each element of the exponent matrix of value "-1 " conventionally represents a null square matrix of size ZfxZf as shown in matrix i

The skilled person easily understands that same benefits may be obtained if the cyclic shift is a cyclic shift to the left instead than a one to the right.

In the following a more concrete embodiment of the present invention is presented, wherein the more concrete embodiment is based on the above-explained embodiments and, thus, supplements the above-explained embodiments. Further, it is understood that any one or any combination of the features described below is combinable with the above presented embodiments.

According to the following embodiment, the seed matrix is generated 51 for LDPC-CTC interlacing at least two (i.e., two or more) binary parity-check matrixes of the LDPC-CC, built with concatenated parity. According to an embodiment, the LDPC-CCs are generated, as described, for example, in Alberto Jimenez Felstrom, Kamil Zigangirov: "Time- varying periodic convolutional codes with low density parity-check matrix", IEEE Trans. Information Theory 45 (6): 2181-2191 (1999), wherein the teaching on the generation of the LDPC-CCs of said publication is incorporated herein by reference.

Here, it has to be noted, that the skilled person easily understands that it is possible to build the LDPC-CTC seed matrixes without concatenated parity following the seed matrix generation procedure presented herein.

The LDPC-CTC encoder 4, with concatenated parity, is arranged, for example, as shown in Fig. 10.

The rate of an LDPC-CTC used according to the embodiment of Fig. 10 is given by:

In the design of the LDPC-CTC with more (e.g., two or more than two) parallel LDPC-CC it operates in this way to compute the rate of the single LDPC-CC codes.

The LDPC-CTC code, with rate R = b I c , is constituted by w parallel LDPC-CC codes. As mentioned above, the single LDPC-CC codes are designed with the following rates:

Let consider, for example, an LDPC-CTC with rate and constituted by

parallel LDPC-CC; the single LDPC-CC codes have rates com puted using equation (9):

Thus:

Fig. 11 shown an exemplary implementation of a LDPC-CTC encoder 4 according to an embodiment. In Fig. 11, an LDPC-CTC encoder 4 is used that has a rate

that constituted by two (w = 2) parallel LDPC-CCs. The first LDPC-CC has a rate

the second LDPC-CC has a rate being

computed according to equation (9):

However, also more LDPC-CCs, generated can be placed in parallel. Of course, it is necessary to find the tradeoff between the desired encoding and/or decoding performance and the complexity of hardware for the encoding 43, 53 and/or decoding 64, 74. The hardware complexity depends, for example, on the number of parallel concatenated LDPC-CCs.

When considering the embodiment of Fig. 11, where only two parallel LDPC-CCs are considered for sake of simplicity, i.e. where w=2, two auxiliary seed matrices are generated in step 511. The first auxiliary seed matrix has the rate of nd the second auxiliary seed matrix has the rate of

In step 512, the interlacing of the two auxiliary seed matrices is executed for generating 51 the seed matrix of the LDPC-CTC. According to the present embodiment, this is accomplished by placing the first auxiliary seed matrix with the rate for interlacing (table Ibis), on the odd rows of the seed matrix of t he LDPC-CTC and by placing the second auxiliary seed matrix with the rate of on the even rows of the seed matrix of the LDPC-CTC.

table Ibis) Binary parity-check matrix for LDPC-CCl with rate Rl=bl/cl=6/7

arranged to interlace with binary parity-check matrix for LDPC-CC2

with rate R2=b2/c2=7/8

(Matrix portion : rows 1-10 and columns 1-24)

In this way, the following correspondence between the rows of the two auxiliary seed matrices and the seed matrix to be generated 51 by the seed matrix generator 41, i.e. the seed matrix of the LDPC-CTC is obtained:

Therefore, even if the LDPC-CTC consists of several LDPC-CCs placed in parallel form, a single seed matrix, a single exponent parity-check matrix and a single binary parity-check matrix are obtained, which are used in the encoding 43, 53 and/or decoding 64, 74 processes.

As already happens for the LDPC block codes (LDPC-BC) carried-out with semi-random technique (the most employed), according to an embodiment, in the encoding process 43, 53 the exponent parity-check matrix of the LDPC-CTC is used for encoding 43 because the exponent parity-check matrix of the LDPC-CTC takes advantage of the cyclic permutation matrix features, and in the decoding process 64, 74 the binary parity-check matrix of the LDPC-CTC is used for decoding 64, 74.

Fig. 12 shows a portion of a generated 51 seed matrix for LDPC-CTC according to an embodiment of the present invention. The seed matrix of Fig. 12 is generated 51 according to the embodiment of Fig. 1 1.

For the LDPC-CCi encoder (part of the encoding device 4 of Fig. 1 1), the equation (7) remains unchanged, but now it is expressed for a code rate by the following equation (1 1):

For the LDPC-CC2 encoder (part of the encoding device 4 of Fig. 1 1), with code rate the equation (7) becomes the following equation (12):

Both equation (1 1) and equation (12) are based on Alberto Jimenez Felstrom, Kamil

Zigangirov: "Time- varying periodic convolutional codes with low density parity-check matrix", IEEE Trans. Information Theory 45 (6): 2181-2191 (1999), which is incorporated herein by reference.

To carry out the binary LDPC-CTC encoder 43, the equations (1 1) and (12) are rearranged according to an embodiment as in the following equation (13):

The above equation (13) allows to carry-out the binary LDPC-CTC encoder 43 with code rate

The binary parity-check matrix of the LDPC-CTC is used as the generated 51 seed matrix.

The generated 51 seed matrix for a specific rate R, built as described herein, masked with the full exponent matrix E exp for the rate R and expanded with the spreading matrix (e.g., cyclic permutation matrix), produces binary parity-check matrix H rxn for the LDPC-CTC which leads to significant performance gains. With the present invention it is possible to carry-out a parallel layered decoding 64, 74 with good performances (fast convergence of the belief propagation algorithm) and low decoding latency.

The LDPC - CTC does not use an interleaver circuit because such operation is carried-out from the spreading matrixes with different exponent value for each parallel path (two or more).

The skilled person will find the trade-off between the desired performances and the parallel concatenated LDPC-CC number, deciding, e.g., on hardware complexity.

The real code rate of an LDPC-CTC for tail-biting (TB-LDPC-CTC) is tied to the

construction rate of the code R = b I c , to the parallel LDPC-CC number w, to the code period length T , to the code period number P and parity element number

The exponent parity-check matrix LDPC-CTC, generated 52 by use of the generated 51 seed matrix and used for encoding 43, 53, has, for example, at least the following characteristics:

In the following, three cases are considered and both real rate for TB-LDPC-CTC equation (14) and the exponent parity-check matrix size are computed:

Increasing the code period number that is increasing the code word length, the real rate of the TB-LDPC-CTC tends asymptotically to the construction rate of the LDPC - CTC, in this case

Looking at the generated 52 exponent parity-check matrix it can be noted that it is periodic both for rows and for columns.

The periodicity of the rows is equal to the product while the

periodicity of the columns is equal to the product Then it is not necessary to store the real size for both the exponent parity-check matrix H exp and the binary parity-check matrix but only for exponent matrix rows and

for binary matrix 0 rows for all three previous cases.

To generate the exponent matrix, with the known art rules, it operates for columns because it is possible to use 40 increment steps (unlike the same operation for rows which would only 10 increment steps). The use of several increment steps in the exponent parity matrix

construction allows to achieve overlap factor less than or equal to "1" (< 1) ; for overlap factor it means the scalar product between any two columns of the binary parity-check matrix The previous condition (overlap factor makes robust the LDPC-CC that is

without 4-length minimum cycles which determine a degradation of the iterative decoding algorithm that is a degradation of the codec performances (for skilled person these statements are clear and known). In the encoding step or process 53 the exponent parity-check matrix xp is used, which takes advantage from the following properties

• the product between two cyclic permutation matrixes of the identity matrix with

exponents respectively a and β produces always a cyclic permutation matrix of the identity matrix with exponent

• the product between a cyclic permutation matrix of the identity matrix with exponent a and a vector of size Zf produces the same vector of size but with a cyclic shift of its elements equal to a.

In the decoding step or process 64, 74 the binary parity-check matrix is used because the iterative algorithm updates the single reliability value, which corresponds to the single bit.

Let the block structured information sequence be block structured encoded sequence then:

The single elements are vectors of size equal to spreading factor

The received information 105 will be correct if the following equation will be satisfied:

The systematic block structured LDPC-CTC encoder 43, derived from the binary LDPC-CTC encoder equation (13), will be carried-out with the following equations:

Exponents

LDPC-CTC parity-check matrix are cyclic permutation matrix of size ; the

coefficients («)are tied to the

information sequence while the coefficients are tied to the parity

sequence, respectively, of LDPC-CCi and LDPC-CC2; each time slot

corresponds to a block of = 288 information bits and

parity bits).

The coefficients are always between 7 but the

coefficients which correspond to the parity columns of the exponent matrix, are always equal to "0" to minimize the hardware complexity of the LDPC-CTC encoding process 43, 53; then the coefficients correspond always to the

identity matrix.

In other words, to reduce the arithmetic operation number in the LDPC-CTC encoding step or process 53, the exponent parity-check matrix is generated by putting to "0 " (cyclic permutation matrix equal to the identity matrix) the last exponent (rightmost element) of each row for all time slots corresponding to the encoded parity

sequence.

The exponent parity check matrix for the LDPC-CTC (table 3) is obtained by masking a full exponent parity check matrix with the seed matrix for the LDPC-CTC shown in figure 12.

To carry-out the LDPC-CTC encoder 4 using the exponent parity-check matrix table 3, the LDPC-CTC encoder 4 must operate in this way:

The exponent parity-check matrix will be composed, for this implementation example,

from the row 13 up to row 22 being

As already said before, by having placed to "0" the last exponent (rightmost element) of each row or all time slots n = 0, 1, 2, 3, .... ) which correspond to the encoded

parity sequence, the arithmetic operation number in the encoding process is minimized.

In fact, the below products become: without any arithmetic operation on the vectors belonging to the current time slot

For example to compute the encoded parity sequences equations (22) and (23),

corresponding to the time slot n = 7 , are carried out:

• "40" cyclic shifts for info/parity sequence vectors,

• "38 " addition operations for info/parity sequence vectors.

Thus, the present invention relates to a device - a seed matrix generator 41 - and a corresponding method, both configured to generate a seed matrix that is arranged to be used for encoding 53 an information 101 and/or for decoding 64, 74 an encoded information 105, wherein the seed matrix generator 41 is arranged to generate the seed matrix based on at least one low-density parity-check convolutional code, LDPC-CC. The seed matrix is, according to an embodiment, a seed matrix of a LDPC convolutional turbo code, LDPC-CTC. Further, the present invention relates to an encoding device 4 and a corresponding method 5, both configured to encode information 101 by use of the seed matrix, to a decoding device 6 and a corresponding method 7, both configured to decode information by use of the seed matrix.

The invention has been described in conjunction with various embodiments herein. However, other variations to the enclosed embodiments can be understood and effected by those skilled in the art and practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.