CLOCKING

FIELD OF THE INVENTION [0001] The invention generally relates in one or more of its embodiments to Integrated

Circuit (IC) design.

BACKGROUND

[0002] In designing circuits, there arc many different design strategics that may be implemented to obtain a desired result, For example, a design strategy for reducing power consumption of a circuit design may be considered. One way to implement such a strategy is by using multiple supply voltage (MSV) circuits. They save power by using lower supply voltages on non-critical paths and blocks. In MSV circuits, level conversion must be performed at the interface of blocks operating at different power supply voltages (different 'levels"). [0003 J A type of MSV is called Clustered Voltage Scaling (CVS) in which the supply voltage is lowered selectively on non-critical paths inside a block. In order to implement CVS, level conversion is done at the sequential elements of the circuit (i.e., flip-ilops). The clock distribution network can also be implemented at a lower supply voltage (i.e., low-swing clocking) for significant additional power savings. In order to do low-swing clocking in addition to CVS, a double lev el -converting flip-flop is required: a flip-flop that takes both data and clock inputs at a lower voltage level and that produces data outputs at a higher voltage level. [0004J The conventional implementation for a double level-converting flip-flop may have a regular flip-flop operating at lower supply voltage followed by a regular asynchronous level converter on the Q output. This approach is very slow and power-inefficient. An improvement includes combining the data storage function of a flip-flop with the level conversion function to form a singlε-level-converting flip-flop. The existing circuit designs introduce contention and arc ratiocd,

[0005] Conventional level converters are ratioed because their operation depends on the precise balancing of the driving strengths and sizes of the transistors in contention. The conventional designs, having contention and being ratioed, means that the ratios of the driving strengths and sizes of the devices in contention must be carefully chosen such that the contention has the desired outcome over all the process comers. Ratioed designs are inherently less robust than non-ratioed designs.

SUMMARY

[0006] The present invention presents a family of contention-free level converting flip- flops for low swing clocking. The design strategy removes the contentions and makes the design non-ratioed, and thus reduces the delay and power of the level converter and increases the circuit design's robustness.

[0007] In one embodiment, a level converting flip-flop includes a plurality of circuit elements configured such that the level converting flip-flop is contention-free, wherein the circuit elements are non-ratioed.

[0008] In another embodiment, the level converting flip-flop is used to build digital circuits that use low-swing docking and clustered voltage scaling to reduce power. [0009] In another embodiment, a method for synthesizing a circuit design that contains at least one level -converting flip-flop, including the acts of providing to a level converting flip-flop at least a data signal and a clock signal at a first swing voltage, wherein the level converting flip- flop has a plurality of circuit elements; performing level conversion and storage of a bit, wherein the flip-flop is contention free and the circuit elements are non-ratioed; outputting from the level converting flip-flop at least one output signal, wherein the output signal is at a second swing voltage; and storing a design data of the circuit design having the level converting flip-flop in a volatile or non-volatile computer usable medium.

[0010] In another embodiment, A computer program product embodied on a computer usable medium, the computer usable medium having stored thereon a circuit design block or a sequence of instructions which, when executed by a processor causes the processor to execute a process for synthesizing a circuit that contains at least one level-converting flip-flop, the process includes the act of providing the circuit design block having plurality of circuit elements configured such thai the level converting flip-flop is contention-free, wherein the circuit elements are non-ratioed,

BRJEF DESCRIPTION OF THE DRAWINGS

[0011] Fig. 1 depicts a diagram of a flip-ilop block according to an embodiment of the invention,

[0012] Fig. 2 illustrates a diagram showing a simplified logic circuit having reduced transient contention as the worst case that can happen according to an embodiment of the invention,

[0013] Fig, 3 illustrates a diagram showing a level-converting latch with low swing clock according to an embodiment of the invention.

[0014] Fig. 4 illustrates a diagram showing a contention-free, non-ratioed double level- converting D flip-ilop according to another embodiment of the invention. [0015] Fig. 5 illustrates a diagram showing a contention free non-ratioed double level- converting flip-flop with two complementary outputs according to another embodiment of the invention.

[0016] Fig. 6 illustrates a diagram showing a contention-free, non-ratioed level- converting flip-flop with synchronous set and clear according to an embodiment of the invention. [0017J Fig. 7 illustrates a diagram showing a contention-free, non-ratioed level- converting flip-flop with synchronous enable according to an embodiment of the invention. [0018] Fig. 8 depicts a flow diagram of a process for designing circuits having reduced contention and using a non-ratioed design according to an embodiment of the invention, [0019] Fig. 9 depicts a computerized system on which a method for interfacing verification environment and the emulator can be implemented.

[0020] Like reference numbers and designations in the various drawings indicate like elements, DETAILED DESCRIPTION

[0021] The present Invention includes a family of level converting flip-ilops that may accept data and clock at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished by these flip-flops in a very efficient manner by sharing the positive feedbacks inside a flip-flop for both storage and level conversion. These flip- flops are contention- free and non-ratioed, thus having reduced timing and power overheads due to the level conversion function. Some embodiments of the present invention include level converters that are more robust to process variations and noise due to the fact that they are not ratioed.

10022 J In some embodiments, an approach of combining the level conversion function with the bit storage function in a flip-flop that takes the clock signal at a lower power supply voltage, thus enabling low-swing clocking and clustered voltage scaling. Some embodiments provide level conversion technique that does not have contention between fully on transistors. Some embodiments enable the level converters to consume less power (by not wasting power in resolving the contention) and to be faster (contentions take time to resolve). [0023] In other embodiments, the technique provides circuit designs with low overhead level conversion for low-swing clocking and clustered voltage scaling, contention-free level conversion, and non-ratioed level conversion. In additional embodiments, other types of level converting flip-flops implemented with the technique are also described below, [0024] The family of non-ratioed contention- free level converting flip-flops includes flip- flops that have the function of level conversion as shown in Fig. 1 with the desirable properties of being non-ratiocd and contention-free as described in Fig. 2. This family of flip-flops takes data and clock at lower voltage level and provides output Q al higher voltage level with the desirable property of being contention free and non-ratioed, In assisting in the description of the embodiments in the detailed description, the lower supply voltage at an interface is referred to as VDDL, and to the corresponding blocks, circuits, and devices operating at VDDL as "VDDL blocks ^" ', "VDDL circuits ^" ' and "VDDL devices". Similarly, the higher supply voltage at an interface is referred to as VDDM, and to the corresponding blocks, circuits, and devices operating at VDDH as "VDDH blocks", "VDDH circuits", and "VDDH devices ^" '. Il is implicitly assumed that VDDL < VDDH.

[0025] Fig. 1 depicts a diagram of a level converting flip-ilop block 100 according to an embodiment of the invention. The block receives a VDDL signal to ports CLK, D, and other synchronous inputs labeled SYNC_1N. The block also may receive V ⁷ DDH signals at asynchronous inputs such as the one labeled AS YTNCJDN . The block outputs a VDDH signal at port Q.

[0026J In some embodiments, the level converting flip-flop 100 may be a D-type flip- flop, T-type flip-flop, JK-type flip-flop, D-type with synchronous set and/or reset and/or asynchronous set and/or enabled, etc. Any type of flip-flop that functions to store a bit may be used.

[0027] Fig. 2 illustrates the contention- free and non-ratiocd properties of the flip-flops in

Fig.l according to an embodiment. Fig. 2 includes a PMOS connected to a V ⁷ DDH and a NMOS that is connected to ground. The gates of the PMOS and NMOS devices are held at VDDL. A VDDH PMOS device with VDDL on its gate is said to be in a "leaky off state. In Fig. 2, the contention has been reduced as compared to the case where the gale of the PMOS is held at zero volts. This reduced contention allows a non-ratioed design, In other words, even a minimum size NMOS is much stronger when fully on than any reasonably sized PMOS in leaky off state, in all process corners.

[0028] Fig. 2 is an example of a circuit design 200 that illustrates the worst case transient contention that can happen between an NMOS device and a PMOS device in any embodiment of the invention. In the worst case and only for a limited time, a fully on NMOS device with VGS = VDDL can be in contention with a leaky off VDDH PMOS device with VDDL on its gate, hence jVGS! = VDDH ^■ - VDDL. Such a contention is resolved very fast by the circuit because the PMOS in leaky off is very weak. In traditional level converting circuits, there is contention between a fully on NMOS with VGS = VDDL and a fully on PMOS with jVGSj = VDDH. Such contention between fully on devices is slower to resolve and consumes more power than the contention illustrated in Fig. 2.

10029 J In Fig. 2, in some embodiments, the threshold voltage of the PMOS device is more than VDDH-VDDL and the PMOS is truly off, causing only a minimal leakage current through the transistors. In other cases, the threshold voltage of the PMOS can be slightly more than VDDH-VDDL, thus causing a higher leakage current through the transistors. In both cases, the leakage current of the PMOS is much less than the ON current that would be produced by having the same device fully on with JVGSj=VDDH. Consequently, the contention between the fully on NMOS and the leaky off PMOS is resolved very fast, with minimal power consumption. A circuit that has the worst case transient contention like the one illustrated in Fig.2 may be considered to be "contention-free". Moreover, because the ratio between the current of the NMOS in the on state and the leakage current of the PMOS in the leaky off state is very large, the devices in Fig, 2 can have almost any ratio of sizes (hence any ratio of driving strengths when fully on) and the contention will always resolve quickly to the desired outcome (fully on NMOS overpowering the leaky-off PMOS). Therefore, a circuit that has the worst case transient contention like the one illustrated in Fig. 2 may be considered to be '"non-ratioed". In contrast, in traditional level converting circuits, where there is contention between a fully on NMOS with VGS = VDDL and a fully on PMOS with |VGS| = VDDH. the ratio of the sizes of the two devices must be very carefully chosen such that the contention resolves to the desired outcome across all process corners. Thus, the "non-ratioed" property of the designs makes the circuits very robust to process variations.

[0030] In some embodiments. VDDL to VDDH conversion may be incorporated into a circuit design that is non-ratioed and contention-free, The design is considered contention-free when, even for the worst-case scenario, the contention is not worse than depicted in Fig. 2. [0031] Fig. 3 shows the schematic of a level converting latch with low swing clocking alone. This latch uses the same schematic as the classical single supply latch, but with the clock signal at VDDL. The internal clock buffers are also at VDDL. The buffers may include an inverter INV CKl to invert the input clock elk in to provide ckb and another inverter INV CK 2 to invert ckb to provide the clock signal ck at VDDL. These clock buffers and inverters also may be used for the level-converting circuit designs in Figs. 4-7.

[0032] The latch of Fig. 3 includes PMOS Pl, P2 and P3, and NMOS Nl, N2, and N3.

This latch has an IN and an OUT, The latch includes P2 connected with VDDH arid Pl . Pl connected with ?2 and IN. Nl connects IN and N 2. N2 connects N 1 and ground. The gate of P2 and N2 are connected to OUT, the gate of Pl is connected to ck and the gate of N 1 is connected to ckb. P3 connects VDDH and OUT, N3 connects OUT and ground, The gate of N3 and P3 are connected to FN, A problematic connection in this latch is c/c-to-gatc of Pl: a VDDL signal (ck) connected to a VDDH PMOS (Pl) has the potential to cause a significant leakage current, On closer inspection, such leakage is not possible after all transients are over: Pl can leak only if IN=O; but if IN =0, then OUT =1 and P2 is off (solidly off, with | VGS |=0), cutting off any leakage from Pl. This design has a slight contention between Pl and the NMOS devices in the gate driving the input: when ck=\ (VDDL) and IN switches 1 to 0, until the positive feedback loop closes and P2 turns off, Pl is in leaky off and in contention with the fully on NMOS devices in the gate driving node IN. This contention between a fully on NMOS and a leaky off PMOS is illustrated in Fig. 2.

[0034] In one embodiment, the principle from Fig. 3 may be applied to design a contention- free non-ratioed double level converting D flip-flop. Fig, 4 illustrates a diagram showing a logic circuit that is contention-free, non-ratioed double level converting D flip-flop using the design strategy of Fig. 3.

[0035] The logic circuit of Fig. 4 includes a VDDL master latch 510, a pass gate driven by a VDDL signal ck 520, and a VDDH slave latch 530. Many different designs are possible for the VDDL master latch 510. The pass gate NS is a VDDL PMOS. The VDDH slave latch may be any design that is similar to the design of slave latch 530.

[0036] In one embodiment, the master latch 510 includes PMOS P 1 , P2 , P3 and P4,

NMOS Nl , N2, N3. and N4 and inverter INV_M. Pl is connected to VDDL and P2. P2 is connected to Pl and node mf. Nl is connected to node tnf and N2. N2 is connected to N 1 and ground. P3 is connected to VDDL and P4. P4 is connected to P3 and node mf. N3 is connected to node mf and N4. N4 is connected to N3 and ground. INV M is connected to node mf and node mo, which take signal nil ^" and provides mo. Signal d is provided to the gates of Pl and N2. Clock signal ck is provided to the gates of N3 and P2. Clock signal ckb is provided to the gates of P4 and Nl, The output of INV M (node mo) is connected to the gate of P3 and N4. [0037] In one embodiment, the pass gate N5 520 connects with mo and si and ck is provided at the gate of N5. (n this type of level conversion flip-flops, level conversion occurs at node si.

[0038] In one embodiment, the slave latch 530 include PMOS, P5, Pό, P7, P8, P9 and

PlO, NMOS N6, N7, N8, N9, Nl O. and INV Q. P7 is connected to VDDIi and node A. P5 and P6 are connected to node A and node si. No is connected to node si and node A\ N7 is connected to A' and ground. PlO is connected to VDDH and node B. P9 and P8 are connected to node B and Node so. N8 is connected to node so and ground. N9 is connected to node so and Nl O, NlO is connected to N9 and ground. P8, P9, PlO, N 8, N9, and N lO are configured as the OAI_Slave. IN V_Q is connected to node so and q. Node so is connected to the gates of P7 and N7. Node si is connected to the gates of PlO and N8, Signal mf is provided to the gate of P5. Signal ckb is provided to N6. Signal ck is provided to Pό, P9 and N9. Signal mo provided to P8 and NlO.

[0039 J Without P5 and P6, contention between N 5 and P7 occurs when mo=Q and ck=l, but P7 is needed for level restoration at node si only when mo=\ and ck=\. Since P7 is needed in the circuit only when mo=\ (VDDL), P5 is inserted in the circuit driven by the complement of mo. Node ?π/ ^* ρrovides this signal very conveniently and with the right timing to avoid contention: nifwill switch to 1 (VDDL) before mo switches to 0. P6 closes the feedback loop in the slave latch when ck=Q and N5 is off. Due to the same reasons as in Fig. 4, P5 and P6 may not leak after all the transients are over despite having VDDL on their gates, Without P8 and P9, the contention between PlO and N9, NTO occurs because N8, N9, NlO and PlO do not form a complementary CMOS gate. In Fig. 4, PMOS PS and PMOS P9 are added, such thai N8, N9, Nl O and P8, P9, PlO form a static CMOS or-and-inverl gale with the function so--=(si+ck*rno)\ P8 and P9 are VDDH PMOS devices driven by VDDL signals (ck and mo). However, they will not leak after all transients are over: for P8 or P9 to leak, node so must be 0, which may be caused by sz-i; therefore, PlO is off with |VGS|=0 and P8 and P9 do not leak.

10041 J The worst case contention in the level converting flip-flop from Fig. 4 is identical to Fig. 2, between fully on NMOS devices with VGS=VDDL and a leaky off PMOS with |VGSj=VDDH- VDDL, thus the design is contention-free and non-ratioed. [0042] Other flip-flop designs can be created using the same technique and design strategy from Fig. 3. Fig. 5 is a diagram of a contention-free non-ratioed double level-converting flip-flop with two outputs. This diagram shows the two-output (Q and QB) version of the double level converting D flip-flop.

[0043] The correct contention-free and non-ratioed operation of this level-converting flip-flop can be demonstrated from Fig. 4. The circuit in Fig. 5 is the same as in Fig. 4 with nodes A and A' shorted, transistors P7 and N7 grouped together and labeled as IN V_SO and the additional inverter INV QB from A to QB. Shorting A and A' of Fig. 5 will not cause any strong contention or leakage.

[0044] In other embodiments, level-converting flip-flops with synchronous inputs may be designed by changing the VDDL master latch. Fig. 6 is a diagram of a contention- free, non- ratioed level-converting flip-flop with synchronous set and clear, with D, CK, SN and CN at VDDL. Fig. 7 is a diagram of a contention- free, non-ratiocd level converting flip-flop with synchronous enable, with D, CK, and E at VDDL. This diagram shows a level-converting flip-flop with synchronous enable signal at VDDI. level, which allows this flip-flop to be used with low swing clocking schemes where clock gating is also done at VDDL. 10046 J In other embodiments, scan-enabled, multiplexed inputs and other combinations of synchronous enable / set / reset level converting flip-flops may also be modified as well. In other words, all synchronous inputs can be at VDDL. In other embodiments, flip-flops with asynchronous inputs ( e.g. asynchronous set / reset) can also be constructed in a similar way with the asynchronous inputs being at VDDH and any synchronous input as well as D and CK remain at VDDL.

[0047] The level converters have the same robustness as static CMOS circuits - they perform their function correctly even with the transistors having very different driving strength due to process variations or simply due to poor design.

[0048] Fig. 8 depicts a flow diagram 900 of a process for designing circuits having reduced contention and using a non-ratioed design according to an embodiment of the invention. In an integrated circuit (IC?) design, in some embodiments, a member of a family of level converting flip-flop is designed. It may be part of the IC design. It may be stored as a circuit block for repeated use in the IC design. It may be advantageous to have standardized cell designs accessible to the designers. In further embodiments, the circuit block may be stored as a standardized cell where designers with access / permission may use it in their design. 10049 J At 910, a level converting flip-flop that is a member of the family of circuits having reduced contention and a non-ratioed design is designed. The level converting flip-flop may be designed using any tools that are available to a designer. It is designed so that it has the desirable properties of being a non-ratioed and contention free design using strategies based on the descriptions above. In some embodiments, the level converting flip-flop may be designed from scratch, In other embodiments, an existing level-converting flip-flip design is used as a starting point. Locations of contentions are identified between transistors such as NMOS and PMOS. Contentions between the transistors are removed by the lessons taught in the Figs, 4 to 7. As such, the worst case contention is as shown in Fig. 2. At 940, the design of this type of flip-flop may then be incorporated into a circuit design/project as desired. |0050| The circuit blocks may be designed in a number of possible ways. For example, at 920, the flip-flop design may be stored as a circuit block for later reuse. In some embodiments, it is saved as a standardized cell block which may be stored in a cell library for easy access by users to incorporate in their design (930), In other embodiments, the block may be directly provided to a user to apply to the circuit design (940).

10051 J At 930, the designed blocks are stored in a cell library. The cell library may use any kind of schema and language. It may be located locally or at a central location. It may also be distributed at one or more remote locations. The cell library may be a computer-usable storage medium such as a repository or database of standardized cells of circuit design. Any form of medium as described in Fig. 9 may be used. The library may be accessed such that a user may incorporate the design block into the IC design. The library may be accessed via any type of connections such as a local bus, the Internet, a local area network, wireless network, etc. In some embodiments, security and/or encryption may be used to control access to the library information.

[0052] At 940, a circuit design incorporates the level converting flip flop that is a member of the family having reduced contention and using a non-ratioed design. In some embodiments, this level converting flip flop maybe be incorporated into a larger circuit design by importing from the cell library, as a circuit block, or directly designed as part of the circuit design,

[0053] The embodimenls may be used for any type of design activities, including hardware design, software design, and designs including both hardware and software such as hardware/software co-design activities. For example, some embodiments of the invention may be applied Io the design of embedded software and systems, which includes graphical processors, central processing units, computers, as well as any other systems that include embedded software.

[0054] The execution of the sequences of instructions required to practice the embodiments may be performed by a computer system 1000 as shown in Fig, 9, In an embodiment, execution of the sequences of instructions is performed by a single computer system 1000. According to other embodiments, two or more computer systems 1000 coupled by a communication link 1015 may perform the sequence of instructions in coordination with one another. Although a description of only one computer system 1000 will be presented below, however, it should be understood that any number of computer systems 1000 may be employed to practice the embodiments,

[0055] Fig. 9 depicts a computerized system on which a method for implemented. The execution of the sequences of instructions required to practice the embodiments may be performed by a computer system 1000 as shown in Fig. 9. In an embodiment, execution of the sequences of instructions is performed by a single computer system 1000. According to other embodiments, two or more computer systems 1000 coupled by a communication link 1015 may perform the sequence of instructions in coordination with one another. Although a description of only one computer system 1000 will be presented below, however, it should be understood that any number of computer systems 1000 may be employed to practice the embodiments,

[0056] A computer system 1000 according Io an embodiment will now be described with reference to Fig. 9, which is a block diagram of the functional components of a computer system

1000. As used herein, the term computer system 1000 is broadly used to describe any computing device that can store and independently run one or more programs.

[0057] The computer system 1000 includes a bus 1006 or other communication mechanism for communicating instructions, messages and data, collectively, information, and one or more processors 1007 coupled with the bus 1006 for processing information. Computer system 1000 also includes a main memory 1008, such as a random access memory (RAM) or other dynamic storage device, coupled Io the bus 1006 for storing dynamic data and instructions to be executed by the processor(s) 1007. The main memory 1008 also may be used for storing temporary data, i.e., variables, or other intermediate information during execution of instructions by the proccssor(s) 1007.

[0058] The computer system 1000 may further include a read only memory (ROM) 1009 or other static storage device coupled to the bus 1006 for storing static data and instructions for the processor(s) 1007. A storage device 1010, such as a magnetic disk or optical disk, may also be provided and coupled to the bus 1006 for storing data and instructions for the ρrocessor(s)

1007.

[0059] The computer system 1000 may be coupled via the bus 1006 to a display device

101 1, such as, but not limited to, a cathode ray tube (CRT), for displaying information to a user.

An input device 1012, e.g., alphanumeric and other keys, is coupled to the bus 1006 for communicating information and command selections to the processor(s) 1007. Each computer system 1000 may include a communication interface 1014 coupled to the bus 1006. The communication interface 1014 provides two-way communication between computer systems 1000. The communication interface 1014 of a respective computer system 1000 transmits and receives electrical, electromagnetic or optica! signals, which include data streams representing various types of signal information, e.g., instructions, messages and data. A communication link 1015 links one computer system 1000 with another computer system 1000. For example, the communication link 1015 may be a LAN, in which case the communication interface 1014 may be a LAN card, or the communication link 1015 may be a PSTN, in which case the communication interface 1014 may be an integrated services digital network (ISDN) card or a modem, or the communication link 1015 may be the Internet, in which case the communication interface 1014 may be a dial-up, cable or wireless modem, [0061] A computer system 1000 may transmit and receive messages, data, and instructions, including program (i.e., application or code) through its respective communication link 1015 and communication interface 1014. Received program code may be executed by the respective processor(s) 1007 as it is received, and/or stored in the storage device 1010, or other associated non-volatile media, for later execution.

[0062] In an embodiment, the computer system 1000 operates in conjunction with a data storage system 1031, e.g., a data storage system 1031 that contains a database 1032 that is readily accessible by the computer system 1000. The computer system 1000 communicates with the data storage system 1031 through a data interface 1033. A data interface 1033, which is coupled to the bus 1006, transmits and receives electrical, electromagnetic or optical signals that include data streams representing various types of signal information, e.g., instructions, messages and data. In other embodiments, the functions of the data interface 1033 may be performed by the communication interface 1014.

[0063] According to one embodiment, an individual computer system 1000 performs specific operations by their respective processors s) 1007 executing one or more sequences of one or more instructions contained in the main memory 1008. Such instructions may be read into the main memory 1008 from another computer-usable medium, such as the ROM 1009 or the storage device 1010. Execution of the sequences of instructions contained in the main memory 1008 causes the processor(s) 1007 to perform the processes described herein. In alternative embodiments, hard- wired circuitry may be used in place of or in combination with software instructions. Thus, embodiments arc not limited to any specific combination of hardware circuitry and/or software,

The term "computer-usable medium,' ¹ as used herein, refers to any medium that provides information or is usable by the processors ) 1007. Such a medium may take many forms, including, but not limited to, non-volatile and volatile. Non-volatile media, i.e., media that can retain information in the absence of power, includes the ROM 1009, CD ROM, magnetic tape, and magnetic discs. Volatile media, i.e., media that cannot retain information in the absence of power, includes the main memory 1008,

[0065] In the foregoing specification, the embodiments have been described with reference to specific elements thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments. For example, the reader is to understand that the specific ordering and combination of process actions shown in the process flow diagrams described herein is merely illustrative, and that using different or additional process actions, or a different combination or ordering of process actions can be used to enact the embodiments, The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.