CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Application No. 17/230,731, filed April 14, 2021, entitled “CONTINUOUS TIME LINEAR EQUALIZATION AND BANDWIDTH ADAPTATION USING PEAK DETECTOR”, all of which are hereby incorporated herein by reference in their entirety for all purposes.

REFERENCES

[0002] The following references are herein incorporated by reference in their entirety for all purposes:

[0003] U.S. Patent No. 10/931,249, issued February 23, 2021, of U.S. Application No. 16/378,461, filed April 8, 2019, naming Suhas Rattan and Kiarash Gharibdoust, herein referred to as [Rattan]

BACKGROUND

[0004] In modern digital systems, digital information has to be processed in a reliable and efficient way. In this context, digital information is to be understood as information available in discrete, i.e., discontinuous values. Bits, collection of bits, but also numbers from a finite set can be used to represent digital information.

[0005] In most chip-to-chip, or device-to-device communication systems, communication takes place over a plurality of wires to increase the aggregate bandwidth. A single or pair of these wires may be referred to as a channel or link and multiple channels create a communication bus between the electronic components. At the physical circuitry level, in chip-to-chip communication systems, buses are typically made of electrical conductors in the package between chips and motherboards, on printed circuit boards (“PCBs”) boards or in cables and connectors between PCBs. In high frequency applications, microstrip or stripline PCB traces may be used.

[0006] Common methods for transmitting signals over bus wires include single-ended and differential signaling methods, with the data encoded as signal amplitude variations, i.e. using Pulse Amplitude Modulation (PAM). In applications requiring high speed communications, those methods can be further optimized in terms of power consumption and pin-efficiency, especially in high-speed communications. More recently, vector signaling methods such as described in [Shokrollahi] have been proposed to further optimize the trade-offs between power consumption, pin efficiency and noise robustness of chip-to-chip communication systems. In those vector signaling systems, digital information at the transmitter is transformed into a different representation space in the form of a vector codeword that is chosen in order to optimize the power consumption, pin-efficiency and speed trade-offs based on the transmission channel properties and communication system design constraints.

[0007] Regardless of the method used, the received signals presented to the receiving device are sampled (or their signal value otherwise recorded) at intervals best representing the original transmitted values, regardless of transmission channel delays, interference, and noise. This Clock and Data Recovery (CDR) or Clock Data Alignment (CDA) not only must determine the appropriate sample timing, but must continue to do so continuously, providing dynamic compensation for varying signal propagation conditions. It is common for communications receivers to extract a receive clock signal from the received data stream. Historically, such extraction required sampling of the received signal at both the center of each receive unit interval (UI) to obtain the data value, and at the UI edge to sample the signal transition or edge for clock alignment. So-called baud-rate CDA systems have been developed which can obtain both data and clock information simultaneously.

[0008] Real-world communications channels are imperfect, degrading transmitted signals in both amplitude (e.g. attenuation) and timing (e.g. delay and pulse smearing) which may be addressed via transmitter pre-compensation and/or receive equalization. Continuous time linear equalization (CTLE) is one known approach to frequency domain equalization, in one example providing compensation for increased channel attenuation at high frequencies. Time-domain-oriented equalization methods are also used to compensate for the effects of inter-symbol-interference or ISI on the received signal. Such ISI is caused by the residual electrical effects of a previously transmitted signal persisting in the communications transmission medium, so as to affect the amplitude or timing of the current symbol interval. As one example, a transmission line medium having one or more impedance anomalies may introduce signal reflections. Thus, a transmitted signal will propagate over the medium and be partially reflected by one or more such anomalies, with such reflections appearing at the receiver at a later time in superposition with signals propagating directly. [0009] One method of data-dependent receive equalization is Decision Feedback Equalization or DFE. Here, the time-domain oriented equalization is performed by maintaining a history of previously-received data values at the receiver, which are processed by a transmission line model to predict the expected influence that each of the historical data values would have on the present receive signal. Such a transmission line model may be pre-calculated, derived by measurement, or generated heuristically, and may encompass the effects of one or more than one previous data interval. The predicted influence of these one or more previous data intervals is collectively called the DFE compensation. At low to moderate data rates, the DFE compensation may be calculated in time to be applied before the next data sample is detected, as example by being explicitly subtracted from the received data signal prior to receive sampling, or implicitly subtracted by modifying the reference level to which the received data signal is compared in the receive data sampler or comparator. However, at higher data rates the detection of previous data bits and computation of the DFE compensation may not be complete in time for the next data sample, requiring use of so-called “unrolled” DFE computations performed on speculative or potential data values rather than known previous data values. As one example, an unrolled DFE stage may predict two different compensation values depending on whether the determining data bit will resolve to a one or a zero, with the receive detector performing sampling or slicing operations based on each of those predictions, the multiple results being maintained until the DFE decision is resolved.

BRIEF DESCRIPTION

[0010] A digital receiver system samples received signals in both amplitude and time, obtaining sufficient information to permit accurate detection and decoding of the transmitted data regardless of signal degradations induced by the communications medium. Addressing the particular characteristics of the communications medium may require signal amplification, frequency- and time-domain filtering, as well as accurate adjustment of both the time and amplitude at which sampling occurs. In an advanced receiver design, this optimal operating point is maintained by a delicate balance of signal equalization and clock sample timing, with both signal equalization (using DFE) and clock synchronization (using data transition detection) being dependent on accurate detection of prior data values. This creates a “chicken and egg” condition at system startup, where correct detection of data values requires proper adjustment of equalization and clock timing, which are themselves dependent on data having been detected correctly. [0011] To facilitate timely initialization of a data receiver, one embodiment extracts amplitude- related information from the incoming signal stream before the receive clock system has extracted enough synchronization information to produce a stable, locked clock reference. These asynchronous measurements of receive signal amplitude variations as frequency-dependent equalization parameters are changed can facilitate entry into normal receiver operation.

[0012] Methods and apparatus are described to obtain a signal peak value associated with high frequency energy of a pulse-amplitude modulated (PAM) data signal at an output of a CTLE using a peak detector, incrementally reducing equalization of the PAM data signal via changes to an equalization code to increase low frequency energy of the PAM data signal, detecting an increase in the signal peak value of the PAM data signal relative to the signal peak value associated with the high frequency energy of the PAM data signal, the increase responsive to a change in the equalization code, and outputting the equalization code the equalization code associated with the increase in the signal peak value.

BRIEF DESCRIPTION OF FIGURES

[0013] FIG. l is a block diagram of a receiver, in accordance with some embodiments.

[0014] FIG. 2 is a schematic illustrating one CTLE embodiment.

[0015] FIG. 3 shows the frequency response of an embodiment as in FIG. 2.

[0016] FIG. 4 illustrates the asynchronous outputs of a CTLE configured to different ratios of high frequency to bandpass gain.

[0017] FIG. 5 is a graph showing the high frequency and mid-frequency gain of one CTLE embodiment as the equalization control code is changed.

[0018] FIG. 6 is a flow chart illustrating one embodiment of a method in accordance with the invention.

[0019] FIG. 7 is a block diagram of control logic, in accordance with some embodiments.

[0020] FIG. 8 is a graph of a frequency response illustrating coarse and fine settings of a CTLE, in accordance with some embodiments.

DETAILED DESCRIPTION [0021] In recent years, the signaling rate of high speed communications systems have reached speeds of tens of gigabits per second, with individual data unit intervals measured in picoseconds. Depending on the particular coding scheme used, the number of channels comprising such a communications link may range from one to eight or more, and may also communicate one or more clock signals, either within data channels or on separate communications channels.

[0022] In one embodiment utilizing a vector signaling code, multiple bits of data are encoded at the transmitter into a vector signaling “codeword”, i.e. a set of symbols to be transmitted essentially simultaneously over the multiple wires or channels of the communication medium. As each such wire or channel may take on more than two possible values, each symbol of the codeword is drawn from an alphabet of allowable signal values; representative examples of the art use alphabets of either four or ten values in encodings of five data bits into six symbol codewords. In the receiver, the multilevel wire signals are detected to determine the received codeword, which is then decoded into received data.

[0023] A vector signaling code receiver may alternatively detect a combination of received wire signals directly using a multi-input comparator (MIC) performing a weighted summation of two or more wire signals correlated with an orthogonal signaling mode corresponding to a single subchannel (i.e. a single encoded bit) of the whole, and directly producing one bit of received data as a simple binary measurement.

[0024] Conventional practice for a high-speed integrated circuit receiver terminates each received signal channel, subchannel, or wire signal in a sampling device. This sampling device performs a measurement constrained in both time and amplitude dimensions; in one example embodiment, it may be composed of a sample-and-hold circuit that constrains the time interval being measured, followed by a threshold detector or digital comparator that determines whether the signal within that interval falls above or below (or in some embodiments, within bounds set by) a reference value. Alternatively, a digital comparator may determine the signal amplitude followed by a clocked digital flip-flop capturing the result at a selected time. In other embodiments, a combined time- and amplitude- sampling circuit is used, sampling the amplitude state of its input in response to a clock transition.

[0025] For descriptive convenience, this document will use the term sampling device, or more simply “sampler” to describe the receiver component that obtains an input measurement, as it implies both the time and amplitude measurement constraints, rather than the similar but less descriptive term “sheer” also used in the art. In some embodiments, the time at which a sample is captured may be adjusted in some or all of the receiver samplers; in some embodiments, the threshold level to which a sample is compared may be adjusted in some or all of the receiver samplers. As one example, the well-known receiver “eye plot” diagram is typically obtained by iterative adjustment of these parameters, with the results plotted graphically as signal amplitudes over time.

[0026] Embodiments may apply to any communication or storage methods, including those requiring coordination of multiple channels or elements of the channel to produce a coherent aggregate result.

Receive signal equalization

[0027] At high data rates, even relatively short and high-quality communications channels exhibit considerable frequency-dependent signal loss, thus it is common for data receivers to incorporate receive signal equalization. Continuous-time Linear Equalization (CTLE) is commonly used to generate an equalized information signal by increasing high frequency gain (and/or lowering low frequency gain) in the receive signal path, in compensation for the increased high frequency attenuation of the channel. Thus, as non-limiting examples, the amount of high frequency signal energy presented to the sampler may be adjusted independent of the mid-frequency signal energy or the low frequency signal energy. In some embodiments, the transition frequency or (also known as the filter break-point,) between a first and a second frequency range may also be configurable. Thus, a typical CTLE embodiment may have multiple configurable parameters associated with the relative or absolute signal gain the circuit provides over particular frequency ranges. In one embodiment, these parameters are made available as digital values or codes that may be configured or adjusted by a controlling device.

[0028] It has also become common practice for data communications receivers to incorporate Decision Feedback Equalization (DFE) to compensate for signal propagation anomalies in the communications medium. The DFE system performs non-linear time-domain equalization on the received signal by maintaining a history of previously-received data values at the receiver, and processing those historic data values with a transmission line model to predict the expected influence each of the historical data values would have on the present receive signal. Such a transmission line model may be pre-calculated, derived by measurement, or generated heuristically, and may encompass the effects of one or more than one previous data interval.

[0029] In a typical receiver design, this computed DFE compensation value will be applied to the current receive signal input to produce a corrected signal more accurately representing the received data value. As an example, previous transmission of consecutive “zero” signals might lead to a predicted lower threshold level for a subsequent receiver data measurement, while previous transmission of consecutive “one” signals might lead to a predicted higher threshold level for the same data measurement. At extremely high data rates, so-called speculative DFE techniques may be used, allowing sampling to occur even though one or more previous data values necessary for the DFE computation are unresolved. In one such embodiment, multiple samples are captured at differing threshold levels corresponding to possible prior data values, with the correct captured value selected for detection once the previous data value has been resolved.

Example embodiment

[0030] For purposes of description and without implying limitation, a serial data receiver as shown in FIG. 1 will be used as an example. To better represent a typical state of the art system, the example receiver includes at least one stage of speculative DFE 150 supported by two data samplers performing concurrent time-sampling operations at two different amplitude thresholds, and a receiver clock system 170 to produce a sampling clock, the phase of which may be adjusted by a clock-data-alignment (CD A) correction to optimize data sampling timing. Two comparators 120 configured to generate two comparator outputs are shown, the comparators configured to compare a received signal to a first threshold as at 121 and a second threshold as at 122, according to a sampling clock, the first and second thresholds determined by an estimated amount of inter symbol interference associated with the received input. A data decision selection circuit 130 configured to select one of the two comparator outputs as a data decision, the selection based on at least one prior data decision that may be stored in sample history 140. The apparatus further includes a phase-error indication selection circuit 160 configured to select one of the two comparator outputs as a phase-error indication in response to receiving a CDA selection signal from a pattern detection circuit 155 configured to identify a predetermined data decision pattern in the sample history 140. In some embodiments, the apparatus further includes a receiver clock system 170 configured to receive the phase-error indication and to responsively adjust a phase of the sampling clock. In some embodiments, the phase-error indication is an early/late logic decision on a transition of the received signal. In some embodiments, the data decision selection circuit 130 and phase-error indication circuit 160 select different comparator outputs. In some embodiments, the apparatus further includes a decision-feedback equalization (DFE) circuit 150 configured to generate the first and second decision thresholds. In some embodiments, the apparatus further includes a sub-channel detection multi -input comparator 190 (MIC) operating on signals received via a plurality of wires, the sub-channel detection MIC 190 configured to generate the information signal. In other embodiments, a single wire signal or the differential value of two wire signals provides the receive data input, with 190 representing any associated termination, amplification, or line receiver elements generating the information signal.

[0031] As described in subsequent examples, FIG. 1 also shows a hardware peak detection element 195 in accordance with some embodiments.

[0032] The descriptions and examples herein additionally assume a CTLE 110 circuit as shown in FIG. 2, without implying limitation. In one embodiment using this circuit, CTLE high- frequency gain may be seen to be essentially constant as shown as 310 in the response curve of FIG. 3, with the primary CTLE configurable parameter controlling bandpass gain 320, the combination of which provides the desired adjustable ratio of high frequency to bandpass frequency gain within the equalization circuit, commonly by changing an equalization code or setting in a control register. Some CTLE embodiments also provide secondary configurable parameters, as suggested by variable capacitors 233/234. In some embodiments, this secondary configurable parameter is used to provide an overall CTLE bandwidth limit capability using a similar control mechanism. In other CTLE embodiments known in the art and equally compatible with the present invention, the bandpass gain may be fixed and the amount of high-frequency peaking gain is variable.

Startup

[0033] During initiation of receive operations such as at system power-up, the normal synergistic behavior of the various receiver components is not functional. The receiver clock subsystem 170 outputs a sampling clock asynchronous to the received data input(s), thus consecutive results of samplers 121/122 will in general not correspond to valid data and/or clock results, and certainly do not represent the consecutive received samples needed by DFE 150 or Pattern Verification 155. The resulting paucity of Pattern-Verified Edge Samples delays obtaining clock lock, while the lack of Measurement Results from Sample history 140 thwarts optimization of CTLE equalization parameters by Control logic 180.

[0034] Some receiver embodiments detect particular sequential transitional data patterns during normal (i.e. locked sampling clock) operation that are associated with, as one example, suitable signal transitions to maintain clock data alignment. Data sequences “01”, “10”, “010”, “101”, “0101”, “1010”, etc. are representative examples of such transitional data patterns. Further embodiments may also identify sequential data patterns associated with high- or low-frequency spectral energy, to inform incremental adjustments of CTLE equalization parameters during normal operation.

[0035] As high transition density is associated with a high frequency spectral content, the previous clock transitional pattern examples also represent sequences having substantial high-frequency spectral energy, while transitional data patterns incorporating low frequency of transitions, such as sequences “000”, “111”, “0000”, “1111” are indicative of lower frequency spectral energy.

[0036] In this context, reference to high, middle, and low frequency energy may be made relative to the Nyquist frequency of ( 1/ 2 * UI ), where “UI” is the Unit Interval or duration of a single bit time at the signal’s data rate. The Fourier transform of a signal consisting of alternating ones and zeroes will have its first or primary energy peak at the Nyquist frequency. Informally, signal energy at lower than the Nyquist frequency is generally associated with signal fidelity across multiple unit intervals, while signal energy above the Nyquist frequency is generally associated with the rise and fall times of signal transitions. Thus, increased high frequency energy (i.e. greater CTLE peaking or high-frequency gain,) produces sharper transition edges and thus wider data eyes, but can also lead to slower and less accurate clock lock using a baud-rate CDA system.

[0037] Even though individual received data bits and sequences of bits cannot be detected reliably in the absence of a locked receive sampling clock, it is observed that the energy spectrum of such sequences can be observed indirectly. FIG. 4 shows examples of a waveform composed of low-, mid-, and high-frequency signal components in differing ratios. For illustrative purposes, multiple instances of the waveform are superimposed, simulating the absence of a locked sampling clock.

[0038] For avoidance of confusion, CTLE equalization settings will subsequently be described first using ratios of high frequency peaking gain to mid-frequency bandpass gain applicable to any CTLE embodiment, then parenthetically as the CTLE configuration setting appropriate for the particular embodiment of FIG. 2 and illustrated in that embodiment’s response curve of FIG. 3 as producing the described ratio. In some embodiments, the CTLE code of the CTLE may be a thermometer code having an analog voltage Vsw provided on a selectable number of outputs and provided to source impedance elements 230 within a plurality of M slices 200 connected in parallel to the load impedance.

[0039] The signal shown as waveform 410 in FIG. 4 is the result of a large ratio of high frequency to mid-frequency gain (produced by a low bandpass gain setting 321 relative to the fixed amount of high frequency gain 310.) Thus, the peak-to-peak or envelope amplitude of this signal is influenced primarily by the energy of that high frequency spectrum range.

[0040] Conversely, the signal shown as waveform 430 is the result of a low ratio of high frequency to mid-frequency gain (produced by a high bandpass gain setting 322 relative to the fixed amount of high frequency gain 310.) Thus, the peak-to-peak or envelope amplitude of this signal is influenced primarily by the energy of the mid-frequency or bandpass spectrum range. Although relative amplitudes depend on both transmission path loss characteristics and CTLE gain characteristics, in most embodiments the peak-to-peak or envelope amplitude of this signal will be as large or larger than that of waveform 410.

[0041] Waveform 420 illustrates an intermediate gain ratio (and intermediate gain setting 323) relative to the maximum and minimum settings associated with the previous two waveforms. In some embodiments, the peak-to-peak or envelope amplitude of this signal will be smaller than both waveforms 410 and 430 due to second-order operational effects. In other words, in those embodiments incremental adjustment from the conditions of 410 through 420 to those of 430 will result in a decrease, a minimum, and then an increase of observed peak-to-peak or envelope amplitude. In other embodiments, waveform 420 may not be smaller than 410, but 430 will still be larger; thus in those embodiments the aforementioned incremental adjustment will show an increase, albeit without an intermediary minimum.

[0042] FIG. 5 is a graph showing the high frequency and mid-frequency gain of one CTLE embodiment as the equalization control code is changed. In some embodiments, the initialization procedure described herein attempts to balance the high-frequency and low-frequency energy of the PAM data signal, illustrated in FIG. 5 by the intersection 510 of the signal peak value curves of the ‘ 111’ and ‘010’ data patterns. While FIG. 5 includes respective curves for the ‘ 111’ and ‘010’ data patterns, it should be noted that such curves are purely for illustrative purposes and do not imply the need for performing pattern verification. It is assumed that by applying the maximum amount of high-frequency peaking, the initial signal peak value of the PAM data signal will be detected while a ‘010’ or ‘ 101’ data pattern is occurring without having to explicitly detect these data patterns. Furthermore, larger signal peak values are detected as compared to the initial signal peak value by virtue of the increase in low frequency energy of the PAM data signal as a result of changes to the CTLE code. Furthermore, while the x-axis of FIG. 5 is in units of time, it should be noted that the ‘010’ and ‘ 111’ curves shown are changing over time as a result of incremental changes in the CTLE code over time. [0043] One embodiment uses a peak detection circuit 195 to estimate the envelope amplitude by measuring the maximum positive (and/or negative) extent of the asynchronous signal. Peak detectors are well represented in the art, the specific design used not being a significant aspect of the invention.

[0044] As an alternative to a hardware peak detection circuit, a procedure using the existing samplers and threshold adjustments may be used; the threshold is incrementally increased from its nominal original value (or decreased, for negative extent,) until no changes are seen in the detected result across multiple samples. As the sampling occurs randomly due to the asynchronous nature of the clock, a sufficient number of samples should be taken after each threshold adjustment to insure that the final adjusted threshold is just above (below) the overall extent of the received signal.

[0045] In one embodiment, a strategy of dynamically adjusting equalization parameters while monitoring the effective peak amplitude of the received signal is used to obtain an initial equalization setting compatible with subsequent receiver operation. It is assumed that the incoming data stream during this procedure consists of a typical mixed data stream presenting a balanced spectrum of low-, mid-, and high-frequency components.

[0046] FIG. 6 is a flow chart of a method 600 in accordance with some embodiments, which may be performed within e.g., control logic 180. As shown, method 600 includes setting 601 the ratio of CTLE high frequency to bandpass gain to its maximum amount or highest ratio (alternatively, setting the bandpass gain to its minimum level relative to a fixed level of high frequency gain,) and setting any CTLE bandwidth limitation to its highest frequency setting or minimum effectiveness. Step 601 further includes measuring, using a signal peak detector circuit or procedure, the signal peak value of the received signal when the ratio of high-frequency energy to low-frequency energy of the PAM data signal is at a maximum, and recording this peak value. Method 600 further includes incrementally decreasing 602 the ratio of CTLE high frequency to bandpass gain in steps (alternatively, incrementally increasing bandpass gain relative to a fixed high frequency gain) while monitoring 603 the signal peak value, until an increase in the measured signal peak value is noted 604 for at least N consecutive decrease steps. If the ratio of CTLE high frequency equalization to bandpass gain reaches 605 its minimum limit or extent (or bandpass gain reaches its maximum extent,) incrementally adjusting 606 the CTLE bandwidth limit control. In such embodiments, adjusting 606 the CTLE bandwidth limit control may include lowering the frequencies of e.g., points A, B, and D in FIG. 3 in each subsequent step. Alternative embodiments may lower the peak magnitude C via adjustments to e.g., the load resistance of the CTLE to provide bandwidth limit control.

[0047] The method 600 provides a startup initialization of CTLE (and in some cases, bandwidth control settings) of the PAM data signal that approximately balances the amount of high- frequency energy in the PAM data signal and the low-frequency energy in the PAM data signal, as described above with relation to waveform 420 of FIG. 4, and the initialized CTLE high frequency equalization and bandwidth settings may then be utilized for subsequent receiver bring- up operations.

[0048] The value of N used in this procedure may vary depending on the granularity of the incremental adjustment steps and the particular receiver design characteristics and may be determined heuristically during initial design or prototype testing. One may observe that continuing the incremental adjustment and testing by “N” steps has two effects; first, providing some measure of statistical smoothing of the test results to avoid spurious measurement errors, and second increasing the final equalization setting by N times the adjustment increment amount. Other embodiments may incorporate other smoothing or transient measurement avoidance mechanisms, and/or may simply offset the final equalization settings by a predetermined amount, resulting in a fully equivalent alternative to the described method.

[0049] FIG. 7 is a block diagram of control logic 180, in accordance with some embodiments. During system startup, the CTLE control 725 may include a multi-bit counting register for storing part of (or all of) the CTLE code and may be initialized to a code value that maximizes the amount of high-frequency energy of the PAM data signal relative to the low-frequency energy of the PAM data signal, e.g., the setting for 321 as shown in FIG. 3. For the purposes of the following description, the control logic 180 makes increments 720 to the CTLE code stored in CTLE control 725 to increase the amount of low-frequency energy relative to the high-frequency energy, however similar embodiments that decrement the value of multi-bit counting register to decrease high-frequency peaking may be envisioned as well.

[0050] As shown, control logic 180 includes a comparator 705 configured to compare the current peak detector value received from peak detector 195 to the previously measured peak detector value, illustrated by delay unit 702. As shown, control logic 180 includes a frame counter 704 that may be configured to allow control logic 180 to make comparisons of the signal peak values and increments to the CTLE code periodically according to e.g., a frame of measurements made on the PAM data signal. Once the interval counter 704 indicates a full frame has been completed, a bit of the frame counter 704 corresponding to an enable signal ‘en’ may initiate (i) comparator 705 to make a comparison, (ii) the delay unit 702 to replace the previously measured signal peak value with the most recent measured signal peak value, and (iii) increment 720 the CTLE code stored in multi-bit counting register within CTLE control 725 to incrementally reduce high- frequency peaking of the PAM data signal. As shown, the CTLE code in CTLE control 725 is incremented when the logical AND 718 of enable signal ‘en’ provided by frame counter 704 is high and the flag bit of multi -bit counting register 715 is low (illustrated by the inverting input to logic AND 718). In such embodiments, continuously monitoring the previously-stored detected peak value may determine intersection point 510 in FIG. 5, which corresponds to the increase in low-frequency energy relative to the high-frequency energy of the PAM data signal while accounting for some lossy-ness in high-frequency gain associated with changing the amount of equalization.

[0051] In alternative embodiments, delay unit 702 may correspond to a register configured to store the initial max signal peak value associated with the high frequency content of the PAM data signal, and after each frame of signaling intervals as determined by interval counter 704 is compared to the initial max signal peak value. In such embodiments, the CTLE code associated with the increase in signal peak value may be determined at point 520, at which point the low frequency energy of the PAM data signal has surpassed the initially determined high frequency energy of the PAM data signal.

[0052] Comparator 705 is configured to detect increases in the signal peak value responsive to changes of the CTLE code stored in multi-bit counting register in CTLE control 725, and upon each detected increase, the least-significant bit (LSB) of multi -bit counting register 715 is incremented 710 via an active-high input indicating that the current signal peak value is higher than the previous signal peak value. In some embodiments, multi -bit counting register 715 may further include an active-low reset input ‘reset’ that is used when detecting consecutive increases in the signal peak value, and thus if the output of comparator 705 indicates that there is no increase in detected signal peak value, the value of multi-bit counting register in CTLE control 725 is reset to 0. Multi -bit counting register 715 further includes a flag bit stored in a most-significant bit (MSB) portion of the register that may correspond to the ‘N’ desired number of consecutive increases, as described above. Once ‘N’ consecutive increases in signal peak value have been detected, increments to the CTLE code stored in multi-bit counting register in CTLE control 725 may be halted via the flag bit reaching a ‘high’ value. [0053] Embodiments above describe storing the CTLE code in a multi-bit counting register. In further embodiments, the CTLE control 725 may further include a digital-to-analog converter (DAC) and thermometer encoder. In such embodiments, the DAC may be used to convert the multi-bit value stored in the multi-bit counting register into an analog voltage Vsw, and the thermometer encoder may be configured to provide the analog voltage Vsw to the source impedance elements 230 of a selectable number of slices according to a thermometer code (shown in FIG. 7 as CTLE code Vsw<M-l:0>). In such embodiments as described in [Rattan], a number of slices 200 receiving the analog voltage (with the remaining slices “disabled” or set in an “open” configuration) sets a fine setting of the high-frequency equalization of the PAM data signal (see FIG. 8, individual lines within groups 802 and 805), and the impedance value of the source impedance elements 230 as determined by the analog voltage Vsw sets a coarse setting of the high-frequency equalization of the PAM data signal (see FIG. 8, groups 802 and 805 representing respective coarse settings). In one example, as the analog value of multi-bit counting register within CTLE control 725 reaches an extreme value associated with a maximum impedance value of source impedance element 230, the thermometer encoder may enable an additional slice 200 of the CTLE.

[0054] In an alternative embodiment, the CTLE control 725 steps through the number of slices 200 receiving a given analog voltage Vsw before adjusting the analog voltage Vsw itself. In one such embodiment, the CTLE of FIG. 2 may be initialized with all slices 200 enabled, and the analog voltage Vsw being associated with a minimum impedance of source impedance element 230. Such a setting initializes the CTLE in a maximum high-frequency peaking configuration. The CTLE control 725 may first adjust the thermometer portion of the code to incrementally disable (e.g., set the source impedance elements 230 to an ‘open’ or high impedance configuration) the number of slices 200 receiving the voltage Vsw associated with the value stored in CTLE control 725. Once the number of slices receiving the analog voltage reaches a minimum, the analog value Vsw portion of the control signal may be adjusted to effectively increase the impedance of source impedance elements 230, and the thermometer encoder may again provide the new analog voltage to all slices 200 of the CTLE and continue to incrementally reduce the number of slices 200 receiving the analog voltage. Such an embodiment incrementally steps through the “fine” settings of the equalization before making adjustments to the “coarse” settings of the equalization, however embodiments operating in reverse order may be considered as well (e.g., stepping through all possible analog voltages Vsw before changing the number of enabled slices 200). [0055] In some embodiments, control logic 180 may be configured to store and output a bandwidth-limiting control signal. In such embodiments, the bandwidth-limiting control may be stored in multi -bit counting register 735, which is only incremented when the CTLE has run out of equalization room. In such embodiments, the control logic 180 may be configured to output the CTLE code associated with minimum high-frequency peaking (e.g., line 322 of FIG. 3), and may begin adjusting bandwidth control via e.g., a bandwidth-limiting code provided to the load impedance R _L of the CTLE shown in FIG. 2. In some such embodiments, the multi-bit counting register 735 may be configured to store a thermometer code, and each load impedance element Ri<n-l>:Ri<0> may have equivalent resistances. In alternative embodiments, the load impedance elements Ri<n-l>:Ri<0> may have differing resistance (e.g., R, 2R, 4R, etc.) and the multi-bit counting register may store a binary value indicative of the load impedance. While adjusting the source impedance elements 230 of the CTLE of FIG. 2 increases the amount of low-frequency gain while maintaining a relatively constant high-frequency gain, the bandwidth limiting control actively attenuates the amount of high-frequency gain to balance the high and low frequency energies of the PAM data signal.

[0056] While embodiments above describe finding the CTLE code associated with the initial increases in signal peak value, it should be noted that the above algorithms may be extrapolated to find larger amounts of low-frequency energy of the PAM data signal relative to the high- frequency energy of the PAM data signal. For example, after determining the initial signal peak value associated with the high frequency of the PAM data signal, the CTLE code may be adjusted until the signal peak detector identifies a signal peak value that is larger than the initial signal peak value by a predetermined amount. In such embodiments, the multi -bit counting register 715 may be configured to count a larger predetermined number of signal peak increases (i.e., a number associated with an approximate magnitude rather than the confidence check). Alternatively, the CTLE code may be adjusted until the peak detector value reaches a ratio-metric increase (e.g., 2x the voltage of the initial measured signal peak), an absolute mV increase relative to the initial measured signal peak, or various other predetermined amounts. Such equalization codes may correspond to e.g., the values at t=97ps, where the low-frequency peak is approximately 50% higher than the initial signal peak value (or 35mV of absolute increase relative to the initial signal peak value, depending on the embodiment used). In some embodiments, the flag bit stored in multi -bit counting register 715 may further be purposed to initiate the next step in the startup/calibration process.