CONTROL AND CALIBRATION OF EXTERNAL OSCILLATORS Field of the Disclosure [0001] Embodiments of the invention relate to electronic systems, and more particularly to, control and calibration of external oscillators. BACKGROUND [0002] Voltage-controlled oscillators (VCOs) are widely used in electronic and communication applications, such as clock generation and distribution, carrier synthesis, and data recovery. VCOs can include an oscillator core that generates an oscillating output signal and a resonator (for example, an inductor-capacitor tank) that presents the oscillator core with variable electrical characteristics such as capacitance and/or inductance. The frequency of oscillation depends at least partly on the value of the variable electrical characteristics, and thus tuning the resonator provides a way to control the frequency of oscillation of the output signal. [0003] VCOs can be included in control loops, such as phase-locked loops (PLLs). Such control loops can use feedback to set an input control voltage of the VCO to a desired value. SUMMARY OF THE DISCLOSURE [0004] Apparatus and methods for control and calibration of external oscillators are provided. In certain embodiments, an electronic oscillator system includes a semiconductor die and a controllable oscillator that is external to the semiconductor die. The oscillation frequency of the controllable oscillator is tuned by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor. [0005] In one aspect, an electronic oscillator system includes a semiconductor die, a controllable oscillator external to the semiconductor die, a first varactor configured to tune an oscillation frequency of the controllable oscillator, and a second varactor configured to tune the oscillation frequency of the controllable oscillator. The semiconductor die includes a phase-locked loop (PLL) configured to provide fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit configured to provide coarse tuning to the controllable oscillator by controlling the second varactor. [0006] In another aspect, a method of electronic oscillator control is provided. The method includes tuning an oscillation frequency of a controllable oscillator using a first varactor, the controllable oscillator external to a semiconductor die. The method further includes tuning the oscillation frequency of the controllable oscillator using a second varactor, controlling the first varactor to provide fine tuning to the controllable oscillator using a phase- locked loop (PLL) on the semiconductor die, and controlling the second varactor to provide coarse tuning to the controllable oscillator using a calibration circuit of the semiconductor die. [0007] In another aspect, a radio frequency communication system is provided. The radio frequency communication system includes a mixer controlled by an oscillator signal, and a local oscillator including a semiconductor die, a controllable oscillator external to the semiconductor die and configured to output the oscillator signal, a first varactor configured to tune an oscillation frequency of the controllable oscillator, and a second varactor configured to tune the oscillation frequency of the controllable oscillator. The semiconductor die includes a phase-locked loop (PLL) configured to provide fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit configured to provide coarse tuning to the controllable oscillator by controlling the second varactor. BRIEF DESCRIPTION OF THE DRAWINGS [0008] Figure 1 is a schematic diagram of one embodiment of a radio frequency (RF) communication system. [0009] Figure 2A is a schematic diagram of one example of tuning for an external voltage controllable oscillator (VCO). [0010] Figure 2B is a schematic diagram of another example of tuning for an external VCO. [0011] Figure 3A is a schematic diagram of an electronic oscillator system according to one embodiment. [0012] Figure 3B is a schematic diagram of an electronic oscillator system according to another embodiment. [0013] Figure 4 is a schematic diagram of an external VCO tracking loop according to one embodiment. [0014] Figure 5A is a schematic diagram of an external VCO tracking loop according to another embodiment. [0015] Figure 5B is a schematic diagram of an external VCO tracking loop according to another embodiment. [0016] Figure 6 is a schematic diagram of an electronic oscillator system according to another embodiment. [0017] Figure 7 is a schematic diagram of another embodiment of an electronic oscillator system including a semiconductor die operating in a first coarse calibration mode. [0018] Figure 8 is a schematic diagram of another embodiment of an electronic oscillator system including a semiconductor die operating in a second coarse calibration mode. DETAILED DESCRIPTION [0019] The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways. In this description, reference is made to the drawings where like reference numerals may indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings. [0020] Control and calibration of external controllable oscillators are provided herein. In certain embodiments, an electronic oscillator system includes a semiconductor die and a controllable oscillator (for instance, a VCO) that is external to the semiconductor die. The oscillation frequency of the controllable oscillator is tuned by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor. [0021] Accordingly, the controllable oscillator can be controlled using a first loop with low gain and a second loop with higher gain than the second loop. This in turn achieves low noise, wide tuning range, and an ability to implement the PLL on the semiconductor die while operating within supply voltage limitations associated with typical semiconductor die manufacturing processes. [0022] The teachings herein are applicable to a wide range of electronic systems and applications. For example, transceivers, such as land mobile radio transceivers, can employ external VCOs as local oscillators (LOs). [0023] Figure 1 is a schematic diagram of one embodiment of an RF communication system 30. The RF communication system 30 includes a transceiver 1, a front- end system 2, and an antenna 3. The transceiver 1 of Figure 1 can include one or more local oscillators (LOs) implemented with tuning and calibration loops in accordance with the teachings herein. However, the teachings herein are applicable to other configurations of electronic circuitry. [0024] In the illustrated embodiment, the transceiver 1 includes a transmitter 5 and a receiver 6. Although not depicted in Figure 1, the transceiver 1 can also include other circuitry, for example, observation receivers, control circuits, and/or additional transmitters and/or receivers. [0025] Although Figure 1 depicts the transceiver 1 as including one transmitter and one receiver, the transceiver can include additional transmitter(s), receiver(s), and/or observation receiver(s). [0026] In the illustrated embodiment, the transmitter 5 includes an I-path DAC 11a, an I-path amplifier 12a, an I-path mixer 13a, a Q-path DAC 11b, a Q-path amplifier 12b, a Q- path mixer 13b, and a transmit local oscillator (LO) 14. Although one example of transmitter circuitry is depicted, a transmitter can be implemented in other ways. [0027] With respect to signal transmission, the I-path DAC 11a converts a digital I signal to an analog I signal, which is amplified by the I-path amplifier 12a. Additionally, the Q-path DAC 11b converts a digital Q signal to an analog Q signal, which is amplified by the Q-path amplifier 12b. The transmit LO 14 provides an I-path clock signal to the I-path mixer 13a, which upconverts the amplified analog I signal. The transmit LO 14 further provides a Q-path clock signal to the Q-path mixer 13b, which upconverts the amplified analog Q signal. The outputs of the I-path mixer 13a and the Q-path mixer 13b are combined to generate an RF transmit signal TX that is provided to the front-end system 2. [0028] With continuing reference to Figure 1, the receiver 6 includes an I-path ADC 21a, an I-path amplifier 22a, an I-path mixer 23a, a Q-path ADC 21b, a Q-path amplifier 22b, a Q-path mixer 23b, and a receive LO 24. Although one example of receiver circuitry is depicted, a receiver can be implemented in other ways. [0029] With respect to signal reception, the receiver 6 receives an RF receive signal RX from the front-end system 2. The receive LO 24 provides an I-path clock signal to the I- path mixer 23a and a Q-path clock signal to the Q-path mixer 23b. The I-path mixer 23a downconverts the RF receive signal RX using the I-path clock signal to generate an analog I signal. The analog I signal is amplified by the I-path amplifier 22a and digitized by the I-path ADC 21a to generate a digital I signal. The Q-path mixer 23b downconverts the RF receive signal RX using the Q-path clock signal to generate an analog Q signal. The analog Q signal is amplified by the Q-path amplifier 22b and digitized by the Q-path ADC 21b to generate a digital Q signal. [0030] The transceiver 1 can be implemented in accordance with any of the embodiments herein. [0031] As shown in Figure 1, the front-end system 2 includes a power amplifier 27 that amplifies the RF transmit signal TX for transmission on the antenna 3, and a low noise amplifier 28 that generates the RF receive signal RX based on amplifying a received signal from the antenna 3. Although only the power amplifier 27 and the low noise amplifier 28 are depicted, the front-end system 2 can include other components including, but not limited to, filters, switches, duplexers, diplexers, couplers, and/or other components. Moreover, transmit and receive channels need not share an antenna, but rather can use separate antennas. [0032] The transceiver 1 can handle signals of a variety of frequencies, including not only RF signals between 30 MHz and 7 GHz, but also signals of higher frequencies, such as those in the X band (about 7 GHz to 12 GHz), the Ku band (about 12 GHz to 18 GHz), the K band (about 18 GHz to 27 GHz), the K _a band (about 27 GHz to 40 GHz), the V band (about 40 GHz to 75 GHz), and/or the W band (about 75 GHz to 110 GHz). Accordingly, the teachings herein are applicable to a wide variety of RF communication systems, including microwave systems. [0033] Figure 2A is a schematic diagram of one example of tuning for an external VCO. In this example, the external VCO is tuned using one loop having a frequency versus voltage gain (KVCO) of 11MHz/volt. When using a 9 V tuning range (from 0.5 V to 9.5 V), the external VCO has 100 MHz of frequency range to account for desired tuning range as well as process, voltage, and/or temperature (PVT) variation. [0034] Figure 2B is a schematic diagram of another example of tuning for an external VCO. In this example, the external VCO is tuned using a first loop for fine tuning having a K _VCO1 of 1MHz/volt and a second loop for coarse tuning having a K _VCO2 of 11MHz/volt. The first loop operates with a relative small voltage tuning range of 1V, allowing the first loop to be implemented on a semiconductor die while still operating within typical supply voltage limitations associated with semiconductor die manufacturing processes. The first loop also has low gain, which is better for noise. The second loop operates with a wide voltage tuning range of 9V (from 0.5 V to 9.5 V) to provide wide frequency range of 100 MHz to account for PVT. [0035] Although various examples of K _VCO values, voltage ranges, and frequencies have been shown in Figures 2A and 2B, other values are possible. [0036] Figure 3A is a schematic diagram of an electronic oscillator system 50 according to one embodiment. The electronic oscillator system 50 includes a semiconductor die 41 and a controllable oscillator 42 that is external to the semiconductor die 41. The electronic oscillator system 50 further includes a first varactor 43 controlled by a fine control signal FINE from the semiconductor die 41 and a second varactor 44 controlled by a coarse control signal COARSE from the semiconductor die 41. [0037] As shown in Figure 3A, the controllable oscillator 42 outputs an oscillation signal OSC that has a frequency of oscillation that is controlled by the fine control signal FINE and by the coarse control signal COARSE. [0038] Accordingly, the oscillation frequency of the controllable oscillator 42 is tuned by the first varactor 43 and the second varactor 44. [0039] With continuing reference to Figure 3A, the semiconductor die 41 includes a phase-locked loop (PLL) 45 that provides fine tuning to the controllable oscillator 42 by controlling the fine control signal FINE provided to the first varactor 43. Additionally, the semiconductor die 41 further includes a calibration circuit 46 that provides coarse tuning to the controllable oscillator 42 by controlling the coarse control signal COARSE provided to the second varactor 44. The oscillation signal OSC is provided to the semiconductor die 41 to provide feedback for adjusting the fine control signal FINE and the coarse control signal COARSE. [0040] By implementing the electronic oscillator system 50 in this manner, the controllable oscillator 42 can be controlled using a first loop with low gain (LOW GAIN loop) and a second loop with higher gain (HIGH GAIN loop). This in turn achieves low noise, wide tuning range, and an ability to implement the PLL 45 on the semiconductor die 41 while operating within supply voltage limitations associated with typical semiconductor die manufacturing processes. [0041] Figure 3B is a schematic diagram of an electronic oscillator system 130 according to another embodiment. The electronic oscillator system 130 includes a semiconductor die 101 and a variety of components external to the semiconductor die 101 on a circuit board. [0042] In the illustrated embodiment, the external components include an external VCO 102, a first varactor 103, a second varactor 104, a first amplifier 105, a second amplifier 106, a temperature sensor 107, a VCO input capacitor 108, a VCO output capacitor 109, a VCO bias inductor 110, a first varactor series capacitor 111a, a second varactor series capacitor 111b, a first varactor biasing inductor 112a, a second varactor biasing inductor 112b, a coarse resistor bypass switch 113a, a bias resistor bypass switch 113b, a coarse resistor 114a, a bias resistor 114b, first voltage divider resistors 115a/115b, second voltage divider resistors 116a/116b, a first amplifier input resistor 117a, a second amplifier input resistor 117b, a bias capacitor 118, a fine capacitor 119a, a sense capacitor 119b, and a coarse capacitor 120. [0043] The semiconductor die 101 of Figure 3B includes a PLL 121, a coarse tuning and calibration circuit 122, an auxiliary analog-to-digital converter (ADC) 123, a PVT and coarse tuning digital-to-analog converter (DAC) 124, an amplitude DAC 125, and a switchable resistor network 126. The switchable resistor network 126 includes a fixed resistor 127, a switchable resistor 128, and a resistor bypass switch 129. The semiconductor die 101 also including various pins or pads including a coarse tuning pin V _coarse , a fine tuning pin V _fine , a range sensing pin V _Z , a VCO sensing pin V _vco , and a VCO biasing pin V _bias . [0044] The external VCO 102 is tuned by both the first varactor 103 and the second varactor 104. The first varactor 103 is controlled by the voltage of the fine tuning pin V _fine set by the PLL 121, which can operate with low voltage (for instance, using a 1 V charge pump 132). As shown in Figure 3B, the PLL 121 receives the VCO’s clock signal on the VCO sensing pin V _vco , which can be used to generate a feedback clock signal for the PLL’s detector. For example, the PLL 121 can include a phase and/or frequency detector (PFD) 133 that compares the feedback clock signal to a reference clock signal, and the output of the PFD is used to control the PLL’s charge pump 132. [0045] The second varactor 104 is controlled by the coarse tuning and calibration circuit 122, which can include tuning circuitry 131 for PVT, temperature coefficient (TC), and/or amplitude control. The coarse tuning and calibration circuit 122 provides a digital coarse control signal to the DAC 124, which outputs a current to the coarse tuning pin V _coarse . Although shown as a single DAC 124 for providing PVT and coarse tuning, multiple DACs can be used. [0046] The current flows from the DAC 124 through a resistor 117a to generate a coarse tuning voltage that is scaled by the amplifier 105 to generate a scaled coarse tuning voltage that tunes the second varactor 104. Although an example in which the coarse tuning voltage is generated by a current flowing a current DAC through a resistor, other implementations are possible, such as configurations in which a voltage DAC generates the coarse tuning voltage. The external amplifier 105 is used to amplify the voltage on Vcoarse to a voltage level suitable for varactor control, for instance, up to about 20V. The external amplifier 105 is powered by a varactor voltage supply V _VAR suitable for generating such voltage levels. The noise from the amplifier 105 is filtered by a low frequency RC filter that can be selectively bypassed (for instance, during calibration). [0047] In this example, the coarse tuning and calibration circuit 122 receives temperature information from the temperature sensor 107 by way of the ADC 123, as well as the VCO’s output clock signal from the VCO sensing pin Vvco and tuning range information from the range sensing pin V _Z . [0048] In certain implementations, the coarse tuning and calibration circuit 122 initially performs a VCO amplitude calibration based on biasing the external VCO 102 using the VCO biasing pin Vbias (and using the second amplifier 106 powered by bias supply voltage VDDB to provide scaling) and based on observations of the VCO output clock signal from the VCO sensing pin V _vco . After the initial amplitude calibration, the coarse tuning and calibration circuit 122 can coarsely tune the external VCO 102 using the second varactor 104. [0049] During normal operation after amplitude calibration and coarse tuning, the PLL 121 serves to provide fine tuning to the external VCO 102 by way of controlling the first varactor 103. Additionally, the coarse tuning and calibration circuit 122 can monitor the tuning voltage of the PLL 121 using the range sensing pin V _Z , and perform a coarse adjustment when the tuning voltage exceeds an upper threshold or falls below a lower threshold. Thus, the coarse adjustment can serve to maintain the tuning voltage within a desired tuning voltage range set by the upper and lower thresholds. [0050] Although an example with VCO amplitude scaling has been described, such amplitude scaling can be omitted. For example, the amplitude DAC 125 and the second amplifier 106 need not be included for bringing the external VCO 102 to a desired target amplitude. [0051] Figure 4 is a schematic diagram of an external VCO tracking loop 210 according to one embodiment. The external VCO tracking loop 210 includes a coarse control resistor 201 on a board, and a low-pass filter 202 and a control loop core 203 formed on a semiconductor die that is attached to the board. [0052] Although certain components are shown as being on the board or on the semiconductor die, other arrangements are possible. [0053] The control loop core 203 can be an analog loop or a digital loop. The control loop core 203 monitors the range sensing signal V _z (generated by sensing the fine voltage used to control the fine varactor) by comparing the signal V _z against an upper threshold (V _{tune_up} ) and a lower threshold (V _{tune_dn} ). The external VCO tracking loop 210 sets the value of the signal V _coarse such that the value of the signal V _z (and thus the fine tuning voltage V _fine of Figure 3B) is kept between the two thresholds. The external VCO tracking loop can receive temperature information 204 (T _BOARD ), in some implementations. [0054] In the illustrated embodiment, the low-pass filter 202 is included for filtering the signal V _z . The low-pass filter 202 includes a series resistor 207 and a shunt capacitor 208, in this example. [0055] Figure 5A is a schematic diagram of an external VCO tracking loop 230 according to another embodiment. The external VCO tracking loop 230 includes a coarse control resistor 201 on a board, and a low-pass filter 202, a first comparator 211, a second comparator 212, a comparator processing circuit 213, an adder 219, and a PVT/TC DAC 220 formed on a semiconductor die that is attached to the board. [0056] In this embodiment, analog hysteretic comparators 211/212 are used to compare the sense voltage V _z (after low-pass filtering by the low-pass filter 202) to the upper threshold V _{tune_up} and the lower threshold V _{tune_dn} . Additionally, the comparator outputs are processed by the comparator processing circuit 213, which includes an up/down counter 215, a flip-flop 216 (controlled by a clock signal CLK), an integrator 217, and a modulator 218. The output of the comparator processing circuit 213 is added in the digital domain to the PVT code 221 set by the PVT calibration loop, and thereafter provided to the PVT/TC DAC 220. [0057] Figure 5B is a schematic diagram of an external VCO tracking loop 240 according to another embodiment. [0058] The external VCO tracking loop 240 of Figure 5B is similar to that of the external VCO tracking loop 230 of Figure 5A, except that separate DACs 231 are used PVT and TC. Thus, a TC DAC 232 is included for temperature control and a PVT DAC 233 is provided for PVT control, with the DAC outputs combined. Implementing the system in this manner can reduce DAC dynamic range specifications. [0059] Figure 6 is a schematic diagram of an electronic oscillator system 430 according to another embodiment. The electronic oscillator system 430 includes a semiconductor die 401 and a variety of components external to the semiconductor die 401 on a circuit board. [0060] In the illustrated embodiment, the external components include an external VCO 402 (powered by a varactor supply voltage V _{CC_VCO} ), a first varactor 103, a second varactor 104, a first amplifier 105, a second amplifier 106, a temperature sensor 107, a VCO input capacitor 108, a VCO output capacitor 109, a first varactor series capacitor 111a, a second varactor series capacitor 111b, a first varactor biasing inductor 112a, a second varactor biasing inductor 112b, a coarse resistor bypass switch 113a, a coarse resistor 114a, a bias capacitor 118, a fine capacitor 119a, a sense capacitor 119b, a coarse capacitor 120, a VCO clock buffer 403, and a coarse voltage scaling circuit 404. [0061] The semiconductor die 401 of Figure 6 includes a PLL 421, a coarse frequency tuning and temperature compensation (TC) calibration circuit 422 (also referred to as a coarse frequency tuning and TC calibration loop), an auxiliary analog-to-digital converter (ADC) 123, a switchable resistor network 126, and an analog/digital interface 423. The switchable resistor network 126 includes a fixed resistor 127, a switchable resistor 128, and a resistor bypass switch 129. The semiconductor die 401 also including various pins or pads including a coarse tuning pin Vcoarse, a fine tuning pin Vfine, a range sensing pin V _Z , and a VCO sensing pin V _vco . [0062] The external VCO 402 is tuned by both the first varactor 103 (fine varactor) and the second varactor 104 (coarse varactor). The first varactor 103 is controlled by the voltage of the fine tuning pin Vfine set by the PLL 421, which operates with a low voltage (1 V or less, in this example) charge pump. As shown in Figure 6, the PLL 421 receives the VCO’s clock signal (through clock driver 403, in this example) on the VCO sensing pin Vvco. [0063] The second varactor 104 (coarse varactor) is controlled by the coarse frequency tuning and TC calibration loop 422, which controls a value of the coarse voltage pin Vcoarse by way of the analog/digital interface 423. The voltage level of the coarse voltage pin Vcoarse stepped up by the coarse voltage scaling circuit 404 to set a bias voltage of the second varactor 104 (coarse varactor). The coarse voltage scaling circuit 404 can include a level shifter, an amplifier, a charge pump, and/or other suitable circuit that serves to step up the bias voltage of the coarse varactor 104 from a low voltage domain associated with the semiconductor die 401 to a high voltage domain associated with the external VCO 402. [0064] Figure 7 is a schematic diagram of another embodiment of an electronic oscillator system 460 including a semiconductor die 431 operating in a first coarse calibration mode. [0065] The electronic oscillator system 460 includes the semiconductor die 431 and a circuit board including various external components to the semiconductor die 431. The external components include an external VCO 402 (powered by a 5V supply, in this example), a first varactor 103, a second varactor 104, a temperature sensor 107, a VCO input capacitor 108, a VCO output capacitor 109, a first varactor series capacitor 111a, a second varactor series capacitor 111b, a first varactor biasing inductor 112a, a second varactor biasing inductor 112b, a fine capacitor 119a, a sense capacitor 119b, a VCO clock buffer 403, a first current mirror transistor 433, a second current mirror transistor 434, a current mirror load resistor 435 (coupled to a 20V supply, in this example), a coarse bias resistor 436, a first current mirror load capacitor 437, a second current mirror load capacitor 438, a first calibration switch Scal1, a coarse integration capacitor C _i , and a sense resistor R _z . [0066] The semiconductor die 431 of Figure 7 includes a PLL 451, a coarse frequency tuning/ switch control calibration circuit 452, an auxiliary ADC 123, an auxiliary switch Saux, a calibration DAC 453, a calibration DAC reference current source Iref, a calibration DAC reference current switch S _ref (used in combination with I _ref to calibrate the DAC 453, in some implementations), a second calibration switch S _cal2 , a third calibration switch S _cal3 , a calibration up switch Scalup, a calibration down switch Scaldn, an up current source Iup, a down current source Idn, first charging switches Schg1, a second charging switch Schg2, a third charging switch S _chg3 , charging resistors R _chg (connected between a 1.8V supply and ground when S _chg1 are closed), a first controllable transconductance circuit G _m1 (receiving a reference voltage Vref), and a second controllable transconductance circuit G _m2 (receiving the reference voltage V _ref ). The semiconductor die 431 also including various pins or pads including a coarse tuning pin Vcoarse, a fine tuning pin Vfine, a range sensing pin V _Z , a coarse integration pin V _{coarse_int} , and a VCO sensing pin V _vco . [0067] The external VCO 402 is tuned by both the first varactor 103 (fine varactor) and the second varactor 104 (coarse varactor). The first varactor 103 is controlled by the voltage of the fine tuning pin Vfine set by the PLL 451, which includes a PFD 455 (receiving a reference clock signal CLKref and a feedback clock signal), a charge pump 456, and a feedback divider 457. [0068] The second varactor 104 (coarse varactor) is controlled by the coarse frequency tuning/ switch control calibration circuit 452, which controls the calibration DAC 453 as well as the state of the depicted switches. The coarse frequency tuning/ switch control calibration circuit 452 receives a temperature signal Dtemp from the auxiliary ADC 123, and provides a calibration DAC code Dcal to the calibration DAC 453. [0069] The semiconductor die 431 is operable in multiple modes for controlling the coarse voltage pin V _coarse . The modes include a first mode (DAC/G _m -C mode) in which the calibration DAC 453 and the transconductance circuits G _m1 and G _m2 are used for coarse calibration, and a second mode (charge pump/G _m -C mode) in which the calibration charge pump (Scalup, Iup, Idn, and Scaldn) and the first transconductance circuit G _m1 are used for coarse calibration. [0070] An electronic oscillator system can be implemented with a selection of board components desired for a particular application, and the semiconductor die 431 can provide coarse calibration using the first mode (DAC/G _m -C mode) or the second mode (charge pump/G _m -C mode) based on the chosen board components for that application. For example, the first mode (DAC/G _m -C mode) can provide less performance with less board complexity, while the second mode (charge pump/G _m -C mode) can provide higher performance at the cost of increased board component complexity. [0071] The electronic oscillator system 460 of Figure 7 is implemented with external components suitable for operating in the first mode (DAC/G _m -C mode). Table 1 below depicts operation of three states of the first mode (DAC/G _m -C mode), where ON=1 and OFF=0. The states are operated in sequence, beginning with a reset state, thereafter transitioning to a calibration state, and ending in a tracking state. The reset state is used to reset voltage levels of nodes, while the calibration state is used to calibrate the voltage levels to suitable values. Thereafter, the tracking state is entered in which the transconductance circuits G _m1 /G _m2 control the coarse voltage pin Vcoarse based on the ranging sensing pin V _z . In this example, current integration is provided by the integration capacitor C _i , and in the tracking mode the second transconductance stage G _m2 buffers the integration capacitor’s voltage to control the coarse voltage pin Vcoarse. In this example, a current mirror is controlled by the coarse voltage pin Vcoarse to thereby control the biasing of the coarse varactor 104.

Table 1 [0072] One embodiment of the first mode will now be described with reference to Figure 7. In this embodiment, the coarse frequency tuning/ switch control calibration circuit 452 operates as a finite state machine (FSM) that begins in the reset state. Additionally, during reset, PLL blocks are powered up by separate power up signals from the local serial peripheral interface (SPI) residing in the PLLs (can be initiated by firmware). Additionally, external VCOs, synth, and external circuits are powered up and ready for calibration (can be initiate by firmware). [0073] The FSM transitions from the reset state to the calibration state when a new frequency is written to the semiconductor die 431. In the calibration state, the PLL loops can be opened, and the PFD put in reset. Additionally, the FSM can perform a search (for instance, a binary search or a linear search) for the calibration DAC code D _cal . For example, binary search can start with most significant bit (MSB) high, and the current from the DAC generates a coarse voltage for the external VCO using the external bipolar transistor and RC components. After each DAC bit trial, wait for a programmable amount of time for DAC to settle before starting frequency measurement. The measured frequency of the external VCO can be compared to the PLL reference frequency or a frequency derived from the PLL reference frequency or to a predetermined target value. Furthermore, once all the bits of the calibration DAC 453 have been exercised, the FSM moves to the tracking state. [0074] In the tracking state, the charge pump tri-stating is released (through control of the PFD), and thereafter tracking is provided by locking of the VCO calibration loop by transconductance circuits G _m1 and G _m2 as well as integration capacitor Ci where the first transconductance circuit G _m1 senses the fine voltage, compares it to a reference and generates current to drive the second transconductance circuit G _m2 . Additionally, the second transconductance compares the output to a reference and further drives the coarse tuning voltage pin V _coarse . [0075] Figure 8 is a schematic diagram of another embodiment of an electronic oscillator system 470 including a semiconductor die operating in a second coarse calibration mode. [0076] The electronic oscillator system 470 includes the semiconductor die 431 and a circuit board including various external components to the semiconductor die 431. The external components include an external VCO 402 (powered by a 5V supply, in this example), a first varactor 103, a second varactor 104, a temperature sensor 107, a VCO input capacitor 108, a VCO output capacitor 109, a first varactor series capacitor 111a, a second varactor series capacitor 111b, a first varactor biasing inductor 112a, a second varactor biasing inductor 112b, a fine capacitor 119a, a sense capacitor 119b, a VCO clock buffer 403, an amplifier 461, a feedback integration capacitor 462, and a sense resistor R _z . [0077] The semiconductor die 431 of Figure 8 includes a PLL 451, a coarse frequency tuning/ switch control calibration circuit 452, an auxiliary ADC 123, an auxiliary switch S _aux , a calibration DAC 453, a calibration DAC reference current source I _ref , a calibration DAC reference current switch Sref, a second calibration switch S _cal2 , a third calibration switch Scal3, a calibration up switch Scalup, a calibration down switch S _caldn , an up current source Iup, a down current source Idn, first charging switches Schg1, a second charging switch S _chg2 , a third charging switch S _chg3 , charging resistors R _chg (connected between a 1.8V supply and ground when Schg1 are closed), a first controllable transconductance circuit G _m1 (receiving a reference voltage Vref), and a second controllable transconductance circuit G _m2 (receiving the reference voltage V _ref ). The semiconductor die 431 also including various pins or pads including a coarse tuning pin Vcoarse, a fine tuning pin Vfine, a range sensing pin V _Z , a coarse integration pin V _{coarse_int} , and a VCO sensing pin V _vco . [0078] The external VCO 402 is tuned by both the first varactor 103 (fine varactor) and the second varactor 104 (coarse varactor). The first varactor 103 is controlled by the voltage of the fine tuning pin V _fine set by the PLL 451, which includes a PFD 455 (receiving a reference clock signal CLK _ref and a feedback clock signal), a charge pump 456, and a feedback divider 457. [0079] As discussed earlier with reference to Figure 7, the semiconductor die 431 is operable in multiple modes for controlling the coarse voltage pin Vcoarse. The modes include a first mode (DAC/G _m -C mode) in which the calibration DAC 453 and the transconductance circuits G _m1 and G _m2 are used for coarse calibration, and a second mode (charge pump/Gm-C mode) in which the calibration charge pump (Scalup, Iup, Idn, and Scaldn) and the first transconductance circuit G _m1 are used for coarse calibration. [0080] The electronic oscillator system 470 of Figure 8 is implemented with external components suitable for operating in the second mode (charge pump/G _m -C mode). Table 2 below depicts operation of three states of the second mode (charge pump/G _m -C mode), where ON=1 and OFF=0. The states are operated in sequence, beginning with a reset state, thereafter transitioning to a calibration state, and ending in a tracking state. The reset state is used to reset voltage levels of nodes, while the calibration state is used to calibrate the voltage levels to suitable values. Thereafter, the tracking state is entered in which the transconductance stage G _m1 control the coarse voltage pin Vcoarse based on the ranging sending pin V _z . In this example, integration of a coarse voltage is provided externally by the amplifier 461 and the feedback integration capacitor 462. The output of the amplifier 461 (in a 20 V domain, in this example) controls the biasing of the coarse varactor 104. Table 2 [0081] One embodiment of the second mode will now be described with reference to Figure 8. In this embodiment, the coarse frequency tuning/ switch control calibration circuit 452 operates as an FSM that begins in the reset state. In the reset state, PLL blocks are powered up by separate power up signals from the local SPI residing in the PLLs (can be initiated by firmware). Additionally, external VCOs, synth, and external circuits are powered up and ready for calibration (can be initiate by firmware). [0082] The FSM transitions from the reset state to the calibration state when a new frequency is written to the semiconductor die 431. In the calibration state, the PLL loops can be opened, and the PFD put in reset. Additionally, the FSM sets the up and down controls of the calibration charge pump (Scalup and Scaldn), and the current from the calibration charge pump is integrated on the external capacitor 462 according to the polarity of the current from the calibration charge pump which is either sourcing current (when S _calup is on) or sinking current (when Scaldn is on). After waiting for a programmable amount of time for settling, the frequency of the external VCO 402 is measured. Additionally, the measured VCO frequency to the PLL reference frequency is compared to a frequency derived from the PLL reference frequency or to a predetermined target value. [0083] Once the VCO frequency approaches the target frequency, the FSM moves to the tracking state. In the tracking state, the charge pump tri-stating is released through the PFD, and the tracking loop thereafter performs a lock where the first transconductance circuit G _m1 senses the fine voltage, compares it to a reference and generates current to drive the external amplifier and integration capacitor. Conclusion [0084] The foregoing description may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected). [0085] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and/or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims. [0086] Although the claims presented here are in single dependency format for filing at the USPTO, it is to be understood that any claim may depend on any preceding claim of the same type except when that is clearly not technically feasible.