Description

Controlled current source and method for sourcing a current

The invention relates to a controlled source and to a method for sourcing a current.

In the field of current sources or current sinks an output current can be generated which is controllable by a certain number of bits to tune the exact value of the output current. One existing implementation of such a digitally controlled current source comprises a transistor arrangement for sourcing the output current and a regulation circuit. The transistor arrangement and the regulation circuit are coupled to each other via a set of switches which are directed by a control signal comprising a number of bits. The number of bits determines the number of levels of the digitally controlled source. The number of transistors of the transistor arrangement corresponds to the number of bits. The sizes of the transistors are selected in a way that they increase with 2 ⁿ , with n ranging from zero to the total number of bits. The regulation circuit generates a constant reference current which is used by the transistor arrangement to source the output current depending on the control signal.

In some applications, a controlled current source with less power consumption can be necessary.

It is an objective of the invention to provide an improved controlled current source and an improved method for sourcing a current with less power consumption and less area.

The objective is achieved with the subject matter of the independent patent claims. Embodiments and developments of the invention are subject matter of the dependent claims.

In one exemplary embodiment, a controlled current source comprises a signal input to receive a control input bus signal, a mapping unit, a reference generator and a current generating unit. The mapping unit has an input coupled to the signal input and an output to provide an internal control bus signal. The reference generator has an input coupled to the output of the mapping unit, a low reference output to provide a low reference potential and a high reference output to provide a high reference potential. The current generating unit has a first input coupled to the output of the mapping unit, a second input coupled to the output of the reference generator and an output to provide an output current. The output current is controlled by the control input bus signal and the low and high reference potentials.

The control input bus signal is applied to the mapping unit. The mapping unit provides the internal control bus signal as a function of the control input bus signal. The reference generator generates the low and the high reference potentials. The current generating unit provides the output current as a function of the control input bus signal using the high and low reference potentials. The provisioning of the internal control bus signal is achieved by coding or decoding the control input bus signal.

The structure of the reference generator acting as a regulation circuit results in two reference potentials: The low reference potential which is used for a first subset of current levels provided by the controlled current source and

the high reference potential which is used in addition to the low reference potential for a second subset of current levels provided by the controlled current source. This leads to an improved control strategy with a reduced current consumption and reduced size.

In another exemplary embodiment, the control input bus signal comprises a binary coded digital signal with n bits.

In a further exemplary embodiment, the internal control bus signal comprises a binary coded digital signal with (n+1) bits .

Using the n bit control input bus signal and mapping it into the n+1 bit internal control bus signal, the 2 ⁿ step or level linear controlled current source can be designed. For the first subset of current levels ranging from zero to 2 ^n-1 -l, only the low reference potential is needed. For the second subset of current levels ranging from 2 ^n~ l to 2 ⁿ , the low and the high reference potentials are required to provide the output current .

In one embodiment, the reference generator comprises a second input to receive a first reference current, a second reference current and a defining potential.

By use of the first and second reference currents and the defining potential, the reference generator provides the high and the low reference potentials.

As the high reference potential is only generated for the second half of current levels of the controlled current

source, a significant reduction in power consumption is achieved.

In another exemplary embodiment, the current generating unit comprises a coupling unit and a current sourcing array. The coupling unit comprises the first input of the current generating unit to receive the internal control bus signal, the second input of the current generating unit to receive the low and the high reference potentials and it comprises an output to provide a gate signal bus. The current sourcing array comprises an input coupled to the output of the coupling unit and the output which provides the output current .

The gate signal bus is generated as a function of the internal control bus signal using the low and/or high reference potentials. Applied to the current sourcing array the gate signal bus drives the level of the output current.

In another exemplary embodiment the current sourcing array comprises an array of transistors coupled in parallel, with their gate terminals coupled to the output of the coupling unit. At the same time, sizes s of the transistors of the array of transistors defined as a quotient of channel width and length are selected as a product of 0.5 and 2 ^X , with x ranging from 0 to n-1, and a size of the last transistor matching the respective size of the second-last transistor. The transistors can be implemented as metal oxide semiconductor, MOS, transistors.

The transistors of the current sourcing array are operated as current sources with the ability to provide a current with a value depending on the size s of the respective transistor.

The gate signal bus controls the respective transistor or transistors .

As the sizes s of the last and the second-last transistors match one another, a reduction in layout is achieved compared to existing implementations where the size of the last transistor is twice the size of the second-last transistor.

In another exemplary embodiment, the reference generator comprises a first and a second equalizer, as well as a first and a second differential amplifier. The first equalizer provides a first threshold potential corresponding to the defining potential. The second equalizer provides a second threshold potential corresponding to the defining potential. The first amplifier provides the low reference potential using the first reference current and a first feedback current at the first threshold potential. The second amplifier provides the high reference potential using the second reference current and a second feedback current at the second threshold potential.

The reference generator maintains the low and the high reference potentials at a constant value respectively.

In another exemplary embodiment the control input bus signal comprises an additional control component and the internal control bus signal comprises an additional internal component .

The additional control component and the additional internal component enable the controlled current source to provide a higher range of current levels using the same number of

transistors in the current sourcing array. The range of the current source is extended to 2 ⁿ + 2 ^n~ l -1 current levels.

In another exemplary embodiment the internal control bus signal comprises a second additional internal component.

Using the second additional internal component, the resolution of the controlled current source is enhanced.

In one exemplary embodiment of a method for sourcing a current, a control input bus signal is supplied. Furthermore, a first and a second reference current as well as a defining potential are supplied. An internal control bus signal is provided as a function of the control input bus signal. The internal control bus signal is forwarded to a current generating unit. An output current is generated for a first subset of current levels as a function of the control input bus signal, and a low reference potential, and for a second subset of current levels as a function of the control input bus signal, the low and a high reference potential.

As the generation and the regulation of a reference potential is split up into two parts, namely the low and the high reference potentials, less power is consumed.

The text below explains the invention in detail using exemplary embodiments with reference to the drawings, in which :

Figure 1 shows a first exemplary embodiment of a controlled current source,

Figure 2A shows an exemplary embodiment of a mapping unit of a second exemplary embodiment of a controlled current source,

Figure 2B shows an exemplary embodiment of a current generating unit of the second exemplary embodiment of a controlled current source,

Figure 2C shows a first exemplary embodiment of a reference generator of the second exemplary embodiment of a controlled current source,

Figure 2D shows a second exemplary embodiment of a reference generator of the second exemplary embodiment of a controlled current source, and

Figure 3 shows an exemplary embodiment of a flow diagram of a method for sourcing a current.

Figure 1 shows a first exemplary embodiment of a controlled current source. The controlled current source comprises a mapping unit MU, a current generating unit CG and a reference generator RG. The mapping MU comprises a signal input to receive a control input bus signal DO to D(n-l) and a signal output to provide an internal control bus signal dO to dn and a high control signal Hc. The control input bus signal DO to D(n-l) comprises a binary coded digital signal with n bits. The internal control bus signal dO to dn comprises a binary coded digital signal with (n+1) bits. The reference generator RG comprises a first input which is coupled to the output of the mapping unit, and a second input to receive a defining potential Vd, a first reference current IrI and a second reference current Ir2. The reference generator RG further

comprises a reference output to provide a low reference potential VgI and a high reference output to provide a high reference potential Vgh. The current generating unit CG comprises a coupling unit CU and a current sourcing array CS. The current generating unit comprises a first input coupled to the output of a mapping unit MU, and a second input to receive the low and the high reference potential. The current generating unit CG further comprises an output to provide an output current lout.

Within the mapping unit MU the n bits of the control input bus signal DO to D(n-l) are coded into n+1 bits of the internal control bus signal dO to dn and the high control signal Hc. The internal control bus signal dO to dn and the high control signal Hc are forwarded to the current generating unit CG. The high control signal Hc is forwarded to the reference generator RG, as well. The reference generator RG generates the low and the high reference potentials VgI and Vgh using the defining potential Vd, the first and the second reference currents IrI and Ir2. Within the current generating unit CG the output current lout is generated as a function of the control input bus signal DO to D(n-l) and the low and the high reference potentials VgI and Vgh. The output current lout is provided as a multiple of a step current.

To summarize, a 2 ⁿ step or level digitally controlled current source is realized. For a lower half of codes of the control input bus signal DO to D(n-l) ranging from zero to 2 ^n-1 -l, only the low reference potential VgI is necessary. Therefore, for this range of codes a significant reduction in power consumption is achieved.

The mapping or the coding of the control input bus signal DO to D(n-l) to the internal control bus signal dO to dn can be realized as follows:

Control input bus signal bit D(n-l) is mapped to the high control signal Hc. If the high control signal Hc equals 0, then the internal control bus signal bits dn and dO equal 0, respectively. The internal control bus signal bit d(n-l) equals bit D(n-2) of the control input bus signal, internal control bus signal bit d(n-2) equals control input bus signal bit D(n-3), internal control bus signal bit d(n-3) equals control input bus signal bit D(n-4) and so forth until internal control bus signal bit dl equals control input bus signal bit DO.

If the high control signal Hc equals 1, then internal control bus signal bits dn and d(n-l) equal control input bus signal bit D(n-l), internal control bus signal bit d(n-2) equals control input bus signal bit D(n-2), internal control bus signal bit d(n-3) equals control input bus signal bit D(n-3), internal control bus signal bit d(n-4) equals control input bus signal bit D(n-4) and so forth until internal control bus signal bit dO equals control input bus signal bit DO.

In an extension of this embodiment of the controlled current source, the current source is extended to provide 2 ⁿ +2 ^n~ l steps or current levels. For this, a respective additional component Dn of the control input bus signal DO to D(n-l) is supplied to the mapping unit MU. A first additional internal component El is generated by the mapping unit MU. The coding can be realised as follows: The first internal component El equals the respective additional component Dn. The high control signal Hc, and internal control bus signal bits dn

and d(n-l) equal 1 respectively. Internal control bus signal bit d(n-2) equals control input bus signal bit D(n-2), internal control bus signal bit d(n-3) equals control input bus signal bit D(n-3), internal control bus signal bit d(n-4) equals control input bus signal bit D(n-4) and so forth until internal control bus signal bit dO equals control input bus signal bit DO

With this extension the same controlled current source can provide a higher range of the output current lout.

By using a second additional internal component E2 the above controlled current source can be further extended. The mapping is changed and can be realized as follows:

The second additional internal component E2 equals 1, the first additional internal component El equals 0, the high control signal Hc equals 0, internal control bus signal bit dn equals 0, internal control bus signal bits dn and d(n-l) equal control input bus signal bit D(n-l), internal control bus signal bit d(n-2) equals control input bus signal bit

D(n-2), internal control bus signal bit d(n-3) equals control input bus signal bit D(n-3), and so forth until internal control bus signal bit dO equals control input bus signal bit DO.

With this extension, a refined resolution at half of the step current is achieved for the controlled current source.

Figure 2A shows an exemplary embodiment of a mapping unit of a second exemplary embodiment of a controlled current source. The mapping unit MU comprises nine 2:1 multiplexers MXO, MXl, MX2, MX3, MX4, MX5, MX6, MX7, and MX8. Each of the multiplexers MXO to MX8 comprises two data inputs, one data

output and one control input. Bit D7 of the control input bus signal DO to D7 is applied to every control input of the multiplexers MXO to MX8. For the multiplexers MXl to MX7, two consecutive bits of the control input bus signal DO to D7 are supplied to the respective data inputs, and one bit of the internal control bus signal dO to d8 is provided at the respective data output. In detail, the higher bit of the control input bus signal Do to D7 is supplied to the lower data input and the lower bit of the control input bus signal DO to D7 is supplied to the upper data input of each multiplexer. As an example, bit DO of the control input bus signal DO to D7 is supplied to the upper data input and the bit Dl of the control input bus signal DO to D7 is supplied to the lower data input of the multiplexer MXl . Bit dl of the internal control bus signal dO to d8 is provided at the data output of the multiplexer MXl . For bit D7 of the control input bus signal DO to D7 being at logical 0, the upper data input of each multiplexer MXO to MX8 is forwarded to the respective data output. For bit D7 of the control input bus signal being at logic 1, the lower data input of each multiplexer MXO to MXl is forwarded to its respective data output. In the multiplexer MXO, bit DO of the control input bus signal DO to D7 is multiplexed with logic 0. For the multiplexer MX8, bit D7 of the control input bus signal DO to D7 is multiplexed with logic 0.

With the mapping unit MU depicted in Figure 2A a mapping of codes is realized as demonstrated in Table 1.

Table 1 : mapping of codes

Table 1 shows on the left side all possible codes of the control input bus signal DO to D7. The second half of Table 1 shows the corresponding codes of the internal control bus signal dO to d8. In the adjacent column the coding of the high control signal Hc is shown. In the right-most column of Table 1 the corresponding values of the output current lout are depicted in units of the step current llsb. The value of

the high control signal Hc corresponds to the value of bit D7 of the control input bus signal DO to D7.

Figure 2B shows an exemplary embodiment of a current generation unit of the second exemplary embodiment of a controlled current source. For n equal to 8, the current generation unit CG can be coupled to the mapping unit MU of Figure 2A. Said current generation unit CG comprises a coupling unit CU and a current sourcing array CS. The current sourcing array CS comprises an array of nine transistors MPO, MPl, MP2, MP3, MP4, MP5, MP6, MP7, and MP8. The transistors MPO to MP8 are coupled in parallel with their respective source terminals coupled to a source potential Vs and their respective drain terminals coupled to a defining potential Vd. Gate terminals of the transistors of the array of transistors MPO to MP8 are coupled to a gate signal bus gθ, gl, g2, g3, g4, g5, g6, g7, and g8. As can be seen, gate signal bus component gO is coupled to the gate of transistor MPO, gate signal bus component gl is coupled to the gate of transistor MPl, gate signal bus component g2 is coupled to transistor MP2's gate, gate signal bus component g3 is coupled to the gate terminal of transistor MP3, gate signal bus component g4 is coupled to the gate terminal of transistor MP4, gate signal bus component g5 is coupled to the gate terminal of transistor MP5, gate signal bus component g6 is coupled to the gate terminal of transistor MP6, gate signal bus component g7 is coupled to the gate terminal of transistor MP7 and gate signal bus component g8 is coupled to the gate terminal of transistor MP8. The sizes of the transistors MPO to MP8 are dimensioned such that the respective channel length is always the same, and the channel width increases with a factor of 2 ^X of a reference width w, starting at half of the reference width w, with x ranging

from 0 to 7. It follows that the width of transistor MPO equals 0.5 w, the width of transistor MPl equals w, the width of transistor MP2 equals 2w, the width of transistor MP3 equals 4w, the width of transistor MP4 equals 8w, the width of transistor MP5 equals 16w, the width of transistor MP6 equals 32w and the widths of transistors MP7 and MP8 equal 64w. Transistors MPO to MP8 are implemented as p-channel MOS transistors, for example. The coupling of the drain terminals of the transistors MPO to MP8 to the defining potential Vd also forms the output of the controlled current source which provides an output current lout.

The coupling unit CU comprises a first input to receive the internal control bus signal dO to d8, as well as the high control signal Hc, and a second input to receive the low and the high reference potentials VgI and Vgh. The coupling unit CU further comprises an output to provide the gate signal bus gO to g8. The coupling unit CU also comprises a high switch sθ, two low switches s7 and s8, six low-high switches si, s2, s3, s4, s5 and s6, a first switch sa and a second switch sb, one inverted high switch xsO, two inverted low switches xs7 and xsS8 and six inverted low-high switches xsl, xs2, xs3, xs4, xs5, and xsβ, and an inverter Nl. All the switches mentioned are logic controlled switches which means that a logic high at the control input of the switch turns the switch on. Switches sO to s8 are controlled by the related bit with the same number of the internal control bus signal dO to d8, respectively. Inverted switches sxO to sx8 are controlled by the inverted related bit with the same number xdO to xd8 of the internal control bus signal dO to d8, respectively.

When the high control signal Hc is low which is the case for codes 0 to 127 according to Table 1, the first switch sa is closed via the inverter Nl. The second switch sb is open. It follows that the gate terminals of transistors MPl to MP6 are coupled either to the low reference potential VgI via the low-high switches si to s6, respectively, or they are coupled to the source potential Vs via the inverted low-high switches xsl to xs6 depending on the value of the bits dl to d6 of the internal control bus signal dO to d8, respectively. As soon as one of the gate terminals of transistors MPl to MP6 is coupled to the low reference potential VgI, the respective transistor is turned on and contributes with its respective multiple of the step current Ilsb to the output current lout. For example, transistor MP3 contributes with 4 times the step current Ilsb to the output current lout when turned on. As for the span of codes from 0 to 127 according to Table 1, the bit dO of the internal control bus signal dO to d8 always is 0, the high reference potential Vgh is coupled to the source potential Vs via switch xsO. This means that transistor MPO stays off. Therefore, the regulation of the output current lout is achieved by regulating only the low reference potential VgI.

For the span of codes from 127 to 255 according to Table 1, the high control signal Hc is at logic high or logic 1. It follows that the second switch sb is closed and the first switch sa is opened via the inverter Nl. Therefore, the gate terminals of transistors MPO to MP6 are either coupled to the high reference potential Vgh or they are coupled to the source potential Vs depending on the value of bits dl to d6 of the internal control bus signal dO to d8, respectively. For this span of codes, bits d7 and d8 of the internal control bus signal dO to d8 are at the value 1 according to

Table 1. It follows that the gate terminals of transistors MP7 and MP8 are coupled to the low reference potential VgI. To summarize, for the codes 128 to 255, the low reference potential VgI and the high reference potential both are directing the gates of the transistors MPO to MP8. The step current Ilsb is defined as the current which is provided when bits Dl to D7 of the control input bus signal DO to D7 are at logic low and bit DO of the control input bus signal DO to D7 is at logic high resulting in transistor MPl being switched on.

Consequently, for the first span of codes from 0 to 127, only the low reference potential VgI is needed to provide the output current lout. This results in reduced power consumption. For the second span of codes from 128 to 255 both, the low reference potential VgI and the high reference potential Vgh, are contributing to provide the output current lout. The transition from code 127 to 128 is smooth and without offset error because for code 127 the low reference potential VgI controls the coupling unit CU. For the code 128 the low and the high reference potentials VgI and Vgh are both regulating the output current lout but the high reference potential Vgh controls only the transistor MPO which contributes the step current Ilsb to the output current lout.

As the size of transistor MP7 corresponds to the size of transistor MP8 and equals 64 W, a layout reduction is achieved.

The current generation unit CG described above can be extended to realize a 2 ⁿ step controlled current source by adding supplementary transistors MP9 to MPn to the current

sourcing array CS and by using bits D8 to D(n-l) of the control input bus signal and bits d9 to dn of the internal control bus signal as described under Figure 1. Then sizes of the transistors are chosen as described above for transistors MPO to MP7. Size of transistor MP8 then equals 128w, size of transistor MP9 equals 256w, and size of transistor MP(n-l) corresponds to the size of transistor MPn. Gate terminals of transistors MP(n-l) and MPn can be coupled to the low reference potential VgI depending upon the corresponding bits d(n-l), dn of the internal control bus signal are at logic zero or one. A gate terminal of transistor MPO can be coupled to the high reference potential Vgh depending upon the corresponding bit dO of the internal control bus signal is 0 or 1. Gate terminals of transistors MPl to MP(n-l) can either be coupled to the low reference potential VgI or to the high reference potential Vgh depending upon the high control signal Hc being at logic zero or logic 1 and the corresponding bits dl to d(n-2) are at logic zero or logic 1.

In an extended embodiment which realizes a 2 ⁿ +2 ^n~ l step controlled current source as described under Figure 1, the gate terminals of transistors MPn and MP(n-l) are coupled to the low reference potential VgI if the first additional internal component El is at logic zero. If the first additional internal component El is at logic 1, the gate terminals of transistors MPn and MP(n-l) are coupled to the high reference potential Vgh.

To implement the second extension described under Figure 1, the coupling of the gate terminal of transistor MPO is directed by the second additional internal component E2. If the second additional internal component E2 is at logic zero, the gate of transistor MPO is coupled to the high reference

potential Vgh. If the second additional internal component E2 is at logic one, the gate of transistor MPO is coupled to the low reference potential VgI. By this, the resolution of the controlled current source is half of the step current Ilsb. A range of 0 to (2 ⁿ -l) times half of the step current Ilsb is achieved.

Figure 2C shows a first exemplary embodiment of a reference generator of the second exemplary embodiment of a controlled current source. This embodiment of the reference generator RG comprises a first differential amplifier AO, a second differential amplifier Al, a first equalizer M3, a second equalizer M4 and a control transistor MO. The first and the second equalizer M3 and M4 and the control transistor MO each comprise a p-channel MOS transistor. Source terminals of the first and the second equalizer M3 and M4 as well as a source terminal of the control transistor MO are each coupled to the source potential Vs. A drain terminal of the first equalizer M3 is coupled to a first input of the first differential amplifier AO. A drain terminal of the second equalizer M4 is coupled to a first input of the second differential amplifier Al. A gate terminal of the first equalizer M3 is coupled to the low reference potential VgI. A gate terminal of the control transistor MO is connected to the high control signal Hc. A drain terminal of the control transistor MO is coupled to a gate terminal of the second equalizer M4 which is coupled to the high reference potential Vgh. A first feedback current IsI is a drain source current of the first equalizer M3. A second feedback current Is2 is a drain source current of the second equalizer M4. A potential at the drain terminal of the first equalizer M3 is defined as a first threshold potential VdI . A potential at the drain terminal of the second equalizer M4 is defined as a second threshold

potential Vd2. A first reference current IrI is supplied to the second input of the first differential amplifier AO. A second reference current Ir2 is supplied to the second input of the second differential amplifier Al. The defining potential Vd is supplied to each supply input of the first and the second differential amplifier AO and Al.

The first and the second equalizers M3 and M4, as well as the control transistor MO can be implemented as p-channel MOS transistors, for example.

The length of the first and the second equalizers M3 and M4 correspond to the lengths of transistors MPO to MP 8. The widths of the first and the second equalizers M3 and M4 are selected as follows:

M w(M 3) and

Ilsb w

IsI _ w(MA) Ilsb w

Wherein IsI represents the value of the first feedback current ISl, Is2 represents the value of the second feedback current IS2, Ilsb represents the value of the step current Ilsb, w(M3) represents the value of the with of the first equaliser M3, w(M4) represents the value of the with of the first equaliser M4, and w represents the value of the reference width w. The values for the step current Ilsb, the first and second feedback currents IsI and Is2 are known from the design respectively.

The first differential amplifier AO provides the low reference potential VgI at its output. The low reference

potential VgI is proportional to the difference between the first feedback current IsI and the first reference current IrI. The first differential amplifier AO maintains the first threshold potential VdI at the defining potential Vd. The second differential amplifier Al provides the high reference potential Vgh at its output. The high reference potential Vgh is proportional to the difference between the second feedback current Is2 and the second reference current Ir2. The second differential amplifier Al maintains the second threshold potential Vd2 equal to the defining potential Vd. The control transistor MO ensures that as long as the high control signal Hc is low, the high reference potential Vgh equals the source potential Vs and is not regulated by the second differential amplifier Al. By this, the reduction in power consumption is achieved.

Figure 2D shows a second exemplary embodiment of a reference generator of the second exemplary embodiment of a controlled current source. This embodiment represents a detailed implementation of the embodiment of the reference generator RG described in Figure 2C. This embodiment of the reference generator RG is operated in the same way as described in Figure 2C. This embodiment comprises a low regulation loop, a high regulation loop, a generation circuit for the defining potential Vd and the control transistor MO. The low regulation loop comprises transistors M2, M6, Mil, M12, M15, and the first equalizer M3. The high regulation loop comprises transistors Ml, M7, MlO, M13, M16, and the second equalizer M4. The generation circuit for the defining potential Vd comprises transistors M5, M8, M9, M14, M17, and M18. Transistor M15 is configured to operate as a current source for the first reference current IrI. Transistor M16 is

configured to operate as a current source for the second reference current Ir2.

Transistors Ml, M2, M5, M6, M7, M8, M9, M12, M13, and M14 are implemented as p-channel MOS transistors, for example.

Transistors MlO, Mil, M15, M16, M17, and M18 are implemented as n-channel MOS transistors, for example.

The first feedback current IsI flowing through the first equalizer M3 as its steady state current is equal to the difference between the first reference current IrI and a second bias current Ib2 flowing through transistor M2. The second feedback current Is2 which is the steady state current of the second equalizer M4 is equal to the difference between the second reference current Ir2 and a first bias current IbI flowing through transistor Ml. For the first span of codes from 0 to 127 as of Table 1, the high control signal Hc is low. Therefore, a gate terminal of the second equalizer M4 is coupled to the source potential Vs. It follows that the second equalizer M4 and the transistors M7, M13, and MlO are turned off. When the high control signal Hc equals zero, a bias potential Vb at gate terminal of the transistor MlO can be set to zero. Hence the first bias current IbI and the second feedback current Is2 are zero. Consequently, the second reference current Ir2 also equals zero. This means that for the first span of codes from 0 to 127 only the transistors of the low regulation loop are being operated. For this span of codes, the defining potential Vd and the first threshold potential VdI are maintained equal. For the span of codes from 0 to 127, transistor MPO is always off, therefore a saturation voltage of the controlled current source remains low. For the second span of codes from 128 to 255, the defining potential Vd, the first threshold potential

VdI and the second threshold potential Vd2 are maintained equal by regulation.

The sizes of transistors M6, M7, M8, M12, M13, and M14 are selected as follows:

Wherein w(M7) represents the value of the with of transistor M7 , 1(M7) represents the value of the length of transistor M7, w(M8) represents the value of the with of transistor M8, 1(M8) represents the value of the length of transistor M8, w(M6) represents the value of the with of transistor M6,

1 (M6) represents the value of the length of transistor M6, w(M13) represents the value of the with of transistor M13, 1(M13) represents the value of the length of transistor M13, w(M14) represents the value of the with of transistor M14, 1(M14) represents the value of the length of transistor M14, w(M12) represents the value of the with of transistor M12, 1(M12) represents the value of the length of transistor M12, Ir2 represents the value of the second reference current Ir2, IbI represents the value of the first bias current IbI, IdI represents the value of a first defining current IdI, and Id2 represents the value of a second defining current Id2.

The size of transistor M9 matches the size of transistor M8.

Figure 3 shows an exemplary embodiment of a flow diagram of a method for sourcing a current. In a first step 21, the control input bus signal DO to D(n-l) is supplied. In a second step 22, the first reference current IrI, the second reference current Ir2, and the defining potential Vd are supplied. In a third step 23, the internal control bus signal dO to dn is provided as a function of the control input bus signal DO to D(n-l) . The low reference potential VgI and the high reference potential Vgh are generated in a fourth step 24. The internal control signal dO to dn is forwarded to the current generating unit CG in the fifth step 25. In a sixth step 26, the output current lout is generated as a function of the control input bus signal DO to D(n-l), as well as the low and the high reference potentials VgI and Vgh.

In other embodiments of a method for sourcing a current, different sequences of steps 21 to 26 can also be realized as long as causal relations between the steps 21 to 26 are adhered to.

Reference list

DO, .. ,

D(n-l) control input bus signal dθ, .. , dn internal control bus signal

El first additional internal component

E2 second additional internal component

Hc high control signal MU mapping unit

CU coupling unit

CG current generating unit

CS current sourcing array

RG reference generator gθ, .., g8 gate signal bus

VgI low reference potential

Vgh high reference potential lout output current

IrI first reference current Ir2 second reference current

IsI first feedback current

Is2 second feedback current

Vd defining potential

VdI first threshold potential Vd2 second threshold potential

AO first differential amplifier

Al second differential amplifier

MPO, ..,

MP (n) transistor M3, M4 equaliser

MXO, .. ,

MX8 multiplexer

Ilsb step current

Vs source potential

SO, .. , s8 switches

XsO, .. xs8 switches

Sa, sb switches

MO, Ml,

M2 transistor

M5, ..,

Ml 8 transistor

IbI first bias current

Ib2 second bias current

IdI first defining current

Id2 second defining current

Vb, VbI, Vb2 bias potential

W reference width

Nl inverter xdO, .. , xd8 inverted internal contr

21 , . . , 2 6 step