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Title:
A/D CONVERSION DEVICE WITH A MULTIPHASE CLOCK GENERATION UNIT BASED ON PHASE INTERPOLATORS
Document Type and Number:
WIPO Patent Application WO/2015/079663
Kind Code:
A1
Abstract:
An A/D conversion device includes a phase-difference clock generation unit configured to use a plurality of phase interpolators to generate multi-phase clock signals, of which phases are shifted with respect to an input clock signal, from the input clock signal and a signal obtained by delaying the input clock signal; and an A/D conversion unit configured to perform A/D conversion on an input analog signal using the multi-phase clock signals generated by the phase-difference clock generation unit.

Inventors:
SAEKI, Takanori (134 Gohdo-cho Hodogaya-ku, Yokohama-sh, Kanagawa 05, 24000, JP)
TAKAHASHI, Tomohiro (1-7-1 Konan, Minato-k, Tokyo 75, 10800, JP)
TAKEDA, Yuiti (1-7-1 Konan, Minato-k, Tokyo 75, 10800, JP)
SUZUKI, Atsushi (1-7-1 Konan, Minato-k, Tokyo 75, 10800, JP)
Application Number:
JP2014/005841
Publication Date:
June 04, 2015
Filing Date:
November 20, 2014
Export Citation:
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Assignee:
SONY CORPORATION (1-7-1, Konan Minato-k, Tokyo 75, 10800, JP)
International Classes:
H03M1/12; H03K5/135; H03K23/00; H03M1/56
Foreign References:
US20110187907A12011-08-04
US20120229319A12012-09-13
Other References:
SAEKI T ET AL: "A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for clock on demand", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 35, no. 11, 1 November 2000 (2000-11-01), pages 1581 - 1590, XP011450354, ISSN: 0018-9200, DOI: 10.1109/4.881203
Attorney, Agent or Firm:
NISHIKAWA, Takashi et al. (Nishishinjukukimuraya Building 9F, 5-25 Nishi-Shinjuku 7-chome, Shinjuku-k, Tokyo 23, 16000, JP)
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