The invention relates to an A/D conversion circuit and method in which folding and interpolation operations are earned out. The invention also relates to a signal processor incoφorating such an A/D conversion circuit.

US-A 4,831 ,379 (attorney's docket PHA 1 , 137) descπbes an 8-bit pπor- art A/D converter of the above-identified type. The pπor-art A/D convener, shown in Fig. 3 of US-A-4, 381 ,379. comprises the following parts: an input amplifier array, a folding array, an inteφolation circuit, a group of fine comparators and a group of coarse comparators, and an encoder. The input amplifier array compnses 64 input amplifiers. Assuming that l is an integer ranging from 0 to 63, each amplifier Ai amplifies the difference between an analog input voltage and a corresponding reference voltage VRi to produce an amplified output voltage VAi.

The folding array electπcally combines groups of amplified output voltages VA0-VA63 to produce 16 VB signals VB0-VB7 and VBN0-VBN7. The VB signals make repetitive transitions between their extreme levels as the analog input voltage vanes across the input range extending from VRO to VR63. The latter is illustrated in Fig. 7 of US- A 4,831 ,379. The inteφolation circuit mteφolates by a factor of 4 between each consecutive pair of VB signals to generate 64 inteφolated signals VD0-VD31 and VDN0-VDN31. The fine comparator group consists of 32 master-slave flip-flops. Each master-slave flip-flop Cq compares complementary signals VDq and VDNq to generate a digital bit Dq Accordingly, 32 bits D0-D31 are obtained which the encoder encodes into five least significant bits MSB-3 - MSB-7 of a digital output code The coarse comparator group consists of three master-slave flip-flops which respectively provide the three most significant bits MSB - MSB-2 of the digital output code in response to three respective pairs of complementary further signals obtained in largely the same manner as the VB signals

The invention seeks to provide an A/D conversion which, with respect to the prior-art. allows more cost-efficient implementations which have a comparable accuracy.

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To this end, a first aspect of the invention provides an A/D conversion circuit as defined in Claim 1. A second aspect of the invention provides an A/D conversion method as defined in Claim 5. A third aspect of the invention provides a signal processor as defined in Claim 6. Advantageous embodiments are defined in the dependent claims. The invention takes the following aspects into consideration. In principle, the complexity of the input part of an A/D converter of the prior-art type may be reduced by increasing the inteφolation factor. For example, if the inteφolation factor in the prior-art A/D converter circuit had been 8 instead of 4, only 32 instead of 64 input stages would have been required. However, in that case 64 instead of 32 pairs of inteφolated signals would have been obtained and, consequently, 64 instead of 32 fine comparators would have been needed. Thus, in the prior-art converter, the choice of the inteφolation factor entails a compromise between the complexity of the input part and that of the output part.

In principle, the complexity of the output part of an A/D converter of the prior-art type may be reduced by increasing the folding factor, that is, the number of transitions provided by the input part which are combined to one signal. For example, if the folding factor in the prior-art A/D converter had been 16 instead of 8, only 4 instead of 8 pairs of complementary signals would have been applied to the inteφolation circuit. In that case, only 16 instead of 32 of inteφolated signals would have been obtained and, consequently, only 16 instead of 32 fine comparators would have been sufficient. However, if the number of signal pairs applied to the inteφolation circuit had been reduced to 4, the inteφolated signals and, consequently, the A/D conversion would have been less accurate. Thus, in the prior-art converter, the choice of the folding factor entails a compromise between the complexity of the output part and the performance of the A/D converter. In any case, at least two signal pairs are needed for an inteφolation, which means that the folding factor in the prior-art A/D converter cannot exceed 32.

In accordance with the invention, at least one of the operations, folding or inteφolation, is carried out more than once in alternation with the other operation, inteφolation or folding, respectively. For such an A/D conversion, the compromises described above and associated with the prior-art A/D converter no longer apply. For example, in accordance with the invention, a first inteφolation operation may be carπed out, followed by a folding operation which is further followed by a second inteφolation operation. If in that case, the inteφolation factor of the first inteφolation is increased by a factor of 2, the overall inteφolation factor will be increased by a factor of 2 and, consequently, only half the number of input stages will be required. If. furthermore, the

folding factor of the folding operation is also increased by a factor of 2, the number of inteφolated signals as a result of the second inteφolation operation will remain the same and, consequently, no additional output circuitry will be required. Thus, in contrast to the prior-art A/D converter, the input part may be simplified by increasing the inteφolation factor, without this automatically requiring a more complex output part.

Another example in accordance with the invention is a first folding operation followed by an inteφolation operation, further followed by a second folding operation. If in that case, the folding factor of the second folding operation is increased by a factor of 2, the overall folding factor will be increased by a factor of 2 and, consequently, only half the number of signals will be supplied to the output part which, as a consequence, may have a simpler construction. The inteφolation accuracy will not be affected, because the folding factor of the first folding operation remains the same and, consequently, the number of signals on which the inteφolation is carried out remains the same. Thus, in contrast to the prior-art converter, the output part may be simplified by increasing the folding factor without this substantially affecting the accuracy.

The invention thus permits simplification of the input part as well as the output part of an A/D converter, thereby achieving cost-efficiency, without adversely affecting accuracy. Besides, the power consumption of the A/D converter is also diminished thereby, which makes it particularly suitable for use in portable devices such as camcorders, cellular telephones and other devices. Furthermore, since the input part requires relatively few transistors, the transistors may be relatively large, which is beneficial to the accuracy of the A/D converter. Accordingly, a relatively accurate A/D converter may be built up with MOS transistors only. This allows the A/D converter to be integrated in a digital signal processor which is commonly implemented with MOS transistors. The invention and its additional features, which may optionally be used to implement the invention to advantage, will be apparent from and elucidated with reference to the examples described hereafter.

In the drawings, Figs, la to ld show, in a block diagram form, four basic examples of an

A/D converter in accordance with the invention;

Fig. le shows, in a block diagram form, a basic example of a signal processor in accordance with the invention;

Fig. 2 shows, in a block diagram form, a first specific example of an A/D

converter in accordance with the invention;

Fig. 3a shows, in a block diagram form, an implementation example of the input pan in the Fig. 2 A/D converter;

Fig. 3b shows transitions provided by the Fig. 3a input part; Fig. 3c shows, in a circuit diagram form, an implementation example of an input amplifier in the Fig. 3a input part;

Fig. 4a shows, in a block diagram form, an implementation example of the intermediate part in the Fig. 2 A/D converter;

Fig. 4b shows, in a circuit diagram form, an implementation example of a folding circuit in the Fig. 4a intermediate part;

Fig. 4c shows, in a circuit diagram form, an implementation example of an inteφolating folding circuit in the Fig. 4a intermediate part;

Figs. 4d and 4e show folding signals in the Fig. 4a intermediate part;

Fig. 5 shows a second specific example of an A/D converter in accordance with the invention;

Fig. 6a shows, in a block diagram form, an implementation example of a folding stage in the Fig. 5 A/D converter;

Fig. 6b shows, in a block diagram form, an implementation example of a folding circuit in the Fig. 6a folding stage; and Figs. 6c to 6d show signals in the Fig. 6b folding circuit.

Identical elements have the same reference signs throughout the drawings.

Figs, la to ld show four basic examples of A/D converters in accordance with the invention. The four basic examples have the following in common. An input part IS provides transitions T1..TX associated with different levels of an analog input signal Vi. An intermediate part IMS carries out folding F and inteφolation I operations on the transitions T1..TX to obtain a set of bit-determining signals X0..XQ. At least one of the operations, folding F or inteφolation I, is carried out more than once in alternation with the other operation, inteφolation I or folding F, respectively. An output part OS provides a digital output signal Do on the basis of the bit-determining signals X0..XQ.

The differences between the four basic examples shown in Figs, la to ld lie within the intermediate part IMS. In Figs, la and lb, a folding operation Fl is carried out first and, subsequently, an inteφolation operation I I is carried out. In Fig. la, a folding operation FN provides the set of bit-determining signals X0..XQ, whereas in Fig. lb, an

inteφolation operation IN provides the set of bit-determining signals X0..XQ. In Figs, lc and ld, an inteφolation operation I I is carπed out first and, subsequently, a folding operation Fl is carπed out. In Fig. lc, an inteφolation operation IN provides the set of bit-determining signals X0..XQ, whereas in Fig. ld, a folding operation FN provides the set of bit-determining signals X0..XQ.

In each of the basic examples shown in Figs, la to Id, there may or may not be additional folding and inteφolation operations which are not visualized as such in these Figures. For example, in an A/D convener according to the Fig. lb example, two folding operations and two inteφolation operations may be carried out. In that case, N=2, that is, the last inteφolation operation is 12 which is earned out subsequent to the folding operation Fl . As another example, in an A/D converter according to the Fig. lb example, three folding operations and three inteφolation operations may be earned out. In that case, N=3, that is, the last inteφolation operation is 13 and a folding operation F3, not shown in Fig. lb. is carπed out after a second teφolation operation 12. In Figs, la to ld, the reference signs which are located directly above a line connecting two functional blocks denote the maximum number of transitions which the left-hand block may apply to the right-hand block. The reference signs which are located directly below a line connecting two functional blocks denote the maximum number of folding signals which the left-hand block may apply to the right-hand block. The functional blocks denoted by F and I carry out folding and inteφolation operations, respectively. An inteφolation operation I increases both the number of transitions and the number of folding signals by its inteφolation factor The first folding operation Fl provides a number of folding signals which is equal to the number of transitions supplied thereto, divided by the folding factor of the first folding stage. Subsequent folding operations, if any, reduce the number of folding signals by their respective folding factors but do not change the number of transitions. Folding factors and inteφolation factors are denoted bythe same reference signs which are used to denote the respective operations

Fig le shows a basic example of a signal processor in accordance with the invention The Fig le signal processor receives an analog signal Sia and provides a digital by processed output signal Sod In the Fig. le signal processor, an A/D converter ADC in accordance with the invention, converts the analog input signal Sia into a digital signal which is processed bv a digital signal processor DSP to provide a digitally processed output signal Sod. The Fig le signal processor may be, for example, an integrated circuit or a receiver.

Fig. 2 shows a first specific example of an 8-bit A/D converter according to the invention. The input part IS of the Fig. 2 A/D converter provides 19 transitions T1..T19 in response to the analog input signal Vi. The intermediate part IMS of the Fig. 2 A/D converter consecutively carries out a first inteφolation operation II by a factor of 2, a folding operation Fl by a factor of 9, and a second inteφolation operation by a factor of 8. Accordingly, 32 bit-determining signals X0-X31 are obtained from which the output part OS derives 5 least significant bits for the 8-bit digital output signal Do. In addition, the Fig. 2 A/D converter comprises circuitry, not shown in Fig. 2, to derive 3 most significant bits. This circuitry may be similar to, for example, the circuitry used in US-A 4,831 ,379 for the same puφose.

Fig. 3a shows an implementation example of the input part IS in the Fig. 2 A/D convener. The Fig. 3a input part comprises an array of 19 input amplifiers A1..A19. Assuming that it is an integer ranging from 0 to 19, each amplifier Ai amplifies the difference between the analog input signal Vin and a reference voltage Vrefi to produce a transition Ti. The more the input signal Vin is amplified, the less any offsets in the intermediate pan IMS affect the accuracy pf the A/D converter. Fig. 3b depicts the relation between the input signal Vin and the transitions T1..T19. The input signal range is denoted by Vrange. Fig. 3c shows details of the input amplifiers. An input amplifier Ai is basically a differential pair which provides a differential output signal Vouti in response to the difference between the input signal Vin and the reference voltage Vrefi.

Fig. 4a shows an implementation example of the intermediate stage IMS in the Fig. 2 A/D converter. The Fig. 4a intermediate part IMS has largely been build up in a modular manner with similar folding circuits, which are denoted by reference signs beginning with FC, and with similar inteφolating folding circuits, which are denoted by reference signs beginning with IFC. The folding circuits FC... carry out a part of the folding operation F l . The inteφolating folding circuits IFC... carry out the first inteφolation operation I I and subsequently carry out the other part of the folding operation Fl . The resistor stπng RSTR carries out the second inteφolation operation 12.

Fig. 4b shows details of an arbitrary folding circuit. The Fig. 4b folding circuit essentially comprises three differential pairs Pl , P2 and P3 whose main current output terminals are interconnected so as to carry out a folding operation by a factor of three. Three differential input signals may be applied, respectively, to the differential pairs Pl , P2 and P3 via differential inputs i l , ι2 and ι3. In response, a differential output signal is provided at output O

Fig. 4c shows details of an arbitrary inteφolating folding circuit. The Fig. 4c inteφolating folding circuit essentially comprises three couples of parallel differential pairs Pla/Plb, P2a/P2b, P3a/P3b. Each couple of parallel differential pairs carries out an inteφolation between a pair of differential signals supplied thereto. Hence, the inteφolation factor is two. The main current output terminals of the three couples of parallel differential pairs Pla/Plb, P2a/P2b, P3a/P3b are interconnected so as to carry out a folding operation on the three inteφolated signals provided by the three pairs of differential pairs. Hence, the folding factor is three. Three pairs of differential input signals may be applied, respectively, to the couples of differential pairs Pla/Plb, P2a P2b, P3a/P3b via pairs of differential inputs ila/ilb, i2a/i2b and i3a/i3b. In response, a differential output signal is provided at output O.

The Fig. 4a intermediate part IMS operates as follows. The folding circuit FC1 11 combines three transitions T2, T8 and T14 to provide a folding signal FS 111. Likewise, the folding circuit FC1 12 combines three transitions T4, TlO and T16 to provide a folding signal FS l 12, and folding circuit FC1 13 combines transitions T6, T12 and T18 to provide a folding signal FS l 13. The folding circuit FC120 combines the three folding signals FS l 1 1 , FS l 12 and FS l 13 to a folding signal FS l 20 which is applied to the resistor string RSTR. The combination of folding circuits FC31 1 , FC312, FC313 and FC320 operates in the same manner as the combination of folding circuits FC1 1 1 , FC1 12, FC113 and FC120 described above, but processes other signals which can readily be understood from Fig. 4a. Fig. 4d shows folding signals FS31 1 , FS312, FS313 and FS320 in the first-mentioned combination. The folding signal FS31 1 comprises transitions Tl , T7 and T13, the folding signal FS312 comprises transitions T3, T9 and T15, and the folding signal FS313 comprises transitions T5, Ti l and T17. The folding signal FS320 comprises all these odd transitions. The inteφolating folding circuit IFC21 1 inteφolates between the transitions T1/T2, T7/T8 and T13/T14, and combines the inteφolated transitions to provide a folding signal FS21 1. Likewise, the inteφolating folding circuit IFC212 inteφolates between the transitions T3/T4, T9/T10 and T15/T16, and combines the inteφolated transitions to provide a folding signal FS212, and inteφolating folding circuit rFC213 inteφolates between the transitions T5/T6, Tl 1/T12 and T17/T18, and combines the inteφolated transitions to provide a folding signal FS213. Fig. 4e illustrates folding signals FS21 1 , FS212, FS213 and FS220. In Fig. 4e, inteφolated transitions which are compnsed in these folding signals, are shown in solid lines. The transitions provided by the input part IS, from which the inteφolated transitions are derived, are shown in broken lines. The folding circuit FC220 combines the three folding signals FS2 I 1 , FS212 and FS213 to a folding

signal FS220 which is applied to the resistor string RSTR. The folding signal FS220 is also shown in Fig. 4e. The combination of inteφolating folding circuits IFC411, IFC412, IFC413 and folding circuit FC420 operates in the same manner as the combination of inteφolating folding circuits IFC211. IFC212, IFC213 and folding circuit FC220 described above, but processes other signals which can readily be understood from Fig. 4a.

The resistor string RSTR, of which only one half is shown in Fig. 4a, is arranged to operate in a differential manner. This is done because the folding signals FS120, FS220, FS320 and FS420, on which the second inteφolation operation 12 is carried out, are differential signals. The resistor string RSTR comprises 64 consecutive nodes N0..N63 between which resistances are coupled. One half of the folding signal FS120 is applied to node NO of the resistor string RSTR, whereas the other, complementary half is applied to node N32. Likewise, one half of the folding signal FS220 is applied to node N8, whereas the other, complementary half is applied to node N40, not shown in Fig. 4a, and so forth. Accordingly, the resistor string provides differential 32 bit-determining signals X0..X31 of which one half X0+ ..X31 + is provided by the half of the resistor string shown in Fig. 4a, whereas the other, complementary half X0-..X31- is provided by the half of the resistor string, not shown in Fig. 4a.

It should be noted that the first inteφolation I I in the Fig. 4a intermediate stage is carried out by active components, where as the second inteφolation is carried out by passive components. In principle, the first inteφolation 11 could also have been carried out by passive components, similarly to the second inteφolation 12. In that case, the inteφolating folding circuits IFC... could have been replaced by folding circuits FC... However, if the first inteφolation had been carried out by passive components, the gain of the input, amplifiers A 1..A 19 would have been affected, which would have resulted in a loss of accuracy.

Fig. 5 shows a second specific example of a 10-bit A/D converter in accordance with the invention. The input part IS of the Fig. 5 A/D converter provides 64 transitions T1..T64 in response to the analog input signal Vi. The intermediate part IMS of the Fig. 5 A/D converter consecutively carries out a first folding operation Fl by a factor of 8, a first inteφolation operation I I by a factor of 4, a second folding operation F2 by a factor of 8, and a second inteφolation by a factor of 4. Accordingly, 16 bit-determining signals X0..X 15 are obtained from which the output part OS derives 4 least significant bits for the 10-bit digital output signal Do. In addition, the output part OS derives 3 most significant bits from coarse bit-determining signals Z, and 3 middle significant bits from

middle bit-determining signals Y. The coarse bit-determining signals Z may be obtained in a manner similar to that in US-A 4,831 ,379. The manner in which middle bit-determining signals Y are obtained will be discussed hereinafter with reference to Fig. 6b.

Fig. 5 also shows some details of the output part OS of the A/D converter. The middle and coarse bit-determining signals Y and Z are applied to a coarse latch arrangement CLA via a synchronisation circuit SYNC. The synchronisation circuit synchronizes the middle and coarse bit-determining signals Y and Z, respectively, with the bit-determining signals X0..X 15. The bit-determining signals X0..X15 are applied to a fine latch arrangement FLA. The fine latch arrangement FLA compnses a latch for each bit- determining signal X0..X 15 supplied thereto. Likewise, the coarse latch arrangements CLA compnse a latch for each individual middle and coarse bit-determining signal supplied thereto. An encoding part ENC encodes the output bits provided by the latches in both latch arrangements CLA and FLA, into the 10-bit digital output signal Do.

The input part IS and the circuitry for carrying out the first folding operation Fl and the first inteφolation operation 12 may be implemented, for example, in a manner known from US-A 4,831 ,379. Accordingly, 32 differential folding signals FS1..FS32 will be obtained, which are comparable with the complementary signal pairs VD0/VDN0..VD31/VDN31 , respectively, in US-A 4,831 ,379.

Fig. 6a shows an implementation example of a folding stage which is particularly suited to carry out the second folding operation F2. The Fig. 6a folding stage compnses four similar folding circuits FCX 1 , FCX2, FCX3 and FCX4. The folding circuit FCX 1 combines the folding signals FS l , FS5, FS9, FS B. FS 17, FS21 , FS25 and FS29, which are applied to inputs ι l ..i8, respectively, to provide a folding signal FX1. The folding circuit FCX2 combines the folding signals FS2, FS6, FS 10, FS 14, FS l 8, FS22, FS26 and FS30, which are applied to inputs ι l ..i8 respectively, to provide a folding signal FSX2, and so on.

Fig. 6b shows details of an arbitrary folding circuit FCX. in the Fig. 6a folding stage. The Fig 6b folding circuit comprises 7 combining circuits CC1..CC7 which effectively operate as analog exclusive ORs and may be implemented, for example, with multipliers. The combining circuit CC l combines folding signals applied at inputs i l and i5, the combining circuit CC2 combines folding signals applied at inputs ι3 and ι7, the combining circuit CC3 combines folding signals applied at inputs ι2 and 16, the combining circuit CC2 combines folding signals applied at inputs ι4 and i8, and so on. The combining circuit CC5 combines output signals ot combining circuits CC l and CC2, and combining

circuit CC6 combines output signals of combining circuits CC3 and CC4. Finally, combining circuit CC7 combines output signals of combining circuits CC5 and CC6 to provide an output folding signal at output O. Figs. 6c to 6f illustrate the operation of folding circuit FCX1. Fig. 6c shows the folding signals FS l , FS5, FS9, FS 13, FS l 7, FS21 , FS25 and FS29 apphed to folding circuit FCX1. The folding signals FS l and FS l 7, which are combined in combining circuit CCl are shown in a fat solid line and a fat broken line, respectively, while the other folding signals are shown in thin solid lines. Fig. 6d shows the output signals of combining circuits CCl , CC2, CC3 and CC4 in folding circuit FSXl . The output signals of combining circuits CCl and CC2 are shown with a thick line and a thick dashed line, respectively, while the other signals are shown with thin lines. Fig. 6e shows the output signals of combining circuits CC5 and CC6 in folding circuit FCX1 , and Fig. 6f shows the signal at output O of folding circuit FCX 1 which is the folding signal FSXl . In Figs. 6d and 6e, an output signal o ^r a combining circuit is denoted by the same reference signs used for that combining circuit.

The Fig 6b folding circuit is particularly suited to provide the previously mentioned middle bit-determining signals. In pnnciple, an output signal from any one of combining circuits CC1..CC4 in any one of the folding circuits FCX1..FCX4 may be applied to the output part as a middle bit-determining signal. Furthermore, an output signal from any one ot combining circuits CC4 or CC6 in any one ot the folding circuits FCX1..FCX4 may be applied to the output part OS as a further middle bit-determining signal. The latter middle bit-determining signal is one rank less significant than the first-mentioned bit-determming signal. Furthermore, the output signal of combining circuit CC7 in any one of the folding circuits FCX1..FCX4 may also be applied as yet another middle bit-determining signals to the output part OS. The latter middle bit-determining signal is two ranks less significant than the first- mentioned bit-determining signal provided by the folding circuit

It should be noted that the above-mentioned examples illustrate rather than limit the invention, and that those skilled in the art will be able to design may alternative embodiments without departing trom the scope of the appended Claims. Any reference signs between parentheses shall not be construed as limiting the Claim concerned. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer