Title:
A/D CONVERTER CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/070029
Kind Code:
A1
Abstract:
The present disclosure pertains to A/D converter circuits (50, 50A) that convert analog information to numeric data, the circuits being provided with a pulse delay circuit (10), and output units (20, 30, 40). A sampling cycle is set such that the relationship between the sampling cycle and a circling cycle satisfies the relational expression of Trdl×n < Ts ≤ Trdl×(n+1). Ts is the sampling cycle, Trdl is the circling cycle in which a pulse signal circles through the pulse delay circuit, and n is an integer of 0 or greater.
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Inventors:
WATANABE TAKAMOTO (JP)
Application Number:
PCT/JP2018/037220
Publication Date:
April 11, 2019
Filing Date:
October 04, 2018
Export Citation:
Assignee:
DENSO CORP (JP)
International Classes:
H03M1/50; H03M1/60
Foreign References:
| JPH08204566A | 1996-08-09 | |||
| JP2011193251A | 2011-09-29 | |||
| JP2007322235A | 2007-12-13 | |||
| JP2014236225A | 2014-12-15 | |||
| EP2330744A1 | 2011-06-08 |
Other References:
WATANABE TAKAMOTO ET AL.: "A 0.0027-mm2 9.5-bit 50-MS/s All-Digital A/D Converter TAD in 65-nm Digital CMOS", 16TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS-(ICECS 2009, 2009, pages 271 - 274, XP031626388, [retrieved on 20100217]
Attorney, Agent or Firm:
NAGOYA INTERNATIONAL PATENT FIRM (JP)
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