Title:
A/D CONVERTER AND SOLID-STATE IMAGING APPARATUS
Document Type and Number:
WIPO Patent Application WO/2011/027768
Kind Code:
A1
Abstract:
In this A/D converter, a ramp generator (19) generates a reference signal which increases or decreases with the passage of time. A comparator (108) starts processing for comparison of an analog signal and the reference signal at a timing related to the input of the analog signal and ends this comparison processing at the timing at which the reference signal satisfies predetermined conditions with respect to the analog signal. A VCO (101) has a plurality of delay units of the same configuration and starts a transition operation at a timing related to the start of the comparison processing. A counter (103) counts the clock from the VCO (101). A lower-order latch (105) latches lower-order logic states at a first timing related to the end of comparison processing, said lower-order logic states being logic states of the plurality of delay units. A higher-order latch (107) latches higher-order logic states at the first timing, said higher-order logic states being logic states of the counter (103). A computation unit (117) computes a digital signal on the basis of the data of the lower-order latch (105) and higher-order latch (107). According to this A/D converter, higher precision A/D conversion becomes possible.
Inventors:
HAGIHARA Yoshio (43-2 Hatagaya 2-chome, Shibuya-k, Tokyo 72, 〒1510072, JP)
Application Number:
JP2010/064891
Publication Date:
March 10, 2011
Filing Date:
September 01, 2010
Export Citation:
Assignee:
OLYMPUS CORPORATION (43-2, Hatagaya 2-chome Shibuya-k, Tokyo 72, 〒1510072, JP)
オリンパス株式会社 (〒72 東京都渋谷区幡ヶ谷２丁目４３番２号 Tokyo, 〒1510072, JP)
オリンパス株式会社 (〒72 東京都渋谷区幡ヶ谷２丁目４３番２号 Tokyo, 〒1510072, JP)
International Classes:
H03M1/56; H04N5/335
Attorney, Agent or Firm:
TANAI Sumio et al. (1-9-2, Marunouchi Chiyoda-k, Tokyo 20, 〒1006620, JP)
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