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Title:
CORRELATED DOUBLE SAMPLING INTEGRATING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2018/148921
Kind Code:
A1
Abstract:
A correlated double sampling integrating circuit, comprising: a sample-and-hold module (101), an energy storage unit (103), and a feedback module (102). The sample-and-hold module (101) is used to perform a sample-and-hold operation on different input signals. The energy storage unit (103) is used to store an electric charge corresponding to the input signal having undergone an sample-and-hold operation to generate a node signal. The feedback module (102) is used to form a negative feedback loop with the energy storage unit (103), and accordingly control consistency between the node signal during an integrating phase and the node signal during a reset phase to prevent an abrupt output transition of the correlated double sampling integrating circuit. In this way, the correlated double sampling integrating circuit eliminates noise caused by 1/f noise of an operational amplifier, a mismatched voltage, etc., and prevents or mitigates an abrupt output change of the correlated double sampling integrating circuit caused by an integrating order increase.

Inventors:
ZHANG MENGWEN (CN)
ZHAN CHANG (CN)
Application Number:
PCT/CN2017/073860
Publication Date:
August 23, 2018
Filing Date:
February 17, 2017
Export Citation:
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Assignee:
SHENZHEN GOODIX TECH CO LTD (CN)
International Classes:
H03M1/54; H03F1/30
Foreign References:
CN104796638A2015-07-22
CN102523394A2012-06-27
CN1835124A2006-09-20
CN1485898A2004-03-31
CN103023499A2013-04-03
US20100194447A12010-08-05
US20150263750A12015-09-17
Other References:
See also references of EP 3422581A4
Attorney, Agent or Firm:
BEIJING HEADSTAY INTELLECTUAL PROPERTY INC. (CN)
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