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Title:
COUNTER CIRCUIT AND PROTECTION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2010/061814
Kind Code:
A1
Abstract:
Provided is a counter circuit having a simple circuit configuration which can switch the delay time from one to another. The counter circuit includes flip-flops of a plurality of stages which are longitudinally connected.  A clock from an oscillator is supplied as an input signal to the flip-flops of the first stage.  A Q output of the preceding stage is supplied as an input signal to the flip-flops of the second stages and after.  A mode signal is supplied to all or some of the flip-flops of the plurality of stages.  When the mode signal indicates a normal delay mode, each of the flip-flops of the plurality of stages outputs the supplied input signal as a Q output after subjecting the input signal to 1/2 division.  When the mode signal indicates a delay reduction mode, the flip-flop of each of the stages which have received the mode signal outputs the supplied input signal as a Q output after passing the input signal directly in a through mode.

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Inventors:
TAKEDA, Takashi (2-11-2, Tsurumaki, Tama-Sh, Tokyo 67, 〒2068567, JP)
Application Number:
JP2009/069791
Publication Date:
June 03, 2010
Filing Date:
November 24, 2009
Export Citation:
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Assignee:
MITSUMI ELECTRIC CO., LTD. (2-11-2, Tsurumaki Tama-Sh, Tokyo 67, 〒2068567, JP)
ミツミ電機株式会社 (〒67 東京都多摩市鶴牧2丁目11番地2 Tokyo, 〒2068567, JP)
International Classes:
H03K23/58; H03K23/00
Foreign References:
JPH0795047A
JPS6424504A
JPH03262317A
JP2002186173A
Attorney, Agent or Firm:
ITOH, Tadahiko (32nd Floor, Yebisu Garden Place Tower 20-3, Ebisu 4-Chome, Shibuya-K, Tokyo 32, 〒1506032, JP)
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