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Title:
UP/DOWN COUNTER CONTROL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/1983/003502
Kind Code:
A1
Abstract:
The design of a system is simplified by making control lines from a microprocessor as small as possible when the frequency-dividing ratio of a programmable divider of a phase-locked loop is controlled by an up/down counter. This circuit has timing control means supplied with a latch signal, data, and a clock signal; data storage means; and an up/down counter. In an up/down counter control circuit, a first level (0 or 1) of the latch signal is detected in a data loading mode based on the control of the timing control means, the data is loaded into the data storage means in synchronism with the clock signal, a second level (1 or 0) of the latch signal is detected in the up/down mode, and the content of the counter is altered in response to the level of the data synchronized with the clock signal.

Inventors:
YAMADA TAKAAKI (JP)
Application Number:
PCT/JP1983/000093
Publication Date:
October 13, 1983
Filing Date:
March 28, 1983
Export Citation:
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Assignee:
SONY CORP (JP)
International Classes:
H03J5/02; H03J7/28; H03L7/18; H03K21/02; H03K23/66; H03K23/86; H03L7/183; H04B1/26; (IPC1-7): H03K21/36; H03L7/18
Foreign References:
JPS54807A1979-01-06
JPS54109309A1979-08-27
Other References:
See also references of EP 0105378A4
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