TECHNOLOGY

[0001] Embodiments of the present disclosure generally relate to a communication system, and more specifically, to methods and devices for data processing at a transmitting device and a receiving device in a communication system.

BACKGROUND

[0002] Polar code has been proposed for an enhanced mobile broadband (eMBB) control channel. The polar code is also a candidate for channel coding of a machine type communication (mMTC). As compared to other channel coding schemes, polar coding has advantages of low complexity and capacity achieving, for example. Therefore, for example in a fifth generation (5G) mobile communication system, the polar coding will play an important role.

[0003] For polar code, frequently used decoding scheme includes a list-based scheme or a cyclic redundant check (CRC)-aided list scheme. A list characterizes decoding paths. That is, for the scheme based on the list having a size of L, L branches are to be retained in decoding. In order to obtain the satisfactory performance, a larger list size is required, for example, L = 32 (although the base line is 8, the use of the larger list size might be an implementation issue). However, the complexity of the polar code may be modeled as a function of L, namely L*log ₂ N, where N represents the size of an encoded unpunctured codeword and L represents the list size. It can be seen from the modeling of the complexity that the complexity of the polar code increases in proportion to the list size. Moreover, storage spaces consumed in the decoding may also be determined by the list size.

[0004] Therefore, although the larger list size can provide the better decoding performance, such as a lower block error rate (BLER), more storage spaces are consumed and the decoding complexity is increased, resulting the higher power consumption and longer decoding latency. This is a disadvantage for certain receiving devices, especially for an mMTC terminal. For downlink control channel, blind decoding is used, and thus the decoding latency and complexity become issues. SUMMARY [0005] A brief summary of various embodiments will be given below to provide basic understanding on some aspects of the various embodiments. It should be noted that this Summary is not intended to identify essential points of key elements or describe the scope of the various embodiments. The sole purpose is to present some concepts in a simplified manner to acts as a preamble of the following detailed description.

[0006] In a first aspect of the present disclosure, there is provided a method of data processing in a communication system. The method comprises: dividing a plurality of information bits to be encoded into at least a first segment and a second segment; encoding the first segment with a first check code to generate a first encoded sequence; encoding the second segment with a second check code to generate a second encoded sequence; and cascading the first and second encoded sequences to form a cascaded sequence; and performing polar encoding on the cascaded sequence.

[0007] In some embodiments, a first ratio between a length of the second segment and a length of the first segment is greater than or equal to 1, and a second ratio between a length of the first check code and a length of the second check code is equal to the first ratio.

[0008] In some embodiments, the ratio between the length of the second segment and the length of the first segment is greater than 1, and the length of the first check code is equal to the length of the second check code.

[0009] In some embodiments, cascading the first and second encoded sequences comprises: generating, by changing a bit order of the first encoded sequence, a third encoded sequence in which a check bit of the first check code are adjacent to information bits associated with the check bits of the first check code; generating, by changing a bit order of the second encoded sequence, a fourth encoded sequence in which a check bit of the second check code are adjacent to information bits associated with the check bits of the second check code; and cascading the third and fourth encoded sequences to form the cascaded sequence.

[0010] In some embodiments, the check bit of at least one of the first check code and the second check code is immediately adjacent to information bit associated with the check bit of the at least one check code.

[0011] In some embodiments, frozen bits are distributed between a check bit of at least one of the first check code and the second check code and the information bit associated with the check bit of the at least one check code.

[0012] In some embodiments, cascading the first and second encoded sequences comprises: generating, by changing a bit order of the first encoded sequence, a third encoded sequence in which the first check code is adjacent to the information bits associated with the first check code; and cascading the third and second encoded sequences to form the cascaded sequence.

[0013] In some embodiments, in the third encoded sequence, the check bit of the first check code are immediately adjacent to the information bits associated with the check bit of the first check code.

[0014] In some embodiments, in the third encoded sequence, frozen bits are distributed between the check bit of the first check code and the information bits associated with the check bit of the first check code.

[0015] In a second aspect of the present disclosure, there is provided a method of data processing in a communication system. The method comprises: performing polar decoding on received polar-encoded data to obtain output bits; obtaining a first bit sequence and a second bit sequence by bit splitting of the output bits, the first and second bit sequences being generated by encoding a first segment and a second segment of a plurality of information bits using a first check code and a second check code, respectively; obtaining the first and second segments by check decoding of the first and second bit sequences; and cascading the first and second segments to obtain the plurality of information bits.

[0016] In a third aspect of the present disclosure, there is provided a communication device. The communication device comprises: a processor and a memory storing instructions, the instructions, when executed by the processor, causing the communication device to: divide a plurality of information bits to be encoded into at least a first segment and a second segment; encode the first segment with a first check code to generate a first encoded sequence; encode the second segment with a second check code to generate a second encoded sequence; and cascade the first and second encoded sequences to form a cascaded sequence; and perform polar encoding on the cascaded sequence.

[0017] In a fourth aspect of the present disclosure, there is provided a communication device. The communication device comprises: a processor and a memory storing instructions, the instructions, when executed by the processor, causing the communication device to: perform polar decoding on received polar-encoded data to obtain output bits; obtain a first bit sequence and a second bit sequence by bit splitting of the output bits, the first and second bit sequences being generated by encoding a first segment and a second segment of a plurality of information bits using a first check code and a second check code, respectively; obtain the first and second segments by check decoding of the first and second bit sequences; and cascade the first and second segments to obtain the plurality of information bits.

[0018] Through the description below, it is to be understood that, in accordance with embodiments of the present disclosure, the communication device can obtain the desired decoding performance with the lower complexity, and provide a better error detection capability in the meantime.

[0019] It is to be understood that contents as described in the SUMMARY portion are not intended to identify key or important features of embodiments of the present disclosure or used to limit the scope of the present disclosure. Other features of the present disclosure will become easily comprehensible through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Through the following detailed description with reference to the accompanying drawings, the above and other objectives, features, and advantages of the embodiments of the present disclosure will become more apparent. In the drawings, the same or similar reference signs refer to the same or similar elements, in which:

[0021] FIG. 1A illustrates a schematic diagram of an example communication system in which methods in accordance with embodiments of the present disclosure can be implemented;

[0022] FIG. IB illustrates a simplified diagram of the processing implemented at a transmitting device and a receiving device in communications in accordance with embodiments of the present disclosure;

[0023] FIG. 2 illustrates a flowchart of a method implemented at a communication device acting as a transmitting device in accordance with embodiments of the present disclosure;

[0024] FIG. 3 illustrates an example of a check part of a CRC generator matrix in accordance with embodiments of the present disclosure;

[0025] FIG. 4 illustrates an example of a transposed check part of the CRC generator matrix in accordance with embodiments of the present disclosure;

[0026] FIG. 5 illustrates a flowchart of a method implemented at a communication device acting as a receiving device in accordance with embodiments of the present disclosure; [0027] FIG. 6 illustrates a block diagram of an apparatus implemented at a communication device acting as a transmitting device in accordance with embodiments of the present disclosure;

[0028] FIG. 7 illustrates a block diagram of an apparatus implemented at a communication device acting as a receiving device in accordance with embodiments of the present disclosure;

[0029] FIG. 8 illustrates a block diagram of a communication device in accordance with embodiments of the present disclosure;

[0030] FIG. 9 illustrates an evaluation result of a block error rate in accordance with embodiments of the present disclosure;

[0031] FIG. 10 illustrates a schematic diagram of percentage of early termination occurrences in accordance with embodiments of the present disclosure;

[0032] FIG. 11 illustrates a schematic diagram of decoding saving due to the early termination in accordance with embodiments of the present disclosure;

[0033] Throughout the drawings, the same or similar reference numerals represent the same or similar element. DETAILED DESCRIPTION

[0034] In the following, details are described for the purpose of illustration. However, those skilled in the art would realize that the present disclosure can be implemented without these specific details. Therefore, the present invention is not intended to be limited to the embodiments as illustrated, but should be endowed with the broadest scope conforming to the principles and features as described herein.

[0035] It is to be understood that the terms such as "first" and "second" are only used to differentiate one element from another. In fact, a first element may also be called a second element, or vice versa. Besides, it is to be understood that "include" and "comprise" are only used to demonstrate the presence of a feature, an element, a function or a component as described herein, without excluding the presence of one or more other features, elements, functions or components.

[0036] For ease of explanation, some embodiments of the present disclosure will be introduced herein in the context of wireless communications, such as cellular communications, and the terms in Long Term Evolution/Long Term Evolution-Advanced (LTE/LTE-A) specified by 3GPP or in 5G are employed. However, those skilled in the art would appreciate that embodiments of the present invention are not limited to wireless communication systems conforming to wireless communication protocols formulated by 3GPP, but may be applicable to any communication system with similar issues, such as WLAN, a wired communication system, or other communication systems to be developed in the future.

[0037] Likewise, the terminal device in the present disclosure may be a user equipment (UE), or any terminal having a wired or wireless communication function, including, but not limited to, a mobile phone, a computer, a personal digital assistant, a game machine, a wearable device, an on-vehicle communication device, a Machine Type Communication (MTC) device, a Device-to-Device (D2D) communication device, a sensor and the like. The term "a terminal device" can be used interchangeably with a UE, a mobile station, a subscriber station, a mobile terminal, a user terminal, or a wireless device. In addition, the network device may be a network node, such as a node B (Node B or NB), a base transceiver station (BTS), a base station (BS), or a base station system (BSS), a relay, remote radio head (RRH), an access node (AN), an access point (AP), and on the like.

[0038] FIG. 1A is a schematic diagram of an example wireless communication system 100 in which methods in accordance with embodiments of the present disclosure can be implemented. The wireless communication system 100 may include one or more network devices 101. For example, in the wireless communication system 100, the network device 101 may be implemented by a base station, such as an evolved node B (eNodeB or eNB). It is to be understood that the network device 101 may be implementedin other manners, such as a node B, a basic transceiver station (BTS), a base station (BS), or a base station sub-system (BSS), a relay and on the like. The network device 101 provides a wireless connection to a plurality of terminal devices 111-112 within the coverage thereof. The terminal devices 111 and 112 may communicate with the network device via a wireless transmission channel 131 or 132, and/or may communicate with each other via a wireless transmission channel 133.

[0039] FIG. IB illustrates a simplified diagram of processing implemented at a transmitting device 120 and a receiving device 130 in communications. The network device 101 or the terminal devices 111 and 112 in FIG. 1A may act as the transmitting device 120 and/or the receiving device 130 shown in FIG. IB.

[0040] As shown in FIG. IB, in order to ensure reliable transmission of data (including control signaling), the transmitting device performs channel encoding (140) on the data to be transmitted to insert redundancy, thereby mitigating distortion probably induced in the transmission channels (for example, 131, 132, and 133 in FIG. 1A). Optionally, the channel-encoded data may be further channel-interleaved (not shown) and/or modulated (150) before being transmitted. At the receiving device, a process reverse to that of the transmitting device is performed. That is, the received signal is demodulated (160), de- interleaved (not shown) and decoded (170) to recover the transmitted data. In some embodiments, other or different processing may be involved at the transmitting device, and the receiving device may perform a reverse operation accordingly.

[0041] In embodiments of the present disclosure, the polar code is used in the channel encoding processing 140 in FIG. IB. For the polar code with a code length N (for example, N = 2 ⁿ , n is a natural number), assuming that its code rate is K/N, then K = [1, N] information bits can be transmitted. Except for the K information bits, N-K bits are redundant bits which are assigned to a fixed value (for example, 0 or any other appropriate values) and which are referred to as frozen bits. The value of the frozen bits is considered to be known, and therefore the frozen bits are represented by the known value or a probability corresponding to the known value, such as a specific value of a log likelihood ratio (LLR)), in decoding.

[0042] The polar code implements channel polarization by two steps of channel combination and channel splitting. It should be note that such a channel is a coding channel, namely a channel the bits are inputted into and outputted from in the encoding, rather than the transmission channels 131-133 in FIG. 1A. The coding channel for each encoded bit to pass through may also be referred to as a sub-channel. Different split sub-channels have different channel transfer probabilities. Due to the presence of a channel transfer characteristics, for the polar code, if a certain bit decoded previously is error, it may affect the decoding of the following bits, thus resulting in error spread. [0043] At the modulation processing 150 in FIG. IB, any modulation technique known or to be developed in the future may be used, such as BPSK, QPSK, 64QAM. The embodiments of the present disclosure are not limited to any specific modulating scheme. It is to be understood that in the demodulation 160 of the receiving device 130, the de-modulating schemes will be varied depending on the modulating schemes. As those skilled in the art would appreciate, the receiving device may use, alternatively or in addition, other processing than de-modulation, based on varied processing used by the transmitting device.

[0044] In some embodiments of the present disclosure, the decoding 170 as shown in FIG. IB may, for example but not limited to, use a list-based decoding approach, or an approach based on sequence cancellation (SC), or any decoding approach known or to be developed in the future.

[0045] One of important characteristics of the polar code is that successive decoding can be used. Therefore, if the decoding may be terminated as early as possible, the decoding complexity may be reduced. However, in the conventional polar decoding schemes, the check bits are attached subsequent to all the information bits and thus. Accordingly, only when all of the information bits and check bits are decoded, a cyclic redundant check (CRC) may be performed, and hence it is impossible to achieve the early termination of the decoding.

[0046] Embodiments of the present disclosure provide a scheme for improving encoding and decoding. Now, example methods in accordance with various embodiments of the present disclosure will be described with reference to FIGS. 2-4. For the purpose of discussion, the description with respect to FIGS. 2-4 will be given in the context of FIG. 1A. [0047] FIG. 2 is a flowchart of a method 200 in accordance with various embodiments of the present disclosure. The method 200 is implemented at a communication device acting as the transmitting device in the communication network 100. For example, the communication device may be the terminal devices 111, 112, or the network device 101 in FIG. 1A. For the purpose of discussion, the method 200 will be described with reference to the network device 101 in FIG. 1A. It is to be understood that the method 200 may also include additional steps not shown and/or may skip over the shown steps, and the scope of the present disclosure will not be limited in this regard.

[0048] As shown in FIG. 2, at 210, the network device 101 divides a plurality of information bits to be encoded into at least a first segment and a second segment. In other words, the plurality of information bits to be encoded are divided into at least two segments, namely, s , ¾, Ss ₇ where Si represents the 1 ^th segment of the information bits, i £ [l, s], s is an integer greater than or equal to 2. In some embodiments, the lengths of s segments have the following relation: s _i+l = \a■ s _i ] , where a is a real number greater than or equal to 1, and · represents rounding down. [0049] For the purpose of illustration, an example will be described below where the plurality of information bits are divided into two segments, namely, the first segment and the second segment. However, it is to be understood that the plurality of information bits may also be divided into more than two segments, and the scope of the present disclosure will not be limited in this regard.

[0050] At 220, the network device 101 encodes the first segment with the first check code to generate a first encoded sequence. At 230, the network device 101 encodes the second segment with the second check code to generate a second encoded sequence.

[0051] In various embodiments of the present disclosure, terms "check code" and "check bit sequence" may be used interchangeably. In some embodiments, the check code may include linear block codes, such as a cyclic redundant check (CRC) code, a BCH code, a Hamming code, or a Gray code. For the purpose of illustration, the CRC code will be taken as an example of the check code in the following depiction. However, it is to be understood that other types of check codes may also be applicable, such as a parity check code, the check code generated based on a Hash function and on the like. The scope of the present disclosure will not be limited in this regard.

[0052] In the conventional check encoding, a check bit sequence is used to encode the entirety of the plurality of information bits. However, in various embodiments of the present disclosure, as the plurality of information bits to be encoded are divided into at least two segments, the check bit sequence is divided into a plurality of segments, accordingly. In the embodiment in which the plurality of information bits are divided into s segments, the check bit sequence is also divided into s segments accordingly, namely, c _\ , c ₂ , c _s. In some embodiments, the lengths of the s segments of the check bit sequence have the following relation: c _i+1 = a - c _; . In some other embodiments, the lengths of the s segments of the check bit sequence are the same. Therefore, the same check encoder may be used to encode the s segments of the information bits, thereby simplifying the implementation.

[0053] It is to be understood that in order to implement the implicit transmission of UE identifier, the UE identifier is generally used to scramble the check bit sequence. In this regard, in embodiments of present disclosure, in order to scramble the first check code and the second check code with the UE identifier, the network device 101 also divides the UE identifier, accordingly. For example, in a case where the check bit sequence with a length of 16 bits is divided into a first check code with a length of 8 bits and a second check code with a length of 8 bits, the UE identifier with a length of 16 bits is also divided into a first portion with a length of 8 bits and a second portion with a length of 8 bits. Thereafter, the first portion of the UE identifier may be used to scramble the first check code, and the second portion of the UE identifier may be used to scramble the second check code,

[0054] Still with reference to FIG. 2, at 240, the network device 101 cascades the first encoded sequence and the second encoded sequence to form a cascaded sequence. At 250, the network device 101 performs polar encoding on the cascaded sequence. [0055] In various embodiments of the present disclosure, the information bits to be encoded are divided into a plurality of segments, and individual segments are separately check-encoded. Subsequently, the check-encoded segments are cascaded, and then further polar-encoded. When the polar decoding is performed at the receiving device, upon on the decoding of the check-encoded segment, the segment may be checked with the check code in the segment. Compared with the conventional approach of attaching the check bits after all the information bits, since the information bits in each segment become less, and the number of check bits for each segment is reduced, errors in the segment may be earlier detected so as to terminate the decoding.

[0056] In order to enable the receiving device to further earlier detect errors in the segments to terminate the decoding, in some embodiments, the network device 101 may change the bit order of at least one of the first encoded sequence and the second encoded sequence so that at least one of the first check code and the second check code is adjacent to the associated information bit in the sequence having the order-changed bits.

[0057] In some embodiments, the network device 101 may generate a third encoded sequence by changing the bit order of the first encoded sequence. In the third encoded sequence, the first check code is adjacent to the information bits associated with the first check code. The network device 101 may further form the cascaded sequence by cascading the third encoded sequence and the second encoded sequence.

[0058] In some other embodiments, the network device 101 may generate, by changing the bit order of the first encoded sequence, the third encoded sequence in which the first check code is adjacent to the information bits associated with the first check code. The network device 101 may further generate a fourth encoded sequence by changing: the bit order of the second encoded sequence. In the fourth encoded sequence, the second check code is adjacent to the information bits associated with the second check code. Furthermore, the network device 101 may form the cascaded sequence by cascading the third encoded sequence and the fourth encoded sequence.

[0059] In some embodiments, the network device 101 may change the bit order of the first encoded sequence by changing the check part of the CRC generator matrix corresponding to the first check code. Similarly, the network device 101 may change the bit order of the second encoded sequence by changing the check part of the CRC generator matrix corresponding to the second check code.

[0060] Specifically, the CRC code is a linear block code and the corresponding CRC generator matrix may be obtained based on the CRC generator polynomial. The CRC generator matrix may have the following form:

where G represents the CRC generator matrix. The left half of the CRC generator matrix G is a unit matrix and the right half is the check part. The check part of the CRC generator matrix G includes k columns, corresponding to k CRC bits respectively, where k is a natural number.

[0061] The network device 101 may swap the rows and/or columns of the check part of the CRC generator matrix G so that the check part of the CRC generator matrix G is changed into an upper triangular matrix as below:

where G' represents the changed check part of the CRC generator matrix G.

[0062] For the first column of G', g _Q ^' _fi = g _l ^' _fi =...= g _d ^' _Q)fi =1 , 5 _d (o)+i,o = 5 _d( o)+2 _, o = ^■ " = 5(i(n-i),o = 0· F° ^r column i, d(i) represents the maximum of the serial number (namely, index) of the rows with the value of 1 after the row/column swapping. In an embodiment, the row/column swapping is based on minimization of the value of d(i) in sequence. For a column with an index greater than or equal to 2, ⁼ 9d(i-'i) ₊₂ ,i = ^■■■ = ga = 1 _> where d(i)>d(i-l)+l, and d(i) represents the maximum number of rows for a particular column with a value of 1.

[0063] Thus, the CRC bits may be calculated in the following equation:

Ci = mod(∑*V> tf _Jil ,2) (3) where mod represents the modular operation. [0064] Transposing of the check part of the CRC generator matrix G will be described below with reference to specific examples of FIGS. 3 and 4.

[0065] FIG. 3 illustrates an example of the check part 300 of the CRC generator matrix G in accordance with embodiments of the present disclosure. In the example shown in FIG. 3, it is assumed that the length of the information bits to be encoded is 16, and the length of the CRC bit sequence is 8. Therefore, the check part 300 contains 16 rows (namely, rows 311 to 326) and 8 columns (namely, columns 331-338).

[0066] When the check part 300 is transposes, the columns are first swapped, and then the rows are swapped. For the swapping of the columns, the column with the smallest number of element 1 (namely, column 336) is selected from the columns 331 to 338, and the column 336 is swapped with the first column 331. Then, the row swapping is performed for the column 336 so that all the elements 0 in the column 336 are swapped below the elements 1. Subsequently, the similar operation is performed to other columns than the column 336. It should be noted that when the row swapping is performed for the column i, if the column i-1 contains d(i-l) elements 1, the row swapping is only performed for the row d(i) of the column i, where i>2.

[0067] FIG. 4 illustrates a check part 400 obtained upon the above transposing of the check part 300 in accordance with embodiments of the present disclosure. As shown in FIG. 4, the check part 400 is similar to the upper triangular matrix. It shall be noted that for the purpose of discussion on the transposing of the check part 300, before the column and row swapping of the check part 300, each row of the check part 300 is multiplied with the index of the row. For example, each row of the check part 300 is multiplied with 1, 2,..., 16.

[0068] As shown in FIG. 4, the check part 400 obtained by the above transposing of the check part 300 contains 16 rows (namely, rows 411 to 426) and 8 columns (columns 431 to 438). [0069] As can be seen from the column 431 of FIG. 4, the first CRC bit cl in the CRC bit sequence is associated with 1 ^st , 15 ^th , 3 ^rd , 11 ^th , 8 ^th and 7 ^th information bits among the plurality of information bits to be encoded. Therefore, it is possible to arrange the first CRC bit cl to be immediately adjacent to any of the 1 ^st , 15 ^th , 3 ^rd , 11 ^th , 8 ^th and 7 ^th information bits. For example, the first CRC bit cl may be arranged subsequent to the 7 ^th information bit in the form of [l 15 3 11 8 7 cl] or the first CRC bit cl may be arranged prior to the first information bit in the form of [cl 1 15 3 11 8 7], or the first CRC information bit may be distributed between the associated information bits (for example, in the form of [l 15 cl 3 11 8 7]).

[0070] Thus, when the polar decoding is performed at the receiving device, after the 1 ^st , 15 ^th , 3 ^rd , 11 ^th , 8 ^th and 7 ^th information bits are decoded, the first CRC bit cl may be used to check these information bits, thereby achieving the early termination of the decoding process to improve the decoding performance. Details about the early termination of the decoding process will be described in the following paragraphs.

[0071] Alternatively, a frozen bit (namely, a bit assigned to a fixed value) may be arranged between the first CRC bit cl and its associated information bits.

[0072] It is to be understood that although the acts of the method 200 are depicted in a particular order, this should not be interpreted as requiring that these acts are completed in the particularly shown order or in a sequential order. For example, the acts 220 and 230 may be executed in parallel or the act 230 may be executed prior to the act 220. [0073] FIG. 5 is a flowchart of a method 500 in accordance with embodiments of the present disclosure. The method 500 is implemented at a communication device acting as the receiving device in the communication network 100. For example, the communication device is the terminal device 111, 112 or network device 101 as shown in FIG. 1. For the purpose of discussion, the method 500 will be described below with reference to the terminal device 111 shown in FIG. 1. It is to be understood that the method 500 may also include additional steps not shown and/or may skip over the shown steps, and the scope of the present disclosure will not be limited in this regard.

[0074] As shown in FIG. 5, at 510, the terminal device 111 performs the polar decoding on the received polar encoded data to obtain the output bits. It is to be understood that "output bits" mentioned herein refer to the output bits of the polar decoder of the terminal device 111. An example implementation of the decoding operation will be described in detail in the following paragraphs. [0075] At 520, the terminal device 111 obtains the first bit sequence and the second bit sequence by bit splitting of the output bits. The first bit sequence and the second bit sequence are generated respectively by encoding the first segment and the second segment of the plurality of information bits using the first check code and the second check code. It is to be understood that the operations at block 520 correspond to the operations at block 240 depicted with reference to FIG. 2, and further detailed description will be omitted herein.

[0076] At 530, the terminal device 111 obtains the first segment and the second segment of the information bits by check decoding of the first bit sequence and the second bit sequence. It is to be understood that the operations at block 530 correspond to the operations at block 230 depicted with reference to FIG. 2, and further detailed description will be omitted herein.

[0077] At 540, the terminal device 111 cascades the first segment and the second segment to obtain the plurality of information bits.

[0078] In some embodiments, the block 510 is implemented with a polar decoder. In these embodiments, the maximum number of remaining decoding paths for each decoding by the polar decoder, such as the list size L, may be configured in advance. In the polar decoding, the terminal device 111 assumes a non-frozen bit to be decoded as 0 or 1 and adds it after all the existing decoding paths, thereby forming 2*L temporary decoding paths.

[0079] In some embodiments, the terminal device 111 may determine the log likelihood ratios (LLR) of the 2*L decoding paths and sort the LLRs of the 2*L decoding paths in a descending order so as to remove L decoding paths with low LLRs from the 2*L decoding paths while retaining L decoding paths with high LLRs.

[0080] In some embodiments, after the first check code and the information bits associated with the first check code are decoded, a first check code may be used to check these information bits for the L remaining decoding paths. If all the checks for the L remaining decoding paths fail, the terminal device 111 then terminates the polar decoding of the information bits. If a part of or all of the path checks of the L remaining decoding paths pass, the terminal device 111 then continues to decode the next bit.

[0081] For example, in the embodiment of arranging the first CRC bit cl subsequent to the 7 ^th information bit in the form of [1 15 3 11 8 7 cl], after the 1 ^st , 15 ^th , 3 ^rd , 11 ^th , 8 ^th and 7 ^th information bits and the first CRC bit cl are decoded, the terminal device 111 may use the first CRC bit cl to check the 1 ^st , 15 ^th , 3 ^rd , 11 ^th , 8 ^th and 7 ^th information bits. If all the checks for the L remaining decoding paths fail, the terminal device 111 may terminate the polar decoding at the 7 ^th information bit, thereby reducing iterative LLR calculation in the polar decoder, hence reducing the decoding complexity and improving decoding performance.

[0082] In addition, in the case of scrambling the check codes with an identifier of the terminal device 111, the terminal device 111 may first descramble the polar-decoded check codes and then check the associated information bits for the L remaining decoding paths. For example, in the case when the first CRC bit cl is scrambled as cl', the terminal device 111 may descramble cl' as cl and check the 1 ^st , 15 ^th , 3 ^rd , 11 ^th , 8 ^th and 7 ^th information bits with cl.

[0083] FIG. 6 is a block diagram of an apparatus 600 according to the some embodiments of the present disclosure. The apparatus 600 may be implemented at a communication device acting as the transmitting device, for example at the terminal device 111 or 112 side or at the network device 101 as shown in FIG. 1. The apparatus 600 may be a software module based system, or may be a hardware component such as a transmitter or the like. Especially, in some embodiments, the apparatus 600 may be considered as an example implementation of the transmitting device itself.

[0084] As shown in FIG. 6, the apparatus 600 may include: a segmenting unit 610 configured to divide a plurality of information bits to be encoded into at least a first segment and a second segment; a first check code encoding unit 620 configured to encode the first segment with a first check code to generate a first encoded sequence; a second check code encoding unit 630 configured to encode the second segment with a second check code to generate a second encoded sequence; a cascading unit 640 configured to cascade the first encoded sequence and the second encoded sequence to form a cascaded sequence; and a polar encoding unit 650 configured to perform polar encoding on the cascaded sequence.

[0085] In some embodiments, the first ratio between the length of the second segment and the length of the first segment is greater than or equal to 1, and the second ratio between the length of the first check code and the length of the second check code is equal to the first ratio.

[0086] In some embodiments, the ratio between the length of the second segment and the length of the first segment is greater than 1, and the length of the first check code is equal to the length of the second check code.

[0087] In some embodiments, apparatus 600 further includes a first bit reordering unit configured to: generate, by changing the bit order of the first encoded sequence, a third encoded sequence in which the first check code is adjacent to the information bits associated with the first check code; generate, by changing the bit order of the second encoded sequence, a fourth encoded sequence in which the second check code is adjacent to the information bits associated with the second check code. The cascading unit 640 is further configured to cascade the third encoded sequence and the fourth encoded sequence to form the cascaded sequence.

[0088] In some embodiments, at least one of the first check code and the second check code is immediately adjacent to the information bits associated with the at least one of the first and second check codes. [0089] In some embodiments, frozen bits are distributed between at least one of the first check code and the second check code and the information bits associated with the at least one of the first and second check codes.

[0090] In some embodiments, the apparatus 600 further includes a second bit reordering unit configured to generate, by changing the bit order of the first encoded sequence, a third encoded sequence in which the first check code is adjacent to the information bits associated with the first check code. The cascading unit 640 is further configured to cascade the third encoded sequence and the second encoded sequence to form the cascaded sequence.

[0091] In some embodiments, in the third encoded sequence, the first check code is immediately adjacent to the information bits associated with the first check code. [0092] In some embodiments, in the third encoded sequence, frozen bits are distributed between the first check code and the information bits associated with the first check code.

[0093] FIG. 7 is a block diagram illustrating an apparatus 700 in accordance with certain embodiments of the present disclosure. The apparatus 700 may be implemented at a communication device acting as a receiving device, for example at the terminal device 111 or 112 side or the network device 101 as shown in FIG. 1. The apparatus 700 may be a system based on software modules, or may be a hardware assembly such as a receiver or the like. Particularly, in some embodiments, the apparatus 700 may be considered as an example implementation of the receiving device itself.

[0094] As shown in FIG. 7, the apparatus 700 may include: a polar decoding unit 710 configured to perform polar decode on received polar encoded data to obtain output bits; a bit splitting unit 720 configured to obtain a first bit sequence and a second bit sequence by bit splitting of the the output bits, the first bit sequence and the second bit sequence being generated by encoding the first segment and the second segment of a plurality of information bits using the first check code and the second check code, respectively; a check decoder 730 configured to obtain the first segment and the second segment by check decoding of the first bit sequence and the second bit sequence; and a cascading unit 740 configured to cascade the first segment and the second segment to obtain the plurality of information bits.

[0095] In some embodiments, the first ratio between the length of the second segment and the length of the first segment is greater than or equal to 1 ; and the second ratio between the length of the first check code and the length of the second check code is equal to the first ratio. [0096] In some embodiments, the ratio between the length of the second segment and the length of the first segment is greater than 1 ; and the length of the first check code is equal to the length of the second check code.

[0097] In some embodiments, the first check code is adjacent to the first information bits associated with the first check code in the first bit sequence, and the second check code is adjacent to the second information bits associated with the second check code in the second bit sequence.

[0098] In some embodiments, the apparatus 700 further includes an inverse bit reordering unit configured to: obtain a third bit sequence by changing the bit order of the first bit sequence, the first check code being located at an end portion of the third bit sequence; obtain a fourth bit sequence by changing the bit order of the second bit sequence, the second check code being located at an end portion of the fourth bit sequence; and where the bit splitting unit 720 is further configured to: extract other bits than the first check code from the third bit sequence to obtain the first segment; and extract other bits than the second check code from the fourth bit sequence to obtain the second segment. [0099] In some embodiments, the polar decoding unit 710 includes a path adjusting unit configured to: determine log likelihood ratios (LLR) of a first number of decoding paths; sort the LLRs in a descending order; and removing a second number of decoding paths with low LLRs from the first number of decoding paths, the first number being twice the second number. [00100] In some embodiments, the polar decoding unit 710 includes a check unit configured to: in response to the first check code and the first information bits associated with the first check code being decoded, check the first information bit for the remaining decoding paths using the first check code; and in response to failures of all the checks of the remaining decoding paths, terminate the polar decoding.

[00101] For the sake of clarity, some optional units of apparatuses 600 and 700 are not shown in FIGS. 6 and 7. However, it is to be understood that each feature as depicted with reference to FIGS. 1-4 is likewise applicable to the apparatus 600; and each feature as depicted with reference to FIG. 5 is likewise applicable to the apparatus 700. Besides, each unit of the apparatus 600 and/or 700 may be a hardware module, or may be a software module. For example, in certain embodiments, the apparatus 700 may be partially or entirely implemented using software and/or firmware, for example implemented as a computer program product included on a computer readable medium. Alternatively or in addition, the apparatus 600 and/or 700 may be partially or entirely implemented based on hardware, for example implemented as an Integrated Circuit (IC), an application-specific Integrated Circuit (ASIC), a system-on-a-chip system (SOC), a field-programmable gate array (FPGA), and the like. The scope of the present disclosure will not limited in the regard. [00102] FIG. 8 is a block diagram of a communication device 800 suitable for implementing embodiments of the present disclosure. The device 800 may be used to implement the transmitting device or the receiving device in the embodiments of the present disclosure, for example the network device 101 or terminal device as shown in FIG. 1, or the first terminal device 111 or 112 as shown in FIG. 1. [00103] As shown in the example of FIG. 8, the device 800 includes a processor 810. The processor 810 controls operations and functionality of the device 800. For example, in certain embodiments, the processor 810 may perform various operations by means of instructions 830 stored in a memory 820 coupled thereto. The memory 820 may be of any appropriate type applicable to a local technical environment, and may be implemented using any appropriate data storage technique, including but not limited to, a semiconductor-based storage device, a magnetic storage device and system, an optical storage device and system. Although FIG. 8 only shows one memory unit, the device 800 may include a plurality of physically different memory units.

[00104] The processor 810 may be of any appropriate type applicable to a local technical environment, and may include, but not limited to, one or more of general purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs) and controllers based on multicore controller architecture. The device 800 may further include a plurality of processors 810. The processor 810 may be coupled to a transceiver 840 which may implement transmitting and receiving of information with aid of one or more antennae 850 and/or other components.

[00105] According to embodiments of the present disclosure, the processor 810 and the memory 820 may be operated in cooperation, to implement the methods 200, 400, and/or 500 as described with reference to FIGS. 2-5. Specifically, if the communication device 800 acts as a transmitting device, the communication device 800 may be caused to perform the method 200 when the instructions 830 in the memory 820 are executed by the processor 810. If the communication device 800 acts as a receiving device, the communication device 800 may be caused to perform the method 400 and/or 500 when the instructions 830 in the memory 820 are executed by the processor 810. It is to be understood that all features as described above are all applicable to the device 800, which are omitted herein.

[00106] FIG. 9 illustrates an example of the evaluation result of the block error rate (BLER) in accordance with embodiments of the present disclosure. In this example, the method in accordance with embodiments of the present disclosure is evaluated with the polar codes (128, 64) and (256, 128), where for the polar code (128, 64), the CRC bits are 16 bits, and the information bits are 48 bits; while for the polar code (256, 128), the CRC bits are 16 bits and the information bits are 112 bits. In this example, the CRC generator polynomial [1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1] is used, which is the same as LTE CRC ₁₆ . [00107] The CRC bits are transmitted immediately following the associated information bits and the new information bits. The evaluation result in FIG. 9 shows that on average, the polar decoder can terminate the decoding at the 32 ^nd information bit (namely, at a half of all the information bits). It is to be noted that for the polar code (128, 64), the total number of bits to be decoded by the polar decoder is 64 because both the information bits and the CRC bits should be decoded. It is to be further noted that the method in accordance with the embodiments of the present disclosure does not affect the BLER performance because this method only changes the transmission order of the information bits and the CRC bits. Moreover, upon occurrence of an error, no matter whether it is an information bit or a CRC bit, both the existing schemes and the embodiments of the present disclosure consider the information block to be erroneous, and therefore, the BLER would be the same.

[00108] FIG. 10 illustrates a schematic diagram of percentage of early termination occurrences in accordance with embodiments of the present disclosure. As can be seen from FIG. 10, in the two cases of employing different block sizes, early termination occurs in about 20% of the decoding, which is independent of the block size.

[00109] FIG. 11 is a schematic diagram of decoding saving due to the early termination in accordance with embodiments of the present disclosure. The decoding saving due to early termination is calculated with a ratio between the total number of undecoded bits and the total number of bits to be decoded. For example, if 64 bits are to be decoded, then on average, the early termination occurs at the 32 ^nd bit, thereby saving 50% of the decoding. As can be seen from FIG. 11, the smaller the block size is, the more benefits will be obtained from the early termination. Furthermore, for downlink control signaling, the control information is about tens of to hundreds of bits. The evaluation result covers 48 to 112 information bits, thus being very convincing.

[00110] Generally, various embodiments of the present disclosure may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, a microprocessor or another computing device. While various aspects of embodiments of the present disclosure are illustrated and described as block diagrams, flowcharts, or using some other pictorial representation, it will be appreciated that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

[00111] As examples, the embodiments of the present disclosure may be described in the context of the machine executable instruction which for example includes program modules executed in the device on a real or virtual processor. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, or the like that perform particular tasks or implement particular abstract data types. The functionality of the program modules may be combined or split between program modules as desired in various embodiments. Machine-executable instructions for program modules may be executed within a local or distributed device. In a distributed device, program modules may be located in both local and remote storage media.

[00112] Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by a computer or other programmable data processing devices, cause the functions/operations specified in the flowcharts and/or block diagrams to be implemented. The program code may execute entirely on a machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

[00113] In context of the present disclosure, the machine readable medium may be any tangible medium that may contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine readable medium may be a machine readable signal medium or a machine readable storage medium. A machine readable medium may include but not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine readable storage medium would include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[00114] Further, while operations are depicted in a specific order, this should not be understood as requiring that such operations be performed in the specific order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific embodiment details are contained in the above discussions, these should not be construed as limitations on the scope of the present disclosure, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination.

[00115] Although the present disclosure has been described in language specific to structural features and/or methodological acts, it is to be understood that the present disclosure defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms for implementing the claims.