BACKGROUND OF THE INVENTION Chemical-mechanical polishing (CMP) is used increasingly as a planarizing technique in the manufacture of very large scale integration (VLSI) integrated circuits.

It has potential for planarizing a variety of materials in IC processing but is used most widely for planarizing metallizied layers and interlevel dielectrics on semiconductor wafers, and for planarizing substrates for shallow trench isolation. The efficient polishing of copper surfaces has taken on added importance due to the wide spread use of the copper damascene process.

There are three critical consumable components in the CMP process. The first is the abrasive liquid slurry. The abrasive liquid slurry's composition must be altered, and special formulations must be produced for each different substrate being polished. For example, some substrates

require a high pH to be activated for polishing, while other substrates need a more acid environment. Still other substrates respond best to silica abrasives, while others require alumina or titanium abrasive particles. The second critical consumable component in the CMP process is the polishing pad. It must be very flat, uniform across its entire surface, and resistant to the chemical nature of the slurry and have the right combination of stiffness and compressibility to minimize effects like dishing and erosion. A third critical consumable component in the CMP process is the carrier film. The carrier film attaches the wafer to its rotating holder must be: adequately flat and uniform in its thickness; an adhesive that will hold it tightly to the carrier but not too tightly to the wafer; and immune to the chemical environment in which it works.

In trench isolation, large areas of field oxide must be polished to produce a planar starting wafer. Integrated circuits that operate with low voltages, i. e., 5 volts or less, and with shallow junctions, can be isolated effectively with relatively shallow trenches, i. e., less than a micron. In shallow trench isolation (STI) technology, the trench is backfilled with oxide and the wafer is planarized using CMP. The result is a more planar structure than typically obtained using LOCOS, and the deeper trench (as compared with LOCOS) provides superior latch up immunity. Also, by comparison with LOCOS, STI substrates have a much reduced"bird's beak"effect and thus theoretically provide higher packing density for circuit elements on the chips. The drawbacks in STI technology to date relate mostly to the planarizing process. Achieving acceptable planarization across the full

diameter of a wafer using traditional etching processes has been largely unsuccessful. By using CMP, where the wafer is polished using a mechanical polishing wheel and a slurry of chemical etchant, unwanted oxide material is removed with a high degree of planarity.

It is also well known that integrated circuit fabrication on semiconductor wafers require the formation of precisely controlled apertures, such as contact openings or"vias,"that are subsequently filled and interconnected to create components and VLSI or ultra large scale integration (ULSI) circuits. Equally well known is that the patterns defining such openings are typically created by optical lithographic processes that require precise alignment with prior levels to accurately contact the active devices located in those prior levels. In multilevel metallization processes, each level in the multilevel structure contributes to irregular topography.

In three or four level metal processes, the topography can be especially severe and complex. The expedient of planarizing the interlevel dielectric layers, as the process proceeds, is now favored in many state-of-the-art TC processes. Planarity in the metal layers is a common objective, and is promoted by using plug interlevel connections. A preferred approach to plug formation is to blanket deposit a thick metal layer on the interlevel dielectric and into the interlevel windows, and then remove the excess using CMP. In a typical case, CMP is used for polishing an oxide, such as SiO2, Ta205, W20,-It can also be used to polish nitrides such as Si3 N4, TaN, TiN, and conductor materials used for interlevel plugs, e. g., Cu, W, Ti, and TiN.

During conventional metal chemical-mechanical polishing (CMP) of metal stacks, an oxidant is used to convert the top metal to metal oxides. These metal oxides are subsequently abraded in situ with some harder metal oxide abrasives. It certain applications, it is desirable to selectively polish such metal surfaces without removing the underlying nitride surface, for example. In such situations, selective metal polishing and precise end-point detection are desirable features.

During metal CMP, areas dense in features (i. e., alignment marks) tend to oxidize at a faster rate than areas with sparse distributions. This uncontrollable oxidation of the metals forming the alignment marks is commonly referred to as oxide erosion. Additionally, manufacturers have observed that oxide erosion in dense arrays increases dramatically as batch sizes are increased.

Traditionally, polishing pads are composed of stacked polyurethane based materials, containing a softer bottom structure and harder top surface used for polishing. Two examples of such pads in wide commercial use include the IC1400 and IC1000/SUBAIV'", pads, manufactured by Rodeo, Inc. (Phoenix, Az.). Such polyurethane pads, however, are subject to wear down and glazing due to hydrolysis during polishing, with consequent deleterious effects on the rate and uniformity of planarization. This in turn requires frequent reconditioning to restore the pad's surface properties, with a subsequent loss in productivity and increase in costs.

Accordingly, what is needed in the art is an improved design for a semiconductor wafer polishing pad that reduces scratches and resultant yield loss during

chemical/mechanical planarization, provides selective metal polishing and end-point detection of such polishing.

SUMMARY OF THE INVENTION To address the deficiencies of the prior art, the present invention, in one embodiment, provides a polishing pad comprising a polishing body comprising a material wherein said material is a cross-linked polymer.

In another embodiment, the present invention provides a polishing apparatus. This particular embodiment includes a mechanically driven carrier head, a polishing platen, and a polishing pad attached to the polishing platen. The carrier head is positionable against the polishing platen to impart a polishing force against the polishing platen.

The polishing pad includes a polishing body comprising a material wherein the material is a cross-linked polymer.

Yet another embodiment provides a method of polishing a substrate. The method comprises positioning a substrate having at least one layer of material located thereon against a polishing pad attached to a polishing apparatus wherein the polishing pad includes a polishing body comprising a cross-linked polymer; and polishing the layer of material against the polishing pad.

The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a

basis for designing or modifying other structures for carrying out the same purposes of the present invention.

Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which: FIGURE 1 illustrates a polishing apparatus, including a polishing pad fabricated using a cross-linked polymer made according to the present invention; FIGURE 2 illustrates an exemplary contour plot of the depth of Copper removed during the polishing of a TEOS wafer having a layer of Copper and an underlying Ta barrier layer, using a pad (A32) fabricated using a cross-linked polymer according to the present invention, and a conventional polyurethane pad (IC1400); FIGURE 3 illustrates an exemplary change in coefficient of friction determined during the polishing of a TEOS wafer having a layer of Copper and an underlying Ta barrier layer, using a pad (A32) fabricated using a cross- linked polymer according to the present invention, and a conventional polyurethane pad (IC1000/SUBA IV).

DETAILED DESCRIPTION We have discovered that polishing pads containing a polishing body comprised of a crossed-linked polymer have unexpected desirable polishing properties. In particular, pads formed from such material are capable of uniformly and

rapidly removing a metal surface, such as copper, with relatively much slower removal rates of an underlying tantalum barrier layer and the silicon wafer.

In one particular embodiment, the cross-linked polymer may be made from a thermoplastic foam polymer.

Alternatively, the polishing pad may be made from a thermoplastic foam elastomer. In other embodiments, the cross-linked polymer has a closed cell structure. In another embodiment, the thermoplastic foam may include cross-linked polyolefins, such as polyethylene, polypropylene, and combinations thereof. In particularly useful embodiments, the crosslinked polymer may be a crosslinked polyethylene closed-cell foam such as Volara, available from Merryweather Foam, Inc. (Anthony, NM); or Aliplast', available JMS Plastics Supply, Inc. (Neptune, NJ), or from Atlas International (Sacramento, CA).

The cross-linked polymer of this invention may be fabricated by melt extrusion of the pellets into sheets, and then pads made by laser cutting, die cutting or similar process familiar to those skilled in the art of thermoplastic processing. Referring to FIGURE 1, these cross-linked polymers may then be incorporated into a polishing body 100 that includes a base pad 110, where a cross-linked polymer pad 120 forms a polishing surface located over the base pad 110. Optionally, a first adhesive material 130, such as epoxy or other materials well known to those skilled in the art, may be used to couple the base pad 110 to the cross-linked polymer pad 120. The polishing pads thus formed may also have a second adhesive material 140, well known to those skilled in the art, applied to the platen side. The polishing pad may

then be cleaned and packaged for use.

With continuing reference to FIGURE 1, the polishing body 100 may then be employed in a variety of CMP processes by incorporation into a polishing apparatus 150. The polishing apparatus 150 typically includes a mechanically driven carrier head 160, carrier ring 170, polishing platen 180, and a polishing pad that includes the polishing body 100 comprising the cross-linked polymer pad 120 of the present invention, attached to the polishing platen 180, optionally using the second adhesive 140. The substrate to be polished 185, typically a wafer, may be attached to the carrier ring with the aid of a third adhesive 190 also well known to those skilled in the art. The carrier head 160 is then positioned against the polishing platen 180 to impart a polishing force against the polishing platen 180, typically a repetitive, regular motion of the mechanically driven carrier head 160, while providing an appropriate slurry mixture well known to those skilled in the art.

With continuing reference to FIGURE 1, in such polishing processes, substrates 185 may be polished by positioning the substrate 185, having at least one layer, on to the above-described polishing apparatus 150, and polishing the layer against the cross-linked polymer pad 120 of the present invention. In one embodiment, the substrate 185 has at least one layer of material that is a metal layer. In a particular embodiment, the metal layer is copper. In another embodiment, the substrate 185 is located on a semiconductor wafer. Cross-linked polymer pads 120 of the present invention are particularly suited for polishing in shallow trench isolation (STI) in integrated circuit fabrication or other fabrication

techniques where large areas of field oxide or other dielectrics must be removed from the wafer to produce a planar surface prior to subsequent processing. The cross- linked polymer pad 120 of the present invention are also desirable for polishing interlevel plug materials such as W, Ti, Cu, Al, and other metals as well as nitrides or barrier materials such as Si3N4, TaN, TiN.

Another embodiment of the present invention includes a method to determine an endpoint for metal polishing. The endpoint may be determined by detecting a change in the coefficient of friction or a change in an acoustic signal during substrate polishing using the cross-linked polymer pad 120 of the present invention associated with the transition from removing the metal layer to removing at least a portion of another layer. Detection apparatus for determining changes in coefficient of friction or a change in an acoustic signal, such as that described by CETR, Inc.

(Campbell, CA), may be used.

Experiments The copper polishing properties of polishing pads made according to the present invention were compared to conventional polishing pads. First, a polishing apparatus was prepared according to the present invention by including a polishing pad whose polishing body comprised a cross-linked polymer, attaching the pad to a polishing platen, and attaching the platen to a mechanically driven carrier head. Specifically, the cross-linked polymer used was Type 6A or Type 10 Aliplast@ (JMS Plastic Supplies, Neptune, N. J.). Both are cross-linked closed cell polyethylene foam having a medium density and hardness of

about 34 Shore A (Type 6A) and about 60 Shore A (Type 10).

The blanket Copper polishing properties of polishing pads incorporating these materials, designated A32 and A40, respectively, were compared to two commercially available pads: an IC1400 pad, and an IC1000/SUBA IV pad stack (both manufactured by Rodel, Phoenix, Az) in two experimental protocols.

In the first protocol, an experiment to compare the uniformity of copper polishing using the IC1400 pad versus the A32 pad was carried out for 1 or 2 minutes using an IPEC-372 polisher (formerly IPEC, Inc., now SpeedFam-IPEC, Inc., Chandler, Az) with a down force of 3.5 psi; table and carrier speeds of 90 and 85 rpm, respectively; and slurry flow of 200 ml/min. The slurry was obtained from DuPont Air Products Nanomaterials, LLC (Carlsbad, California), contained hydrogen peroxide, and was adjusted to a pH of about 4. Ex si tu pad conditioning was used.

Tetraethylorthosilicate (TEOS) wafers having a deposited copper surface and an underlying 250 A thick tantalum barrier layer were used.

Contour plots of copper surfaces polished using the IC 1400 versus the A32 pad were measured electrically by measuring sheet resistance at 49 points distributed radially across the wafer. Texture maps were generated using software obtained from Resat@ Corporation (Resmat map model 487; Montreal, Quebec, Canada). As illustrated in FIGURE 2, the depth of copper removed across the wafer using the IC 1400 pad ranged from 3000 to 6500 A, and from 2000 to 5500 A in a second experiment (not shown). In contrast, the depth of copper removed us. ing the A32 pad was more uniform, ranging from only 4000 to 5250 A.

Using the same experimental protocol, in a second experiment, the average and standard deviation for the removal rate of copper (i. e., the average of 49 measurement points) was compared for the IC1400 pad versus the A32 pad.

The copper removal rate and its standard deviation using the A32 pad (4931 715 A/min) was not significantly different than the removal rate obtained using the IC1400 pad (5446 760 and 5429 801 A/min, in two experiments). Thus, the A32 pad removed copper at a rate comparable to that of a commercial pad.

Polishing using the A32 pad was continued until the copper layer was entirely removed and the Ta layer was polished for an additional two minutes. The thickness of Ta removed narrowly ranged from 75 to 175 A, and the average rate of removal over all 49 measurement points was only about 41 A/min. Finally, polishing was continued until the entire Ta layer was removed, and the underlying TEOS wafer was polished. The removal rate of the TEOS was about 45 A/min. Thus, the A32 pad polished the underlying Ta layer and TEOS wafer at much slower rates than the Copper layer. This shows that the A32 pad has a higher selectivity for Copper removal, as compared to Ta or Si.

Also using the same protocol, a third experiment was performed to examine the effect of two parameters, down force and table speed, on the removal rate of copper using the A32 pad. Three different down forces (i. e., 3,4.4 and 5 psi) and table speeds (i. e., 40,60 and 90 rpm) were examined. Either down force or table speed were held constant while the other of these two parameters was successively adjusted to each of the three above-mentioned values. The removal rate increased as a linear function of

increasing down force. For example, at a table speed of 40 rpm, the removal rate increased from 3416 875 A/min, with a down force of 3 psi, to 6826 491 A/min, with a down force of 5 psi. In contrast, the removal rate was relatively invariant at different table speeds. For example, at a down force of 3 psi, the removal rate increased slightly from 3416 875 A/min with a table speed of 40 rm, to 4452 730 A/min with a table speed of 80. Thus, of these two parameters, it is more desirable to adjust down force to produce faster removal rates.

In the second experimental protocol, the blanket copper polishing properties of the A32 pad was compared to the IC1000/SUBA IV pad stack. The comparison was performed using a Model PMT-A CMP tester (CETR, Inc., Campbell, Ca.), operated with a down force of 3 psi and table speed of 200 rpm. The PMT-A CMP tester was equipped with both a coefficient of friction and an acoustic signal detector.

An EP-C5001 slurry, (Cabot Microelectronics, Inc., Aurora, Il.) containing hydrogen peroxide and adjusted to a pH of about 6.1, was used. TEOS wafers having a 16,000 A thick copper surface and underlying 300 A thick tantalum barrier layer were used.

As illustrated in FIG. 2, during the copper polishing stage, the coefficient of friction measured by the tester was more uniform compared to the IC1000/SUBA IV pad stack.

Moreover, during a 300 second polishing period, the IC1000/SUBA IV pad never completely removed the Copper layer, whereas the A32 pad removed the Cu layer in about 220 s, as determined by an increase the coefficient of friction when the Ta layer was reached (FIGURE 3), or as similarly determined by an decrease in the acoustic signal

(not shown).

Using the same protocol, removal rates and the selectivity of removal of Cu versus Ta were compared for the A32 and A40 pads versus the IC1000/SUBA IV pad stack.

The rates of Cu and Ta removal were about 5700 A/min and about 170 A/min, respectively, using the IC1000/SUBA IV pad. In comparison, rates of Cu and Ta removal were about 5000 A/min and about 185 A/min, respectively, using the A40 pad. Thus, the selectivity of Cu over Ta removal, as characterized by the ratio of rates of Cu to Ta removal were about 33.5 and 27, for the IC1000/SUBA IV and A40 pads, respectively. For the A32 pad the Cu removal rate was about 3,300 5000 A/min. Both A32 and A40 pads were able to effectively polish wafers having a tungsten surface.

Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.