BACKGROUND OF THE INVENTION Current biasing circuits, or"current mirror"circuits, are generally well known. Current mirrors generally use transistors, FETs (Field-Effect Transistors) or BJTs (Bipolar Junction Transistors), to produce a controlled current in a"biased" device as a multiple of a reference current that flows in a"reference"device. In an ideal case, the multiplying factor depends only upon the geometrical properties of the reference and the biased device.

Current mirrors constructed of conventional transistor devices should come close to the ideal case, where the physical geometry of the transistors is the sole factor influencing errors. Transistors typically used in current mirror devices include MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), MESFET (Metal Semiconductor Field-Effect Transistor), HEMT (High-Electron-Mobility Transistor) and PHEMT (Pseudomorphic High-Electron-Mobility Transistor) devices. The opera- tion of these transistors is based upon the strength of an electrical field in a"channel" underneath a"gate"region. In the ideal case, inaccuracies in the current multiplication factor should relate back only to lithographic errors, which are unavoidable in semi- conductor device manufacturing. However, the lithographic errors can be minimized.

If the electrical device transfer functions are ideal, in the sense that differences in the electrical environment or temperature of the reference device and the

biased device do not influence the current multiplication factor, then the geometrical errors of the devices define the accuracy limit that can be achieved. However, this is not generally the case, particularly in advanced transistor devices with very short channel lengths ; the channel length being the physical length of the gate contact. Various operational parameters influence the current multiplication factor in traditional current mirror devices.

For instance, short channel effects, which result from channel length modulation due to changes in the transistor's drain-source voltage, effect the current multiplication ratio. Velocity saturation effects, which depend on the transistor's drain-source voltage and result from the limited drift velocity of charge carriers in the channel region of the transistor substrate, also effect the current multiplication ratio.

Threshold voltage modulation effects also influence the current multiplication ratio.

The threshold voltage modulation effects generally result from either a barrier lower- ing effect caused by increasing drain-source voltage in short channel length transistors, or a barrier increasing effect, particular to short channel length silicon MOSFET transistors, caused by increasing source-bulk voltage. Still further, drain-gate reverse leakage current, common to FETs, has an effect on the current multiplication ratio. The drain-gate leakage current typically results from reverse leakage, including tunnel- ling, in the gate-source Schottky contact in MESFET devices, or tunnelling through the gate oxide region in MOSFET devices.

The present invention is directed toward overcoming one or more of the above-mentioned problems.

SUMMARY OF THE INVENTION A current mirror circuit is disclosed including a reference device and a biased device, each having control, input and output elements, with the control element

of the biased device operably connected to the control element of the reference device.

A reference current source is connected to the input element of the reference device and produces a reference current flowing through the reference device, wherein a bias current is produced in the biased device as a multiple of the reference current. A compensation network is connected between the biased device and the reference device for maintaining a constant bias current in the biased device regardless of vary- ing operating characteristics in at least one of the biased device and the reference device.

In one form, the reference and biased devices include field effect transis- tors having gate, drain and source elements corresponding to the control, input and output elements.

In another form, the reference and biased currents flow from the drain to source elements in the reference and biased transistors, respectively. The varying operating characteristics include a varying voltage across the drain and source ele- ments of at least one of the biased transistor and the reference transistor.

The varying voltage across the drain and source elements of at least one of the biased transistor and the reference transistor results from at least one of thresh- old voltage modulation, short channel effects and gate leakage current occurring in at least one of the biased transistor and the reference transistor.

In another form, the compensation network includes a first resistor connected between the input element of the reference device and the control element of the biased device, and a second resistor connected between the input element of the biased device and the control element of the reference device.

The current mirror circuit may further include third and fourth resistors serially connected between the control elements of the reference device and the biased device. A feedback loop is provided between a node common to the third and fourth

resistors and the input element of the reference device. Depending upon the types of transistors implemented in the current mirror circuit, the feedback loop may include a unity gain amplifier or a level shifter biasing the reference device to operate in a saturation mode. The first and second resistors may have equal resistance values, and the third and fourth resistors may have equal resistance values.

In another form, the compensation network further includes a compensa- tion device having control, input and output elements, with the input element of the compensation device connected to the input element of the biased device, and the control element of the compensation device connected to the control element of the reference device. A fifth resistor is connected between the output element of the compensation device and ground.

The compensation device may include a field effect transistor having gate, drain and source elements corresponding to the control, input and output ele- ments.

In another form, the compensation network further includes a sixth resistor connecting the second and third resistors to the control element of the refer- ence device, and a seventh resistor connecting the first and fourth resistors to the control element of the biased device.

An object of the present invention is to cancel the effects of threshold voltage modulation in a current mirror device.

A further object of the present invention is to cancel the influence of short channel effects in a current mirror device.

A further object of the present invention is to cancel the influence of gate leakage current related effects in a current mirror device.

A further object of the present invention is to maintain a constant output current in a current mirror device regardless of voltage changes in either the reference or biased device.

Other aspects, objects and advantages of the present invention can be obtained from a study of the application, the drawings, and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a prior art current mirror circuit in silicon MOSFET tech- nology using enhancement mode n-channel transistors ; Fig. 2 shows a prior art current mirror circuit in GaAs MESFET technol- ogy using depletion mode n-channel transistors ; Fig. 3 shows a prior art biasing circuit utilized in common source ampli- fiers ; Fig. 4 is a graph illustrating the relationship between drain current and drain-source voltage in a biased transistor of a current mirror circuit due to short channel and threshold voltage modulation effects ; Fig. 5 is a graph illustrating the relationship between drain current and drain-source voltage in a biased transistor of a current mirror circuit due to gate leak- age current ; Fig. 6 shows a biasing circuit for a current mirror according to a first embodiment of the present invention compensating for short channel and threshold voltage modulation effects ; Fig. 7 is a graph illustrating the relationship between drain current and drain-source voltage in the biased transistor of the biasing circuit for a current mirror shown in Fig. 6 ;

Fig. 8 shows a biasing circuit for a current mirror according to a second embodiment of the present invention additionally compensating for drain-gate reverse leakage current effects ; and Fig. 9 is a graph illustrating the relationship between drain current and drain-source voltage in the biased transistor of the biasing circuit for a current mirror shown in Fig. 8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A common solution to the problem of providing a controlled current in a biased device is to"mirror"a reference current (typically much smaller than the current in the biased device for DC current efficiency reasons) that flows in a reference device into the biased device. Typically, such circuits are known as"current mirrors".

Current mirrors generally utilize FET devices operating in the saturation region. The DC transfer characteristics of an FET device operation in the saturation region are described in the following equation : ID = (K/2) (W/L) [VGS-(Vto-αVDS)]n(1+#VDS), where in-drain current, K = constant (depends on specific process parameters, e. g., layer thickness, carrier mobility, doping lev- els, etc.), W = channel width, L = channel length, VGS gate-source voltage,

Vto threshold voltage without threshold voltage modu- lation (Vto > 0 for enhancement mode transistors ; Vto < 0 for depletion mode transistors), VDS drain-source voltage, a threshold voltage modulation coefficient, n velocity saturation index (n = 2 in a long channel device without velocity saturation ; n = 1 in an ex- treme short channel device with velocity satura- tion) ; in a typical 0. 5 tim channel length device n ~ 1. 5, and channel length modulation coefficient (or"Early- Voltage"coefficient).

Fig. 1 illustrates a typical prior art current mirror, shown generally at 10, in silicon MOSFET technology using enhancement mode n-channel transistors Q, and Q2 operating in the saturation region, each transistor Qj. Qs having drain D, source S and gate G contacts. In operation, the gate currents IG, and IG2 flowing into the gates G, and G2 of transistors Q, and Q2 are zero (or very small compared to the reference current IREF supplied by current source 12). The drain-source voltage VDS1 of transistor Q, is equal to its gate-source voltage VGS, due to the feedback loop 14. The feedback loop 14 adjusts the gate-source voltage VGS1 of transistor Q1 such that the entire refer- ence current IREF will flow as the drain current of the"reference device"Q,.

Since the gates G"G2 ofthe two transistors QI, Q2 are connected together with their sourcesS,, S2connected to ground, and since there is no gate current flowing that would establish any voltage drop (IG1=IG2=0), the gate voltages applied to transis- tors Q, and Q2 will be equal (VGS, = VGS2). Thus, the output current IouT will mirror the reference current IREF. The accuracy of the current mirror 10 is limited by the

threshold voltage mismatch of the two transistors Q, and Q2, as well as by short chan- nel effects.

In order to achieve current multiplication ratios other than unity, the channel widths W"W2 ofthe transistors-Q"Q2 must be different. In an ideal case, the channel width W2 of Q2 is an integer multiple of the channel width W, of Ql. This will equalize the influence of short channel effects on the current multiplication ratio. In this case, IOUT is related to the channel widths Wl, W2 as follows : IOUT = IREF (W2/WI)- (Eq. 2) Fig. 2 illustrates a conventional current mirror, shown generally at 20, in GaAs MESFET technology using depletion mode n-channel transistors Q, and Q2.

The operation of the depletion mode current mirror 20 is identical to the operation of the enhancement mode current mirror 10 shown in Fig. 1, with the exception that measures have to be taken to account for the negative threshold voltage (Vt < 0) of transistors Q ;, Q2 in the depletion mode current mirror 20.

In order to ensure transistor operation in the saturation region, an addi- tional level shift is necessary between the gate G, and drain D, of the reference transis- tor Q,. This additional level shift is accomplished by a level shifter circuit 22 con- nected between the gate G, and drain D, of transistor Q,. The level shifter 22 gener- ally includes a series of diodes D,... DM that are forward biased by a"helper current" IH and voltage source Vss (Vss may be any negative voltage), and connected between the drain D, and gate G, of Q, through a"helper source follower"transistor QH. The voltage gain of the level shifter 22 is unity and its effect on the current mirror 20 is similar to that of the feedback loop 14 as described with respect to Fig. 1.

Fig. 3 illustrates a conventional biasing circuit, shown generally at 30, utilized in common source amplifiers. A solution to the problem of biasing common source amplifiers is an extension of the current mirrors 10, 20 shown in Figs. 1 and 2

by the addition of two resistors R, and R2 serially connected between the gates G, and G2 of transistors Q, and Q2, and a bypass capacitor CB connected between a node 32 common to resistors R, and R2 and ground. In the biasing circuit 30 shown in Fig. 3, depending upon the implementation with either enhancement mode (Fig. 1) or deple- tion mode (Fig. 2) transistors, the unity gain amplifier 34 may be replaced with either the level shifter 22 (with current source IH and voltage source Vss) of Fig. 2 or the feedback loop 14 of Fig. 1.

The bypass capacitor CB accomplishes a low impedance at the center node 32 such that the resistor R2, together with the gate input impedance of transistor Q2, determine the overall input impedance seen by the signal SOURCE connected to the gate G2 oftransistor Q2 through capacitor CK. Resistor R, should have a resistance equal to R2 x (W2/Wl) to aid in reducing the effects of gate leakage current. In the case of a linear amplifier, such as a low noise amplifier or a linear power amplifier, the reference current EF should be chosen such that the gain of the biasing circuit 30 is independent of device tolerances. In the case of a saturated amplifier, the reference current IREF should be chosen to be constant over temperature variations. Thus, assum- ing a unity gain amplifier 34, IF = IouT One disadvantage in the circuits previously described, is that in the presence of short channel effects, the current multiplication ratio will be different from the geometrical value (W2/W,) in the case where the drain-source voltages VDSI and VDS2 on the reference device Q, and the biased device Q2 are different. Generally, it can be found that in MOSFET and MESFET devices, the channel length modulation coefficient . increases as the channel length of the device decreases. In a common source amplifier case (Fig. 3) the minimum channel length available in the transistor technology in which the circuit is implemented is the most desirable one to use since it allows for the highest frequency of operation of the circuit. Thus, in order to achieve

a desired drain current ID2 (IOUT) operating point for the biased device Q2 over drain- source voltage VDS2 variations, caused by, for example, supply voltage (VBB) varia- tions, the influence of # must be compensated for.

Another disadvantage in the previously described circuits is that in the presence of threshold voltage modulation in short channel devices, the drain current ID2 nOUT) in the biased device Q2 will again be affected by changes in the drain-source VO1tage VDS2 Fig. 4 illustrates the drain current IDZ (IOUT) in the biased device Q2 as a function of its drain-source voltage VDS2 due to short channel and threshold voltage modulation effects. The transistors Q, and Q2 utilized to generate the graph of Fig. 4 are PHEMT transistors having a channel length of 0. 5 um. The geometric channel width ratio (W2/W,) is unity, the reference current IREF is 1 mA, and therefore the desired output current ID2 (IOUT) is 1 mA. However, as shown in Fig. 4, the output current ID2(IOUT) increases as VDS2 increases. The deviation shown in Fig. 4 is entirely due to short channel and threshold voltage modulation effects.

Another disadvantage to the general solution, as shown in Fig. 3, for biasing common source amplifiers is that any gate leakage current IGL1, IGL2 out of the gates G,, G2 of transistors Q, and/or Q2 will cause voltage drops across the serially connected resistors R, and R2. Even if the two resistors R,, R2 are ratioed according to the geometrical channel width ratio such that W2/w1 = R2/R1, the voltage drops across the resistors R, and R2 will be different since the drain-source voltages VDS1 and VDS2 (and also the drain-gate voltages VDG1 and VDG2) are not the same. Thus, the gate leakage currents IGLI and IGL2 Of transistors Q, and Q2 will be different since the gate leakage current IGLI,'GL2depends exponentially on the drain-gate voltages VDGI, VDG2 applied.

Fig. 5 illustrates the drain current ID2 (IOUT) in the biased device Q2 as a function of its drain-source voltage VDS2 due to the effects of gate leakage current.

The circuit utilized to generate the graph of Fig. 5 follows the schematic shown in Fig.

3, with transistors Q, and Q2 being PHEMT transistors having a channel length of 0. 5 um. The value of resistor R2 is 850 Q, the geometrical channel width ratio (W2/WI) is 75, and the desired output current ID2 (IOUT) is 150 mA. The deviation of the measured current ID2 (IOUT) from the desired value is due to the gate leakage current IGL2 of Q2 causing a voltage drop across R2 that is different from the voltage drop across the ratioed resistor R,, which is caused by the gate leakage current IGLI of Q, Fig. 6 illustrates a current biasing circuit, shown generally at 40, accord- ing to the present invention for minimizing the effects of short channel lengths and threshold voltage modulation generally present in current mirror circuits. The current biasing circuit 40 includes a reference transistor Q3 and a biased transistor Q4, each having drain D, source S and gate G contacts. Resistors Rl l and Rl2 are serially con- nected between the gates G3 and G4 of transistors Q3 and Q4, with a unity gain ampli- fier 42, or feedback loop, connected between a node 44 common to resistors R,, and R12 and the drain D3 of Q3. Depending upon the implementation of the unity gain amplifier 42 as either the level shifter 22 (with current source in and voltage source Vss) of Fig. 2, or the feedback loop 14 of Fig. 1, the biasing circuit 40 shown in Fig.

6 can be implemented as a current mirror in MOSFET and/or MESFET technologies.

The addition of capacitor CB makes it possible for the current biasing circuit 40 to be utilized in common source amplifiers (the signal SOURCE would be input to the gate G4 of transistor Q4).

The current biasing circuit 40 includes a compensation network 46 connected between transistors Q3 and Q4. The compensation network 46 includes a resistor R2, connected between the gate G3 of transistor Q3 and the drain D4 oftransis-

tor Q4, and a resistor R22 connected between the drain D3 of the transistor Q3 and the gate G4 of transistor Q4.

The sources S3, S4 of transistors Q3, Q4 are connected to ground. The gate currents IG1,IG2 are zero (or negligible with respect to IREF), and accordingly, there is no voltage drop across resistors Rll and R, 2. Similarly, the currents through resistors R2, and R22 are negligible with respect to IREF Since the drain D3 and gate G3 of transistor Q3 are connected together, via unity gain amplifier 42, the bias or output current IOUT (Io4) mirrors a reference current IREF which flows into the drain D3 of Q3 and is sup- plied by a current source 48. However, as previously noted, various operational parameters, such as short channel effects, threshold voltage modulation and gate leakage currents, influence the current multiplication factor and thus the output current IOUT (ID4) These operational parameters may result from a changing drain-source voltage VDS4 in transistor Q4, resulting from variations in the battery voltage VBB connected to the drain D4 of transistor Q4. The current biasing circuit 40 of Fig. 6 is designed to minimize the effects of these operational parameters.

For simplicity, it is assumed that there is only a threshold voltage (Vt) modulation effect influencing the transfer function of Eq. 1 (R = 0) : ID = (K/2) (W/L) [VGS-Vt], (Eq 3) where Vt = Vto - αVDS. (Eq. 4) The effective threshold voltage Vt3 of transistor Q3 is Vto-aVDS3, and the effective threshold voltage Vt4 of transistor Q4 is Vto-aVDS4. As the drain-source voltages VDS3, VDS4 of transistors Q3, Q4 change, so does their respective threshold voltage Vt3, Vt4. As the threshold voltages Vt3, Vt4 of transistors Q3, Q4 change, so does their respective drain currents ID3, ID4. From Eqs. 3-4, it follows that the difference between the two effective threshold voltages Vt3 and Vt4 is (Vt3 - Vt4) = α(VDS4 - VDS3). (Eq. 5

Since K, W and L in Eq. 3 are constants, the only way to compensate for a changing threshold voltage Vt (due to threshold voltage modulation effects, i. e., changing VDS) is to modify VGS such that VGS - Vt, where Vt = Vto - αVDS (Eq. 4), remains constant regardless of changes in the drain-source voltages. This is accomplished by the com- pensation network 46 of Fig. 6 as follows.

The output of the unity gain amplifier 42 forces a voltage Vcc on its output at node 44. Basic circuit analysis reveals that the voltage on the gate G3 of Q3 (VGS3) is higher than Vcc by the amount (VDS4-VCC) [R11/(R11 + R21)], and similarly, the voltage on the gate G4 of Q4 (VGS4) is higher than Vcc by the amount (VDS3-VCC) [R12/(R12 + R22)].

For symmetry reasons in a unity current gain mirror, R11=R12=R1, and similarly R2, =R22=R2. Accordingly, after simple algebraic manipulation, the difference of the two gates voltages VGS3, VGS4 is (VGS3-VGS4) [R1/(R1 + R2)] (VDS4 - VDS3).

Comparing Eq. 5 and Eq. 6, the difference of the gate-source voltages (VGS3-VGS4) of transistors Q3 and Q4 can be made equal to the difference of their effective threshold voltages (Vt3-Vt4) if the following design choice is made : α = R1/(R1 + R2).

This is the appropriate design choice for cancellation of the threshold voltage modulation effects, and thus the influence of changing drain-source voltages VDS3, VDS4. on the output current IOUT (ID4) In the presence of short channel effects, the parameter A in the transfer function of Eq. 1 has a non-zero value and must be taken into account. The effect of A is similar to the effect of a, in that A models the dependence of the drain current ID in transistors operating in the saturation region on their drain-source voltage VDS. This dependence stems from channel length modulation, L- (L-AL), with AL increasing

with increasing VDS. This leads to an additional factor in the drain current ID equation : ID # ID x (1 + #VDS).

Adding this additional factor to the transfer function of Eq. 1, the drain currents ID3, ID4 for the transistors Q3 and Q4 in Fig. 6 are : <BR> <BR> <BR> <BR> ID3 = (K/2)(W/L)[VGS3 - (Vto - αVDS3)]n(1 + #VDS3), (Eq. 7)<BR> <BR> <BR> <BR> <BR> ID4 = (K/2)(W/L)[VGS4 - (Vto - αVDS4)]n (1 + #VDS4). (Eq. 8) For compensation effects, it is assumed that the current through resistors R1 and R, 2 (R,) and R2, and R22 (R2) is negligible with respect to IREF Thus, ID3 is approximately equal to IREF.

Assuming a 1 : 1 current mirror, if the drain current ID4 (IOUT) through transistor Q4 is to remain constant regardless of changes in VDS3 and/or VDS4, then it follows that : #### = #### = 0. (Eq. 9) # VDS4 a VDS3 Basic circuit analysis of the current biasing circuit 40 of Fig. 6 reveals that VGS3 = [R2/(R1 + R2)]VCC + [R,/ + R2)] VDS49 and (Eq. 10) VGS4 = [R2/(R1 + R2)]VCC + [R1/(R1 + R2)]VDS3. (Eq. 11) After algebraic elimination of VCC, VGS4 vus3 + [R,ORI + R2)] (VDS3-VDS4O (Eq. 12) By virtue of the unity gain amplifier 42, and the fact that ID3 = IREF, VGS3 (Vto - αVDS3)[IREF/((1 + #VDS3)(KW/2L))]1/n (Eq. 13 Eq. 12 and Eq. 13 yield expressions that can be used to evaluate the partial derivatives of ID4 (Eq. 8) with respect to VDS3 and VDS4 (Eq. 9). After calculation of the partial

derivatives, a modified value for the appropriate values of the resistors is obtained, namely, R,/ (R, + R2) = α + (#/n)(VGS3 - Vt3). (Eq. 14) Since Vt3 will be provided by the manufacturer of the transistor device Q3, and VGS3 can be determined by knowledge of IREF (ID3), resistors R, (R11 and R12) and R2 (R2, and R22) can be chosen to obtain the appropriate ratio of Eq. 14. This is the appropriate design choice for cancellation of threshold voltage modulation and short channel effects on the output current IOUT (ID4) Fig. 7 illustrates the drain current ID4 (IOUT) Of Q4 as a function of its drain-source voltage VDS4 for the circuit of Fig. 6. Transistors Q3 and Q4 are PHEMT transistors each having a channel length of 0. 5pm. The geometric channel width ratio (W2/WI) is unity, with values for resistors R, I, Rl2, R2l and R22 chosen as follows : R11 = 1k# ; R12 = 1k# ; R2, = 50kQ ; and R22 = 50kQ. As seen from Fig. 7, the drain current ID4 (IouT) through Q4 remains constant regardless of changes in its drain-source voltage VDS4. Since a unity gain amplifier was assumed, the drain current ID4 (IOUT) equals the reference current P. EF, which is approximately 1 mA.

Fig. 8 illustrates a biasing circuit according to a second embodiment of the present invention, shown generally at 50, with like elements of Fig. 6 indicated with the same reference numbers and elements that have been modified indicated with a prime ('). In this second embodiment, the compensation network 46'further includes an additional compensation network 52 including transistor Q5 and resistor R4. De- vices Q5 and R4 are added to minimize the effects of drain-gate reverse leakage cur- rents as previously described. The drain Dus ouf transistor Q5 is connected to the drain D4 of transistor Q4, with the gate Gs oftransistor Q5 connected to the gate G3 oftransis- tor Q3. The resistor R4 is connected between the source Ss oftransistor Q5 and ground.

The biasing circuit 50 is of particularly utility for large current multiplication ratios.

The reason being that the absolute magnitudes of the drain-gate reverse leakage cur- rents IGL3 and IGL4 of transistors Q3 and Q4 differ more for larger multiplication ratios.

While this difference could be offset by ratioing the resistor values R,,/R and R2)/R22 according to the current mirror ratio, for large ratios this leads to unreasonably high resistance values for R,, and R2,. In addition, this approach does not work for a wide range of drain-source voltages VDS of the biased transistor Q4, but is only valid if the drain-source voltages VDS3 and VDS4 of both transistors Q3 and Q4 are equal.

Since large resistors generally consume a large amount of chip space and are not economical for monolithic integration, the total amount of chip area consumed by transistor Q5 and resistor R4, can be reduced by the addition of resistors R3, and R32.

Resistor R31 is connected between resistors Rl l-R2l and the gate G3 of transistor Q3, while resistor R32 is connected between resistors R12-R22 and the gate G4 of transistor Q4.

The addition of resistors R31 and R32 permits scaling of resistors R12 and R22 by a scaling factorS2 <1, e. g., R, 2 = S2Rl2 and R22 = S2R22, with resistor R32 chosen to be R32 = R22 (1-S2). The scaling factor 82 should be made as small as possible in a practical design, but big enough to keep the current IDS flowing in the compensation network 52 (Q5 and R4) below 5% to 10% of the reference current uF-It should be noted that the compensation network 52 (Q5 and R4) can be equally applied to both sides of the current mirror.

Operation of the biasing circuit 50 of Fig. 8 in minimizing drain-gate current leakage is as follows. Assume a large desired current multiplication factor, e. g., 75 as in a typical power amplifier application. Since Q4 will be sized much larger than Q3 (75 x in the present example), the leakage current IGL3 of the reference transis- tor Q3 can be neglected with respect to the leakage current IGL4 in the biased transistor Q4. As a practical matter, the gate leakage currents for each transistor are known a

priori, as the manufacturer of the device provides this information on the transistor spec sheet.

The transistor Q5 is chosen such that its channel length is the same as the other transistors Q3 and Q4 in the biasing circuit 50. As previously discussed, the gate- source voltage VGS3 of transistor Q3 is ideally the same as the gate-source voltage VGS4 of transistor Q4 (IG3 = IG4 = 0). It follows then, that the drain-gate voltage VDGS of transistor Q5 is equal to the drain-gate voltage VDG4 of the biased transistor Q4. This results in the same gate leakage current densities (gate leakage current per area) in both devices Q4 and Q5. From the area ratios of transistors Q4 and Q5, the actual gate leakage current IGLS flowing out of the gate Gus ouf transistor Q5 can be determined.

The leakage current IGLS flowing out of the gate G5 of transistor Q5 creates a voltage drop VGLS across the resistor series connection R31 and R, 1. Similarly, the leakage current IGL4 flowing out of the gate G4 of transistor Q4 creates a voltage drop VGL4 across the resistor series connection R32 and R12. Resistors R31, R11, R32 and R12 are chosen such that VGLS VGL4- Due to the action of the feedback loop (amplifier 42) around the refer- ence device Q3, the gate voltage VGS3 of transistor Q3 is held constant and the voltage at the output (node 44) of the unity gain amplifier 42 is lowered. This will then lower the gate voltage VGS4 of transistor Q4 and thereby reduce the drain current ID4 (IOUT) of transistor Q4.

The drain current ID5 through transistor Q5 is limited to a small value by resistor R4 which forces the gate-source voltage VGS5 of transistor Q5 to be close to the gate-source voltages VGS3 and VGS4 of transistors Q3 and Q4. In this manner, it is ensured that the reverse gate leakage current densities are equal for transistors Q4 and Q5. The amount of drain current ID5 in transistor Q5 does not influence the accuracy of the compensation network 52 (Q5 and R4). however, it should be kept small.

In an ideal case, the channel widths W3, W5 of the transistors Q3 and Q5 are integer multiples of each other with the channel width Ws of Q5 smaller than the channel width W4 of Q4 (W4=NWs, with N >> 1). Although this is not a requirement for proper operation of the biasing circuit 50, the chip area consumption due to the addition of the gate leakage compensation network 52 (Q5 and R4) is kept at a mini- mum.

Resistors R,, and R2, can be scaled by a scaling factor S, using the requirement that the current through the series connection of S1R21 - S1R11 should be the same as the current through the series connection of S2R22-S2R, 2. This balances the current sum at the output of the unit gain amplifier 42 at node 44.

The scaling factor S, is chosen to be S1=S2(VDS4/VDS3). This leads to values for the resistors as follows : R11=S1R11 and R2, =S, R2,. To balance the gate- source voltage shifts on both sides of the current mirror, and thus ensure a constant drain current ID4 (IOUT), the resistor R31 resistor R3, scaled accordingly scaled R3, R31[(W4/W3)/(N + 1) - S1]/(1 - S2).

Fig. 9 illustrates the drain current ID4 (IOUT) of transistor Q4 as a function of its drain-source voltage VDS4 achieved by the biasing circuit 50 of Fig. 8. Transis- tors Q3, Q4 and Q5 are PHEMT transistors each having a channel length of 0. 5pm. The geometric channel width ratio (W4/W3) is 75. The reference current IREF is 2 mA. The resistor values are as follows : R11 = 680# ; R12 = 255# ; R2, = 3 1k# ; R22 = 11.6k# ; R3, = 6. 8kQ ; R32 = 595Q ; and R4 = 10kQ. As illustrated, the desired output current IouT (ID4) is 150 mA (equal to 75 x the reference current IREF) over a changing drain-source voltage VDS4 in the biased device Q4.

While the invention has been described with particular reference to the drawings, it should be understood that various modifications could be made without departing from the spirit and scope of the present invention.