RECEIVER ARCHITECTURE

INVENTORS:

JOHN WILLIAM KESTERSON ANDREY MALININ

RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Patent Application No.

61/920,997 to John William Kesterson and Andrey Malinin, entitled "Current Meter for Load Modulation Communication Receiver Architecture," filed on December 26, 2013, and U.S. Utility Patent Application No. 14/565,010 to John William Kesterson and Andrey Malinin, entitled "Current Meter for Load Modulation Communication Receiver Architecture," filed on December 9, 2014, the content of which is incorporated by reference herein.

BACKGROUND

1. Technical Field

[0002] The disclosed embodiments relate generally to a switch mode power converter, and more specifically, to a switch mode power converter that facilitates communication from a load device coupled to a secondary side of the power supply to a primary side controller.

2. Description of the Related Arts

[0003] In a conventional isolated switching power supply such as a flyback power converter, a switch controller located on the primary side of the power supply regulates power to the load by controlling on-times and off-times of a switch based upon one or more feedback signals representing output power, output voltage, and/or output current. It is often desirable to communicate messages from the load device to the primary side controller so that the load device can communicate a desired voltage, current, or operating mode to be provided by the power converter. In devices that distribute power through a standard Universal Serial Bus (USB) cable, there are different conventional methods of communication. Some

conventional systems rely on communication through the D+/D- data lines of USB during negotiation stages where the power delivery method can be changed to different modes. However, it is often undesirable to use the D+/D- lines because connecting these lines to anything other than their normal high-speed communication path may impact the bit error rate. Another disadvantage of communicating operating mode information using the D+/D- data lines is that it such solutions typically require a communication integrated circuit on the secondary side of the charger/adapter, thereby increasing overall cost of the system.

SUMMARY

[0004] A switching power converter provides power to an electronic device based on a digital message generated by the electronic device. The electronic device generates the digital message by modulating a load current to the electronic device according to a predefined pattern. A transformer electrically isolates a secondary side of the switching power converter coupled to the electronic device from a primary side. A load current detector obtains samples of a primary side voltage sense signal representative of an output voltage to the electronic device and samples of a current sense signal representing a primary side current. The voltage sense signal and the current sense signal vary based on the modulated load current to the electronic device. The load current detector generates a load current signal representing a waveform of the modulated current to the electronic device. A digital decoder decodes the load current signal to recover the digital message encoding by the electronic device. A power controller controls switching of a switch to control at least one of an output voltage and an output current to the electronic device based on the voltage sense signal, the current sense signal, and the digital message.

[0005] The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The teachings of the embodiments of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings.

[0007] Figure (FIG.) 1 illustrates an embodiment of a switching power converter.

[0008] FIG. 2 illustrates an embodiment of a switching power converter with a secondary controller.

[0009] FIG. 3 illustrates a waveform representing a digital message encoded by modulating a load current. [0010] FIG. 4 illustrates an embodiment of a primary side controller for detecting a digital message in a switching power converter.

[0011] FIG. 5 illustrates example waveforms for various signals present during operation of a switching power converter when communicating a digital message.

[0012] FIG. 6 illustrates an embodiment of a secondary side of a switching power converter.

[0013] FIG. 7 illustrates an example embodiment of load current detection logic for a primary side controller in a switching power converter.

[0014] FIG. 8 illustrates example waveforms for an output current of a switching power converter.

[0015] FIG. 9 illustrates a more detailed diagram of load current detection logic for a primary side controller in a switching power converter.

[0016] FIG. 10 illustrates another embodiment of load current detection logic for a primary side controller in a switching power converter.

[0017] FIG. 11 illustrates example logic for a digital decoder in a primary side controller in a switching power converter.

[0018] FIG. 12 illustrates example waveforms associated with operation of a digital decoder in a primary side controller in a switching power converter.

[0019] FIG. 13 illustrates additional example waveforms associated with operation of a digital decoder in a primary side controller in a switching power converter.

[0020] FIG. 14 illustrates an example embodiment of a state machine associated with operation of a digital decoder in a primary side controller in a switching power converter.

DETAILED DESCRIPTION OF EMBODIMENTS

[0021] The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter.

[0022] The Figures (FIG.) and the following description relate to the preferred embodiments of the present invention by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of the present invention. [0023] Reference will now be made in detail to several embodiments of the present invention(s), examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the present invention for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the invention described herein.

[0024] A load device on a secondary side of an isolated switching power converter communicates a digital message to a primary side controller by modulating the load current in accordance with certain predefined timing patterns. The load current modulation is detected by the primary side controller and the digital message is decoded based on the predefined timing patterns. The load device may encode the digital message in order to control the primary side controller to operate in a particular mode compatible with the load device. In one embodiment, where the power converter is coupled to the load device via a USB cable, the digital message may be transmitted over the Vbus lines that provide power to the load device.

[0025] FIG. 1 is a circuit diagram illustrating an embodiment of a switching power converter 100 (e.g., a primary-side fly-back switching power converter). The switching power converter 100 provides power to a load device 121 via a Vdd connector 132 and a ground (GND) connector 134. In the case of a USB controller, the Vdd connector 132 and the GND connector 134 may correspond to the Vbus and GND lines respectively of the standard USB connector pin out. The switching power converter 100 includes, among other components, a transformer Tl having a primary winding Np, a secondary winding Ns, and an auxiliary winding Na, a switch 104 (e.g., a transistor), a primary side controller 102, an output rectifier diode Dl, resistors Rl, R2, R3, and output filter capacitor CI .

[0026] An input voltage (Vm) 108, typically a rectified AC voltage, is input to power converter 100. The primary side controller 102 controls the on state and the off state of the switch 104 using the switch control signal 106 with on-times (TO _N ) and off-times (TO _FF ). When the switch 104 is turned on during its on-time, energy is stored in the primary side windings Np of the transformer Tl . The voltage across the secondary winding Ns is negative and the diode Dl is reverse biased, blocking transfer of energy to the load device 121. In this state, energy is supplied to the load device 121 via capacitor CI . When the switch 104 is turned off, the energy stored in the primary winding Np of the transformer Tl is released to the secondary winding Ns of the transformer Tl . The diode Dl becomes forward biased enabling transfer of energy stored in the transformer Tl to the load device 121 and recharging the capacitor C I .

[0027] The resistors Rl and R2 form a voltage divider coupled in series with the auxiliary winding Na of the transformer Tl, and produce the sensed voltage (VS _EN S _E ) 112, which can be used to estimate the output voltage (VOU _T ) 110. The resistor R3 is coupled in series with the switch 104 to produce a voltage (IS _EN S _E ) 114 representing a primary side current which can be used in conjunction with VS _EN S _E 112 to estimate the output current Ι ₀ υτ 116.

[0028] In normal operation, the controller 102 monitors VS _EN S _E 112 and/or IS _EN S _E 114 and controls switching of the switch 104 to maintain a regulated output. For example, in a constant voltage mode (CVM), the controller 102 controls switching of the switch 104 to maintain VOU _T 110 substantially near a desired regulation voltage V _REF (for example, within an allowable error range). In a constant current mode (CCM), the controller 102 controls switching of the switch 104 to maintain Ιουτ 116 substantially near a desired regulation current I _REF (for example, within an allowable error range).

[0029] The controller 102 receives the voltage feedback signal VS _EN S _E and the current feedback signal IS _EN S _E and generates a switch control signal that is provided to the switch 104. The switch control signal controls the on/off states of the switch 104. In general, the controller 102 can implement any number of control schemes suitable for switch-mode power converters 100, such as pulse-width-modulation (PWM) or pulse-frequency-modulation (PFM), and/or their combinations. In one embodiment, the controller 102 outputs a control signal that causes the ON time (or duty cycle) of the power switch 104 to increase, during a certain switching cycle, in order to increase power delivery to the load during that switching cycle, or to decrease in order to decrease power delivery to the load during that switching cycle.

[0030] The primary side auxiliary winding Na of the transformer Tl allows for a low voltage VS _EN S _E 112 to be generated because the voltage can be scaled down based on the turn ratio of the secondary winding Ns and auxiliary winding Na. However, in an alternative

embodiment, the auxiliary winding Na may be omitted, and VS _EN S _E may instead be detected by directly monitoring the voltage across the primary winding Np.

[0031] FIG. 2 illustrates an example of a power converter 200 similar to the power converter 100 of FIG. 1, but includes a secondary side controller 210 (comprising an output current sensor 212, a decoder 214, and an isolation device 216) to provide secondary detection of a digital message generated by the load device 121. In this embodiment, the load device 121 generates the digital message by controlling an internal switch to turn on or off current to the load according to a recognizable pattern. The modulated secondary load current is sensed via the load current sensor 212 and the pattern is decoded by the decoder 214. The decoded message is then provided to the primary side controller 102 as signal 218 via an isolation device 216, such as an optocoupler. The primary side controller 102 then controls switching of the switch 104 based on the digital message. For example, the digital message may provide a voltage or current for the controller 102 to provide to the load device 121 or select an operational mode compatible with the load device 121 such a constant current mode or constant voltage mode.

[0032] FIG. 3 illustrates an example encoding technique that can be used to encode the digital message. Here, the load device 121 generates a digital message by turning on or off the output current to the load during different predefined time slots. For example, in the illustrated waveform, the load device 121 turns off current to the load to represent a first digital value (e.g., 0) and turns on current to the load (e.g., at a predefined current level) to represent a second digital value (e.g., 1).

[0033] FIG. 4 illustrates an embodiment of a primary side controller 102 that may be used in conjunction with the power converter 100 of FIG. 1. In this embodiment, the primary side controller 102 detects a digital message generated by the load device 121 using only primary side sensing. The embodiment of FIG. 4 provides a substantial cost benefit relative to the embodiment of FIG. 2 since the secondary side controller 210 is not needed. In this embodiment, the digital message generated by the load device 121 modulating the output current 116 is reflected to the primary side of the transformer Tl and can be detected on the primary side by the primary side controller 102 based on the feedback signals VS _EN S _E 112, Isense 114. For example, in one embodiment, the controller 102 comprises a load current detector 402, a digital decoder 404, and a switch controller 406. The load current detector 402 obtains samples of VS _E NS _E 112 and IS _E NS _E 114. Here, VS _E NS _E 112 is a primary side voltage related to the output voltage (e.g., a divided voltage across an auxiliary winding as shown in FIG. 1). Furthermore, IS _EN S _E 114 represents a primary side current and may be detected, for example, as a voltage across a sense resistor R3 in series with the primary winding Np as shown in FIG. 1. Based on the samples of VS _E NS _E 112 and IS _E NS _E 114, the load current detector 402 generates a load current signal 403 comprising a sequence of load current samples representing current to the load device 121 over a sequence of switching cycles. The digital decoder 404 decodes the load current signal 403 to recover the digital message as signal 405, and provides the recovered message 405 to the switch controller 406. The switch controller 406 then adjusts operation based on the digital message 405. For example, the switch controller 406 controls switching via the switch control signal 106 to achieve a particular output voltage, output current, or operating mode of the switching power converter 100 based on the digital message 405.

[0034] FIG. 5 illustrates example waveforms associated with the operation of the power converter 100 having the primary side controller 102 of FIG. 4 described above. In the illustrated example, the load device 121 modulates the load current (e.g., by turning on or off a switch) to be in one of two states (e.g., a on state and an off state) over a sequence of predefined time periods. In the illustrated example, the output current is modulated to alternate between the on state and off state during each period, thus representing the digital values (e.g., 0 1 0 1 0 1 ). The on and off states of the output current can be detected by monitoring the IS _EN S _E 1 14 and VS _EN S _E 1 12 signals. For example, the peak current in the IS _EN S _E signal 1 14 is higher when the output current 1 16 is in the on state than when the output current 1 16 is in the off state. Furthermore, the widths of the voltage pulses in VS _EN S _E 1 12 are wider when the output current 1 16 is in the on state than when the output current 1 16 is in the off state.

[0035] Based on the characteristics of the waveforms described above, the load current detector 402 can detect whether the load current is on or off by observing the peak current on the primary side of the controller 102 and comparing it to a threshold value. For example, the output current detector 402 determines that the load current is "on" when the peak current is above the threshold and determines that the load current is off when the peak current is below the same threshold or a different threshold set for hysteresis. However, due to the many different modes that mass produced power adapter/chargers operate in, this threshold method is not always robust to mode variations of the controller particularly if the controller 102 can operate in one of multiple PFM modes or in one of multiple PWM modes of operation, or when the controller is configurable to operate in either Continuous Voltage (CV) or Continuous Current (CC) mode.

[0036] To provide more robust detection of the message, the load current detector 402 can estimate the shape of the load current waveform via primary side sensing (as opposed to merely threshold testing of the primary peak current and/or primary voltage). As will be described below, an embodiment of the load current detector 402 detects the load current waveform by applying a digital filter to samples derived from the feedback signals IS _EN S _E 1 14 and VS _EN S _E 1 12. In one embodiment, the digital filter operates with variable sampling frequency while maintaining constant bandwidth. A state machine then correlates the filter output to determine patterns. The described technique beneficially provides reliable message recognition without false detection, and furthermore does not require a secondary side sensor.

[0037] FIG. 6 illustrates the secondary side of the power converter 100, where the load device 121 is modeled as a resistor R _L . The digital message is directly represented by the load current ILOAD 602. The relationship between ILOAD 602 and Ιουτ 1 16 is given by:

where / _c is the current going into the capacitor C 1. Since it is known that the capacitor C 1 and output load (modelled as RL) act as a low pass filter to the current source Ιουτ 1 16, ILOAD 602 can therefore be estimated by filtering Ιουτ 1 16 if the low pass filter bandwidth is set at or below the natural bandwidth of the system.

[0038] FIG. 7 illustrates an embodiment of a load current estimator 402 for estimating the load current waveform. At the end of each reset period TRESET of the transformer Tl , the average output current over the last sampling period (Iout) _Ts (Where Ts is a sampling period) is determined by the computation block 702 based on samples of VSENSE and ISENSE- In one embodiment, (Iout) _Ts can be determined as follows:

where D _isense is a voltage representative of the primary ISENSE peak current threshold # _sense is the resistance of the sense resistor R3 on the primary control switch 104, N _p is the number of turns of the primary side winding of transformer Tl , N _s is the number of turns of the secondary side winding of transformer Tl , T _reset is the time for the flyback transformer Tl to fully discharge (in Discontinuous Conduction Mode (DCM)), T _period is the period for the power conversion cycle, and Ts is a sampling period. T _PE RIOD, TRESET, and DISENSE can be derived from samples of ISENSE and VSENSE- The above relationship is valid for DCM, and is based on the fact that the secondary current is the product of the primary current and the turns ratio at the point where the transformer Tl communicates. The relationship in equation (1) describes the current from the secondary side of the transformer Tl to the output stage of the power converter 100.

[0039] In a digital implementation, equation (2) can be simplified as follows:

(Iout) _Ts = ^{D ISENSE7 ESET} (3)

Tperiod

[0040] This approximation simply removes the constants from equation (2). The

approximation is useful because an absolute current measurement is not necessarily needed, and the digital message can be detected based on the shape of the output current as a function of time. In one embodiment, the computation block 702 updates the value (Iout) _Ts once per switching cycle. In some embodiments, (e.g., when using PFM mode), the period of each switching cycle T _PERIO D can change.

[0041] The time machine signal generator 704 obtains the value of lout of (Iout) _Ts via signal 703 and synthesizes a signal 705 that represents the value of (Iout) _Ts (held constant) for a duration equivalent to the switching period T _PERIO D of the last cycle. The synthesized signal 705 is thus updated at the end of each switching cycle (which may be of variable duration). The synthesized signal 705 is then filtered using a low pass filter 706 to simulate the effect of the output capacitor CI and load resistance RL on the output current in order to generate a signal 707 that approximates a waveform of the load current. In one embodiment, the low pass filter 706 is tuned such that it is narrow enough in bandwidth so as to not capture the high frequency noise of the calculated result, but wide enough to support the communicated bit stream through the load current modulation scheme. In one embodiment, the low pass filter 706 is simple, but wide, and a time counter for each cycle is used. The use of a digital filter may be desirable since the input function to the filter is produced by calculations that already exist in the controller. In another embodiment, a continuous time filter may be used.

[0042] In order to maintain a constant bandwidth of the signal channel, it is also desirable to oversample the output of this ¾υτ sequence due to the non-periodic timing of its updates. To avoid aliasing, the signal is sampled at least as fast as the highest PWM frequency used in the system. The Nyquist frequency is one half of the highest PWM frequency.

[0043] The form of the filter 706 is a first order low pass seen as follows:

GW = ^; = y„= ^ (4)

dT _s

[0044] With a little algebra, the filter 706 is defined:

[0045] A further simplification of this filter is achieved when ⁷ ^ = 2 ⁿ — 1. When this is true, the multiply operations are easily swapped with shift and add/subtract operations. For example, if n = 3 in the above, it simplifies to: [0046] When τ » T _s , the add functions become quite wide, but there are no multiply operations, thus simplifying a digital implementation of the filter 706.

[0047] FIG. 8 illustrates an example waveform showing operation of the above described load current detector 402 of FIG. 7, In the illustrated waveform, IOUT is the output current from the secondary winding, Tpx is the switching period of a cycle x, and Trx is the transformer reset period associated with the switching cycle x. At the end of each

transformer reset period Trx (which also marks the end of the switching period Tp), <IOUT>T _S is calculated based on equation (3) (or alternatively, based on equation (2)). In the synthesized output signal, <IOUT ^> _TS is held constant for a duration Ioutx (for a cycle x), which is equal in period to the corresponding measured period Tpx of the cycle for which the calculation was completed.

[0048] FIG. 9 is a block diagram illustrating an example implementation of the current detector 402 for estimating the load current waveform. In this embodiment, a Treset pulse 901 (e.g., a short pulse) is generated at the end of each transformer reset. A train stop pulse 903 is another short pulse that is generated when the primary switch 104 has been turned off. The switching period T _P is measured by Tperiod counter 902 between two consecutive Treset pulses 901. The Treset counter 904 measures the reset period between a train stop pulse and the next Treset pulse 901. The results of the counters 902, 904 are captured by the capture blocks 906, 908 a short delay (implemented by delay block 910) after the Treset pulse 901 occurs since at this time both counters 902, 904 have the correct values. After another short delay (implemented by delay block 912), the captured values are passed to the calculate block 914 to calculate IOUT based on the measured switching period T _P and the measured reset time TR. Finally after another short delay (implemented by delay block 916), the calculated value for IOUT and the measured switching period Tp are written into the FIFO 918. The FIFO 918 outputs a signal DOUT representing the measured switching period T _P to control the duration of the Tperiod output counter 920. After this counter 920 reaches a terminal count (TC), then it clocks another pair of values (T _P and ¾υτ for that period) and the cycle repeats. The samples of IOUT can then be read from the FIFO 918 and filtered by filter 706 as described above.

[0049] In one embodiment, the depth of the FIFO 918 is determined by the ratio of the largest T _P to the shortest T _P that can happen in adjacent cycles if it is desired to not lose any data. For example if there is a short period where the DJSENSE remains the same, the average current for that cycle is larger due to the small Tp, but that large average output current is only present through the short duration of the cycle for which it was calculated. If the value is merely held there until the next calculation, it will appear that this extra current was there for a much longer time, and will introduce undesired noise into the current measurement (and therefore into the communication channel). The extra counter 920 overcomes this problem.

[0050] In another embodiment, to avoid using extra counters to ensure that each Ιουτ value is output for the correct time duration to the filter 706, an alternative embodiment uses a digital filter that is operable with a sample time that varies as the switching frequency varies. With a little algebra, equation (6) can be rewritten in terms of Tp instead of Ts:

xnTp+yn-l ^T ()\

- = T _{p +} r < ⁸ >

[0051] With two multiplies, two adds, and one divide, the Ts can be the T _P which is measured each cycle. From this, one can easily see that if T _P is short, the influence of the input is reduced. Although the arithmetic is slightly increased with this rendition, the counter

(time machine signal generator 704) is not used. In equation (8), x _n = Ipk _n ^reset , so the final equation reduces to: n = Τρ+τ (9)

[0052] FIG. 10 is block diagram illustrating this alternative method for estimating the load current. This implementation uses a computation and filtering block 1002 to output a signal 1007 representing the load current waveform using a variable sampling frequency. This implementation has more full multiplications, and still has wide registers due to the fact that tau is much greater than some Tp values. However, this method has the advantage of not using the time machine signal generator 704.

[0053] In another embodiment, the accuracy of the estimation of the load current waveform can be further improved by accounting for the fact that the current through the diode Dl be either going into our out of the output capacitor C 1.

[0054] As was shown before, the relationship is as follows:

[0055] I _c can be determined by the relationship:

Ic = ^ (1 1) [0056] Equation (1 1) can be used when C is known. Even if the exact value of C is not known, but it is known to be within a certain range, a second order correction can still be applied to enhance the accuracy some. V _out and Rvalues can be determined based on the samples of ISENSE and VSENSE- In another alternative embodiment, these parameters can be user-configurable.

[0057] As described above with respect to FIG. 4, once the load current waveform is estimated by the output current detector 402, the digital decoder 404 decodes the digital message from the waveform. Particularly, the digital decoder 404 perform a pattern recognition function to determine which pattern was the most likely to have been received from the samples representing the load current waveform. In communications theory, this function may be performed with a maximal likelihood detector which consists of a matched filter, which is also equivalent to an integration of the product of what is expected versus what is received. This can be performed on a bit by bit basis, or on a message by message. A maximal likelihood estimation of x for example is the value of x which makes the observed data the most probable. If a given message is cross correlated with every possible pattern in the space of available codes, the pattern that shows the highest cross correlation with the observed data is the most likely to have been transmitted.

[0058] A matched filter is the filter that yields the highest signal-to-noise ratio (SNR) at its output. A matched filter has an impulse response that is the flipped in place version of the expected signal. Since the filter performs convolution in the time domain, this is numerically the same as correlation. If a bank of correlation functions is operated over the duration of the symbol, the one that has the highest cross correlation points to the most likely symbol to have been transmitted. These correlation operations do not need to slide if the beginning of the symbol can be accurately determined.

[0059] The above described functions can be costly in terms of numerical processing requirements. For a very slow data rate pattern where only two patterns exist, this system can be considerably simplified while maintaining robust operation that will reliably detect patterns without false positives. In the power conversion scheme, it is generally better to miss a message than to falsely decide one was received, resulting in an output voltage or current change that was not requested by the load device.

[0060] In one embodiment, the digital decoder 404 comprises a bank of state machines that are expecting each pattern based on "on" and "off times. If there is a mistake in the pattern, the state machine goes to its beginning state, and waits for the correct pattern. [0061] FIG. 11 is an example embodiment of a digital decoder 404 and FIG. 12 illustrates a simulation of the digital decoder 404 of FIG. 11 for example inputs. Although FIGs. 11-12 describe a digital implementation, parts of it can be done with analog equivalent functions.

[0062] The estimated load current waveform is first de-glitched with a digital time filter that ensures that if the logic state changes, it remains in the changed state for a minimum time before the output of the filter changes to the new state. There is a group delay through the filter, but this does not affect performance since it is a minor delay and is applied to all transitions, thus differential time measurements are not affected. After the above processing, the resulting deglitched signal is processed by a bank of state machines that are each monitoring for the expected message pattern. The state machine is an event based machine and it advances with each transition in the filtered and de-glitched received signal.

[0063] In the block diagram, the filtered current measurement ("iom ' in FIGS. 11-12) 1102 representing the load current waveform is compared against a high threshold 1104 and a low threshold 1106 by a pair of comparators 1108, 11 10. The outputs of the comparators 1108, 1110 control an SR flop 1112. In the Glitch Removal block 1114, a deglitch operation is performed by using a counter. The glitch removal block 1114 ensures that the output of the raw received data stays in a particular state for more than a specified number of clock cycles before the transition is seen on the output of the signal "rx d". The counting operation is demonstrated in the waveform of FIG. 12 in the signal "rx d cnt". This counter ramps all the way to its max or down to its minimum before the output "rx d" is changed to the new state of the raw signal. If the raw signal changes back to its original value before this happens, the counter is set to the rail that corresponds to the previous setting. This ensures that a change is seen for a specified number of clock signals before it is propagated to the "rx d" signal. The "rx d" signal in the waveform of FIG. 12 corresponds to the output of the block "glitch removal" in FIG. 11.

[0064] The "rx d" signal is then processed to detect rising and falling edges by a rising edge detection block 1116 and a falling edge detection block 1118 respectively. These edges are logically "OR'd" together by an OR gate 11120 to be used as a counter reset. A free running counter 1122 outputs a signal shown as "sym cnt" in the waveform of FIG. 13. It appears as an analog saw-tooth waveform, where the counter is reset at every edge.

[0065] There are multiple message state machines 1124 in parallel that each receive 3 inputs; a rising edge detection signal 1126, a falling edge detection signal 1128, and a captured counter output 1130 which is the output of the counter 1122 at the last edge (either rising or falling). With these inputs, each Message State Machine 1124 is tuned for reception of one message. The outputs of the message state machines 1124 control the power control state block 1132, which configures the power state of the power converter 100.

[0066] In alternative embodiments, a different message decoding system may be used. For example, alternative messaging formats may include start, stop, parity, or data bits.

Although the techniques described herein are well suited for relatively slow message systems with a limited number of symbols, the method is also usable for faster speeds and more complex communications protocols. FIG. 13 defines an embodiment of a message pattern. A watchdog method is also defined here, which is a different form of message. The messages are relatively orthogonal (not easily mistaken one for another) and the likelihood of a false positive is very low.

[0067] FIG. 14 is a state machine diagram illustrating an embodiment of a state machine 1400 that can be used in the architecture described above. Every transition in the state diagram means that a rising or falling edge of the filtered output has occurred. Each time this does occur, the time windows are checked and the state machine 1400 advances according to the result of the windows associated with the state from which it is proceeding from. When the last state 1402 is arrived at, then the message is considered to have been received.

[0068] The transitions that advance the state machine 1400 are based on the correct edge detection combined with the captured count being within a defined window. This determines that this high or low period was as expected for this message. Any time this condition is not met (an edge occurs at the wrong time), the state machine 1400 is reset (returns to state SO), and begins waiting for a new message.

[0069] In the embodiment illustrated, there are 2 message types; an "increase" and a

"decrease" message. The purpose of these messages are to increase or decrease the regulation voltage value after the message is received. The messages could have very different purposes. The state variable for each of these machines is displayed in the waveform of FIG. 12 as "st_inc" and "st_dec" respectively.

[0070] The example message in FIG. 12 is a "decrease" message. Observation of "st inc" and "st dec" indicates that the increase state machine made it all the way through to message completion; while the state machine for the "increase" message only got part of the way through, because it is the wrong message. The state machines are also coordinated to one another such that if any of them sees a message complete, they are all reset, so that they start watching for the next message at the same time.

[0071] Upon reading this disclosure, those of skill in the art will appreciate still additional alternative embodiments through the disclosed principles herein. Thus, while particular embodiments and applications have been illustrated and described, it is to be understood that the disclosed embodiments are not limited to the precise construction and components disclosed herein. Various modifications, changes and variations, which will be apparent to those skilled in the art, may be made in the arrangement, operation and details of the method and apparatus disclosed herein without departing from the spirit and scope described herein.