Title:
CURRENT MIRROR CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2023/100368
Kind Code:
A1
Abstract:
A current mirror circuit 10 comprises: a plurality of first transistors P that are connected to a first power supply VCC at sources and to an input terminal Pi1 at gates and drains; and a second transistor P0 that is connected to the first power supply VCC at a source, to the input terminal Pi1 at a gate, and to an output terminal Po1 at a drain. A switch circuit PS is provided between the first transistors P and the input terminal Pi1. The switch circuit PS comprises: third and fourth transistors P13, P14 that are connected in series between the first transistors P and the input terminal Pi1; an inverter circuit INV1; and a fifth transistor N15 that is connected between an intermediate node md1 of the third and fourth transistors P13, P14 and an output terminal of the inverter circuit INV1. A switch control signal is applied to gates of the third through fifth transistors P13, P14, N15 and to an input of the inverter circuit INV1.
Inventors:
HU YISHEN (JP)
Application Number:
PCT/JP2021/044525
Publication Date:
June 08, 2023
Filing Date:
December 03, 2021
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H03F3/343; G05F3/26; H03K17/16; H03K17/687
Foreign References:
| JP2003323145A | 2003-11-14 | |||
| JP2006020098A | 2006-01-19 | |||
| JPH0865116A | 1996-03-08 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
Download PDF:
Previous Patent: WIRELESS COMMUNICATION SYSTEM, WIRELESS COMMUNICATION METHOD, BASE STATION, AND CONTROL PROGRAM
Next Patent: MOTOR CONTROL DEVICE
Next Patent: MOTOR CONTROL DEVICE