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Patent Searching and Data


Title:
CURRENT MODE LOGIC (CML) CLOCK DIVISION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2012/131795
Kind Code:
A1
Abstract:
A CML clock division circuit (1A) according to the present invention is provided with a plurality of latch circuits (31, 32) having a first and a second transistor groups (301, 302) which receive clock signals (CLK1, NCLK1) at the gates thereof, and a gate potential control circuit (10) which applies a gate bias voltage to the gates of the first and the second transistor groups (301, 302). The gate potential control circuit (10) has the function of adjusting the gate bias voltage to be applied in accordance with a fluctuation in the switching voltage of each transistor belonging to the first and the second transistor groups (301, 302).

Inventors:
ANDOU, Tosiakira (())
Application Number:
JP2011/004706
Publication Date:
October 04, 2012
Filing Date:
August 24, 2011
Export Citation:
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Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真1006番地 Osaka, 〒5718501, JP)
International Classes:
H03K23/44
Domestic Patent References:
WO2006118184A1
Foreign References:
JP2008011132A
JPH1051279A
JPH09107275A
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (Osaka-Marubeni Bldg, 5-7Hommachi 2-chome, Chuo-ku, Osaka-sh, Osaka 53, 〒5410053, JP)
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Claims: