[0002] Active matrix liquid crystal displays (AMLCD) have eliminated many problems associated with passive displays. For example, the fabrication of active matrix liquid crystal displays have enabled display screens to achieve greater brightness, enhanced readability, a greater variety of color shades, and broader viewing angles compared to displays that employ other technologies. Active matrix liquid crystal displays generally comprise an array of picture elements called pixels. An electronic switch is associated with each pixel in the display to control the operation thereof.

Various electronic switches such as, for example, thin film transistors and organic light emitting diodes (OLED), among others have been investigated to control pixel operation. Thin film transistors, in particular, offer a high degree of design flexibility and device performance.

[0003] Thin film transistors generally are formed on large area substrates having a high degree of optical transparency such as, for example, glass substrates. FIG. 1 depicts a cross-sectional schematic view of a thin film transistor (TFT) 122 being a type that has a bottom gate structure. The thin film transistor 122 includes a glass substrate 101 having an underlayer 102 formed on the surface thereof. A gate is formed on the underlayer 102. The gate comprises a gate metal layer 104 and a gate dielectric 108. The gate controls the movement of charge carriers in the transistor. The gate dielectric 108 formed over the gate metal layer 104 electrically isolates the gate metal layer 104 from semiconductor layers 110,114a, 114b, formed thereon, each of which may function to provide charge carriers to the transistor. A source region 118a of the transistor is formed on semiconductor layer 114a and a drain region 118b of the transistor is formed on semiconductor layer

114b. Finally, a passivation layer 120 encapsulates the thin film transistor 122 to protect it from environmental hazards such as moisture and oxygen.

[0004] Each layer is critical with respect to the electrical performance of the thin film transistor (TFT). In particular, the gate dielectric layer needs to have certain qualities (e. g., low flatband voltage (Vfb) ) in order for the transistor to have overall desirable electrical parameters, such as, for example, a high breakdown voltage (VB).

[0005] Many film layers can be deposited using conventional techniques, such as, for example, plasma assisted chemical vapor deposition (PECVD). Unfortunately, high temperatures are required to deposit film layers using PECVD techniques and high deposition temperatures may not be compatible with some substrates, such as glass substrates, as the glass may soften and become dimensionally unstable.

[0006] Therefore, a need exists to develop a method of forming high-quality film layers on temperature-sensitive substrates.

SUMMARY OF THE INVENTION [0007] A method of film deposition is described herein. The film is deposited using a cyclical deposition process. The cyclical deposition process consists essentially of a substantially continuous flow of one or more process gases modulated by alternating periods of pulsing and non-pulsing where the periods of pulsing alternate between pulsing a precursor into the process environment, and pulsing energy into the process environment to generate a plasma. Thus, the methods consist essentially of placing a substrate in a process chamber; exposing the substrate to a substantially continuous flow of a process gas composition under process conditions, and providing a period of non-pulsing. Next, a pulse of a precursor is provided to the process environment. Under the process conditions, the precursor does not react with the process gas composition. Once the precursor has been provided to the process environment, a second period of non-pulsing is provided. Next, a high frequency power is provided to the process environment to produce a plasma. Under the plasma conditions, the process gas composition does react with the precursor.

The reaction produces a film layer. The steps of pulsing and non-pulsing are repeated until a desired thickness of the film layer has been formed.

[0008] The methods of the present invention eliminate the need to provide a carrier gas and/or a purge gas in addition to a reactant gas unlike prior art methods.

Instead, a"process gas"or"process gas composition"is provided to a chamber in a continuous or substantially continuous manner throughout the deposition of the desired film layer. Essentially any film layer can be deposited in this manner using any precursor and process gas combination, as long as the precursor and the process gas composition do not react with each other (or react minimally) under process conditions, but do react with each other when the process environment is supplied with enough energy to produce a plasma.

BRIEF DESCRIPTION OF THE DRAWINGS [0009] So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments which are described in the present specification and illustrated in the appended drawings. It is to be noted, however, that the specification and appended drawings illustrate only certain embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

[0010] FIG. 1 depicts a cross-sectional schematic view of a bottom-gate thin film transistor (TFT); [0011] FIG. 2 depicts a schematic, cross-sectional view of a process chamber that may be used to practice the methods described herein; [0012] FIG. 3 illustrates a process sequence for film layer formation using cyclical deposition techniques according to one embodiment of the present invention; [0013] FIG. 4 is a graph showing the effect of precursor flow on film thickness.

[0014] FIG. 5 is a graph showing the effect of the length of the RF pulse on film thickness.

[0015] FIG. 6 is a graph showing the effect of non-pulsing time between the precursor pulse and the plasma pulse on film thickness.

[0016] FIG. 7 is a graph showing the effect of non-pulsing time between the plasma pulse and the precursor pulse on film thickness.

[0017] FIG. 8 is a graph showing the effect of spacing (in millimeters) between the electrode and the substrate on film thickness [0018] FIG. 9 is a graph showing the effect of RF power on film thickness.

[0019] FIGS. 10A-10C depict cross-sectional views of a substrate at different stages of a bottom-gate thin film transistor (TFT) fabrication sequence; and [0020] FIGS. 11 A-11 C depict cross-sectional views of a substrate at different stages of a top-gate thin film transistor (TFT) fabrication sequence.

[0021] FIG. 12 shows flatbed voltage of a gate dielectric film deposited by the methods of the present invention before annealing (FIG. 12A) and after annealing (FIG. 12B).

[0022] FIG. 13 shows flatbed voltage of a gate dielectric film deposited by the methods of the present invention.

DETAILED DESCRIPTION OF THE INVENTION [0023] The methods of the present invention relate to methods of cyclical deposition to form film layers on a substrate. The methods provided eliminate the need to provide a carrier gas and/or a purge gas in addition to a reactant gas. Instead, a process gas or process gas composition is provided to a chamber in a substantially

continuous manner throughout the deposition of the desired film layer. Essentially any film layer can be deposited in this manner using any precursor and process gas combination, as long as the precursor and the process gas composition do not react with each other (or react minimally) under process conditions, but do react with each other when the process environment is hit with enough energy to produce a plasma.

[0024] FIG. 2 shows a schematic sectional view of a process chamber apparatus 10 in which the methods of the present invention may be carried out. Apparatus 10 comprises a deposition chamber 12 that has a top wall 14 with an opening therethrough and a first electrode or a gas inlet manifold 16 within the opening.

Alternatively, the top wall 14 can be solid with the electrode 16 being adjacent to the inner surface. Within chamber 12 is a susceptor 18 in the form of a plate that extends parallel to the first electrode 16. The susceptor 18 may be made of aluminum and coated with a layer of aluminum oxide. The susceptor 18 is connected to ground so that it serves as a second electrode. The susceptor 18 is mounted on the end of a shaft 20 that extends vertically through a bottom wall 22 of the deposition chamber 12. The shaft 20 is movable vertically so as to permit movement of the susceptor 18 vertically toward and away from the first electrode 16. A lift-off plate 24 extends horizontally between the susceptor 18 and the bottom wall 22 of the deposition chamber 12 substantially parallel to the susceptor 18. Lift-off pins 26 project vertically upwardly from the lift-off plate 24. The lift-off pins 26 are positioned to be able to extend through holes 28 in the susceptor 18, and are of a length slightly longer than the thickness of the susceptor 18. While there are only two lift-off pins 26 shown in the figure, there may be more of the lift-off pins 26 spaced around the lift- off plate 24. A gas outlet 30 extends through a side wall 32 of the deposition chamber 12 and is connected to means (not shown) for evacuating the deposition chamber 12. A gas inlet pipes 42 extends through the first electrode or the gas inlet manifold 16 of the deposition chamber 12, and is connected through a gas switching network (not shown) to sources (not shown) of various gases. The first electrode 16 is connected to an RF power source 36. A transfer plate (not shown) is typically provided to carry substrates through a load-lock door (not shown) into the deposition

chamber 12 and onto the susceptor 18, and also to remove the coated substrate from the deposition chamber 12.

[0025] In the operation of the process chamber 10, a substrate 38 is first loaded into the deposition chamber 12 and is placed on the susceptor 18 by the transfer plate (not shown). The substrate 38 is of a size to extend over the holes 28 in the susceptor 18. The susceptor 18 lifts the substrate 38 off the lift-off pins 26 by moving shaft 20 upwards such that the lift-off pins 26 do not extend through the holes 28, and the susceptor 18 and substrate 38 are relatively close to the first electrode 16.

The electrode spacing or the distance between the substrate surface and the discharge surface of the gas inlet manifold 16 may be optimized depending on the kind of precursor and process gas used, as well as on the desired properties of the resulting film.

Film Formation [0026] Methods of film layer deposition are described. The film layer is deposited using a cyclical deposition process. The cyclical deposition process comprises adsorbing a precursor on the substrate, subsequently, when energy is supplied to the system, the precursor reacts with the process gas or process gas compostion to form the film layer on the substrate. Any film layer can be deposited in this manner using any precursor and process gas combination, so long as the precursor and the process gas composition do not react with each other (or react minimally) under process conditions, but do react with each other when a plasma is introduced into the process environment. One such film layer is a gate dielectric layer, for example, silicon nitride (Si3N4), silicon oxide (SiO), silicon dioxide (Si02), aluminum nitride, or aluminum oxide.

[0027] FIG. 3 illustrates a process sequence 400 illustrating the various steps used for the deposition of a film layer. These steps may be performed in a process chamber similar to that described above with reference to FIG. 2. In general, deposition conditions such as temperature, pressure, process gas and precursor flow rates, power and pulse times will vary depending on the process gas, precursor

and chamber being used. However, conditions are selected such that the precursor and the process gas composition do not react with each other (or react minimally) under the process conditions, but do react with each other when a plasma is introduced into the process environment.

[0028] As shown in step 402, a substrate is provided to the process chamber. The substrate may be, for example, a silicon, glass or clear plastic material suitable for film formation. Process chamber conditions, such as temperature and pressure, are adjusted to enhance the reaction of the precursor and the process gas. In general, for film layer deposition according to the present invention, the substrate should be maintained at a temperature of less than about 500 °C, preferably at about 350 °C, and at a process chamber pressure of between about 10 millitorr and about 10 torr.

[0029] However, in the present invention, the process gas or process gas composition is a reactant gas. In embodiments of the present invention where a substantially constant process gas flow is desired, a gas stream is established within the process chamber as indicated in step 404. Process gases and process gas compositions are selected so as to act as a reactant gas as well as a carrier gas and/or a purge gas. Typically, a carrier gas is a non-reactive gas such as, for example, helium (He), argon (Ar), nitrogen (N2), hydrogen (H2), or combinations thereof. Purge gases also are non-reactive gases, and can be the same or different than the gas used as a carrier gas. Unlike carrier gases, however, purge gases are not provided in a continuous or substantially continuous flow, but are instead provided to the system at predetermined intervals.

[0030] Reactant gases are those gases that react within the chamber to effect some chemical reaction. For example, reactant gases may serve as a catalyst for a reaction or, more typically, as a reactant in the chemical reaction.

Depending on the system and chemical reaction that is to take place, reactant gases typically are different in composition from the non-reactive carrier gases or purge gases. Reactive gases include, for example, ammonia (NH3), hydrazine

(N2H4), nitrogen (N2) and combinations thereof, among others, for the deposition of nitride layers. Suitable reactant gases may also include oxygen (02), ozone (O3), hydrogen (H2), water vapor (H2O) and combinations thereof, among others, for the deposition of oxide layers. In the current invention, one gas composition (the process gas or process gas composition) is used to serve the purposes of all of the gases used in prior art methods-the carrier gas, the purge gas and the reactive gas.

[0031] The conditions for the delivery of the process gas or process gas composition to the chamber are selected depending, among other things, on the nature of the process gas used, other process conditions (such as chamber temperature and pressure), and chamber size. For example, process gases may be provided to the chamber at 200-3000 sccm or greater.

[0032] Referring to step 406, after the process gas stream is established within the process chamber, a pulse of a precursor is added to the gas stream. For example, a silicon-containing precursor may comprise a halogenated silicon compound, such as silicon tetrachloride (SiCI4), dichlorosilane (Si2CI2H2,), and trichlorosilane (SiCl3H).

The silicon-containing precursor may also comprise other suitable silicon compounds such as siloxane compounds, silane (SiH4), or disilane (Si2H6), among others. The term pulse as used herein refers to a dose of material injected into the process chamber or into the gas stream. Such a dose may be a single injection of pre-determined duration, or several injections in succession. The pulse of the precursor lasts for a pre-determined time interval.

[0033] The time interval for the pulse of the precursor is variable depending upon a number of factors such as, for example, the volume capacity of the process chamber employed, the vacuum system coupled thereto and the volatility/reactivity of the reactants used. For example, a precursor pulse may last for about 0.2 seconds to about 5 seconds, or, preferably, about 0.5 second to about 2 seconds, or more preferably for about 0.7 seconds to about 1 second. However, the duration of the

precursor pulse will vary depending on chamber and substrate size and precursor and process gas flow rate. Flow rate for the precursor may be about 100 sccm to about 1000 sccm, and preferably is about 200-500 sccm. In general, the process conditions are selected advantageously so that a pulse of the precursor provides a sufficient amount so that at least a monolayer of the precursor is adsorbed on the substrate. Thereafter, excess precursor remaining in the chamber may be removed from the process chamber by the process gas stream in combination with the vacuum system.

[0034] In step 408, after the excess precursor has been sufficiently removed from the process chamber by the process gas stream, a high frequency power, such as an RF power, is applied to the chamber, for example, via a showerhead or susceptor (substrate support) to generate a plasma comprising the process gas composition within the process chamber. The application of the high frequency power to the substrate support pedestal lasts for a predetermined time interval, of, for example, about 2 to about 10 seconds, or of about 3 to about 5 seconds. In general, for film layer deposition, a high frequency power of about 500 Watts to about 2000 Watts may be applied or, preferably a high frequency power of about 750 watts to about 175 watts is applied, or, preferably a high frequency power of about 900 to about 1200 is applied.

[0035] Steps 404 through 408 comprise one embodiment of a deposition cycle for a film layer. For such an embodiment, a substantially constant flow of process gas is provided to the process chamber modulated by alternating periods of pulsing and non-pulsing where the periods of pulsing alternate between the precursor and the high frequency power, and the periods of non-pulsing consist essentially of the process gas stream. The present method is drawn to eliminating the need to provide a carrier gas and/or purge gas in addition to a reactant gas.

Instead, a process gas composition (comprising one or more reactant gases) is used. One skilled in the art, however, understands that substrate processing may include stopping the flow of the process gas composition

periodically or alternating or combining the process gas with another gas during processing.

[0036] The time interval for each of the pulses of the precursor and the high frequency power may have the same duration. That is, the duration of the pulse of the precursor may be identical to the duration of the pulse of the high frequency power. For such an embodiment, a time interval (T1) for the pulse of the precursor is equal to a time interval (T2) for the pulse of the high frequency power.

[0037] Alternatively, the time interval for each of the pulses of the precursor and the high frequency power may have different durations. That is, the duration of the pulse of the precursor may be shorter or longer than the duration of the pulse of the high frequency power. For such an embodiment, a time interval (T1) for the pulse of the precursor is different than a time interval (T2) for the pulse of the high frequency power.

[0038] In addition, the periods of non-pulsing between each of the pulses of the precursor and the high frequency power may have the same duration. That is, the duration of the period of non-pulsing between each pulse of the precursor and each of the pulses of the high frequency power is identical. For such an embodiment, a time interval (T3) of non-pulsing between the pulse of the precursor and the pulse of the high frequency power is equal to a time interval (T4) of non-pulsing between the pulse of the high frequency power and the pulse of the precursor. During the time periods of non-pulsing the constant process gas stream is provided to the process chamber.

[0039] Alternatively, the periods of non-pulsing between each of the pulses of the precursor and the high frequency power may have different durations. That is, the duration of the period of non-pulsing between each pulse of the precursor and each pulse of the high frequency power may be shorter or longer than the duration of the

period of non-pulsing between each pulse of the high frequency power and the precursor. For such an embodiment, a time interval (T3) of non-pulsing between the pulse of the precursor and the pulse of the high frequency power is different from a time interval (T4) of non-pulsing between the pulse of the high frequency power and the pulse of the precursor. During the time periods of non-pulsing only the constant process gas stream is provided to the process chamber.

[0040] The time intervals for each pulse of the precursor, the high frequency power and the periods of non-pulsing therebetween for each deposition cycle may have the same duration. For such an embodiment, a time interval (T1) for the precursor, a time interval (T2) for the high frequency power, a time interval (T3) of non-pulsing between the pulse of the precursor and the pulse of the high frequency power and a time interval (T4) of non-pulsing between the pulse of the high frequency power and the pulse of the precursor each have the same value for each subsequent deposition cycle. For example, in a first deposition cycle (Ci), a time interval (T1) for the pulse of the precursor has the same duration as the time interval (T1) for the pulse of the precursor in subsequent deposition cycles (C2... CN). Similarly, the duration of each pulse of the high frequency power and the periods of non-pulsing between the pulse of the precursor and the high frequency power in deposition cycle (Ci) is the same as the duration of each pulse of the high frequency power and the periods of non-pulsing between the pulse of the precursor the high frequency power in subsequent deposition cycles (C2... CN), respectively.

[0041] Additionally, the time intervals for at least one pulse of the precursor, the high frequency power and the periods of non-pulsing therebetween for one or more of the deposition cycles of the gate dielectric layer deposition process may have different durations. For such an embodiment, one or more of the time intervals (Ti) for the pulse of the precursor, the time intervals (T2) for the pulse of the high frequency power, the time intervals (T3) of non-pulsing between the pulse of the precursor and the pulse of the high frequency power and the time intervals (T4) of non-pulsing between the pulse of the high frequency power and the pulse of the precursor may have different values for one or more subsequent deposition cycles of the film layer

deposition process. For example, in a first deposition cycle (C1), the time interval (T1) for the pulse of the precursor may be longer or shorter than the time interval (Ti) for the pulse of the precursor in a subsequent deposition cycle (C2... CN). Similarly, the duration of each pulse of the high frequency power and the periods of non-pulsing between the pulse of the precursor and the high frequency power in deposition cycle (C1) may be the same or different than the duration of each pulse of the high frequency power and the periods of non-pulsing between the pulse of the precursor and the high frequency power in subsequent deposition cycles (C2... CN), respectively. One skilled in the art recognizes that a"pulse"may be a single dose or injection of a compound or application or energy; alternatively, a"pulse"may be two or more sequential doses or injections.

[0042] Referring to step 410, after each deposition cycle (steps 404 through 408), a certain thickness of the film layer will be formed on the substrate. Depending on specific device requirements, subsequent deposition cycles may be needed 411 to achieve a desired thickness. As such, steps 404 through 408 are repeated until the desired thickness for the film layer is achieved. Thereafter, when the desired thickness for the film layer is achieved 412, the process is stopped as indicated by step 413.

[0043] One exemplary process of depositing a silicon-containing gate film layer comprises depositing a silicon-containing gate dielectric layer by providing pulses of silicon tetrachloride (SiC14) in a process gas mixture of hydrogen (H2)/oxygen (02).

The tetrachloride (SiC) 4) may be provided to an appropriate flow control valve, for example, an electronic flow control valve, at a flow rate of between about 50 sccm (standard cubic centimeters per minute) and about 500 sccm, preferably at about 200 sccm, and thereafter pulsed for about 2 seconds or less, preferably about 0.5 to about 1 second. The hydrogen (H2)/oxygen (02) is provided at a flow rate between about 500 sccm to about 2500 sccm, preferably about 1000-2000 sccm. The process gas may be provided to an appropriate flow control valve, for example, an electronic flow control valve. The substrate may be maintained at a chamber pressure between about 0.05 torr to about 10 torr. The substrate is maintained at a

temperature less than about 500 °C, and preferably at less than about 350 °C. The above-mentioned flow rates for the silicon-containing precursor, and the reactant gas may be varied, depending upon the volume capacity of the process chamber.

The high frequency energy source may be RF supplied at about 250 to about 2000 Watts, and preferably at about 500 to about 1500 Watts.

[0044] Figures 4-9 are graphs showing the effect of various deposition parameters on film thickness for the deposition of a silicon dioxide gate dielectric layer. FIG. 4 shows the effect of the length of time of a SiCl4 pulse (at a flow rate of 200 sccm) on film thickness. Note that maximum thickness is achieved at less than 0.8 seconds per pulse, and that thickness decreases with time over 1 second. FIG. 5 shows the effect of the length of the RF pulse on film thickness. Note that maximum efficiency for the pulse is achieved at between 3 and 5 seconds.

[0045] FIG. 6 shows the effect of time for the non-pulsing interval between the pulse of the precursor and the energy pulse, where FIG. 7 shows the effect of time for the non-pulsing interval between the energy pulse and the pulse of the precursor. FIG. 8 shows the effect of electrode spacing on film thickness, and FIG. 9 shows the effect of RF power on film thickness.

Intearated Circuit Fabrication Processes Bottom-Gate Thin Film Transistor (TFT) [0046] FIGS. 1OA-10C illustrate cross-sectional schematic views of substrate structure 650 during different stages of a bottom-gate thin film transistor fabrication sequence incorporating a gate dielectric layer formed using a plasma enhanced chemical vapor deposition process. This particular transistor fabrication sequence is for a switch in an active matrix liquid crystal display and the process depicts the formation of one embodiment of an array of switches used in an active matrix liquid crystal display. FIG. 10A, for example, illustrates a cross-sectional view of a substrate 600. The substrate 600 may comprise a material that is essentially optically transparent in the visible spectrum, such as, for example, glass or clear plastic, including soda-lime glass, borosilicate glass, or quartz glass. The substrate

may be of varying shapes or dimensions. Typically, for TFT applications, the substrate is a glass substrate with dimensions greater than about 500 mm2.

[0047] The substrate 600 may have an underlayer 602 thereon. The underlayer 602 may be an insulating material, for example, such as silicon dioxide (Si02) or silicon nitride (SiN). The underlayer 602 may be formed using conventional deposition techniques.

[0048] A gate metal layer 604 is formed on the underlayer 602. The gate metal layer 604 comprises an electrically conductive layer that controls the movement of charge carriers within the TFT. The gate metal layer 604 may comprise a metal such as, for example, aluminum (Al), tungsten (W), chromium (Cr), tantalum (Ta), or combinations thereof, among others. The gate metal layer 604 may be formed using conventional deposition, lithography and etching techniques.

[0049] Referring to FIG. 10B, a gate dielectric layer 608 is formed on the gate metal layer 604. The gate dielectric layer 608 may comprise, for example silicon nitride (Si3N4), silicon oxide (SiO), and silicone dioxide (Si02), among others, deposited using an embodiment of the cyclical deposition technique described above with reference to FIG. 3. The gate dielectric layer 608 may be formed to a thickness in the range of about 20 Angstroms to about 5000 Angstroms.

[0050] Alternatively, the gate dielectric layer 608 may comprise two or more layers.

For such an embodiment, a first gate dielectric layer 608a may be formed using an embodiment of the cyclical deposition techniques described above with reference to FIG. 3. The first gate dielectric layer 608a may have a composition similar to gate dielectric layer 608.

[0051] Following the deposition of the first gate dielectric layer 608a, a second gate dielectric layer 608b may be deposited thereon using conventional deposition techniques such as, for example, chemical vapor deposition (CVD) or plasma

enhanced chemical vapor deposition (PECVD). The second gate dielectric layer may also comprise silicon oxide (SiO), silicon dioxide (Si02), or silicon nitride (Si3N4).

[0052] Additionally, the composition of first gate dielectric layer 608a and second gate dielectric layer 608b optionally may be different. For example, the first gate dielectric layer 608a may silicon dioxide (Si02), while the second gate dielectric layer may comprise silicon nitride (Si3N4).

[0053] Referring to FIG. 10C, a bulk semiconductor layer 610 is formed on the gate dielectric layer 608. Bulk semiconductor layer 610 may be formed using conventional deposition techniques. The bulk semiconductor layer 610 may comprise, for example, amorphous silicon or polycrystalline silicon. Bulk semiconductor layer 610 may be deposited to a thickness within a range of about 20 Angstroms to about 5000 Angstroms.

[0054] An etch stop layer 612 may be formed on bulk semiconductor layer 610. The etch stop layer 612 may comprise an insulating material, such as silicon nitride. The etch stop layer 612 may be formed using, for example, plasma enhanced chemical vapor deposition, chemical vapor deposition, physical vapor deposition, or other conventional methods known to the art. Etch stop layer 612 and bulk semiconductor layer 610 are lithographically patterned and etched using conventional techniques.

[0055] A doped semiconductor layer 614 is formed on the patterned etch stop layer 612 and semiconductor bulk layer 610. Doped semiconductor layer 614 may comprise, for example, silicon. The doped semiconductor layer 614 may be deposited to a thickness within a range of about 10 Angstroms to about 100 Angstroms. The doped semiconductor layer 614 directly contacts portions of the bulk semiconductor layer 610, forming a semiconductor junction.

[0056] A transparent conductor layer 616 is formed on portions of the gate dielectric layer 608 and the doped semiconductor layer 614. Transparent conductor layer 616 comprises a material that is generally optically transparent in the visible

spectrum and is electrically conductive. Transparent conductor layer 616 may comprise, for example, indium tin oxide (ITO), zinc oxide, among others.

Transparent conductor layer 616 is lithographically patterned and etched using conventional techniques.

[0057] A conductive layer 618 is formed on portions of the doped semiconductor layer 614 and the transparent conductor layer 616. Conductive layer 618 may comprise a metal such as, for example, aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), and combinations thereof, among others. The conductive layer 618 may be formed using conventional deposition techniques.

[0058] Both the conductive layer 618 and the doped semiconductor layer 614 may be lithographically patterned to define a source region 614a and a drain region 614b as well as a source contact 618a and a drain contact 618b. The source 614a and drain 614b regions of the thin film transistor (TFT) are separated from one another by the stop etch layer 612.

[0059] Thereafter, a passivation layer 620 may be deposited atop the substrate structure 650. Passivation layer 620 conformably coats exposed surfaces of gate dielectric layer 608, source contact 61 8a, drain contact 61 8b and etch stop layer 612, and semiconductor source 614a and drain 614b. The passivation layer 620 is generally an insulator and may comprise, for example, silicon oxide or silicon nitride.

The passivation layer 620 may be formed using conventional deposition techniques.

Top-Gate Thin Film Transistor (TFT) [0060] FIGS. 11 A-11 C illustrate cross-sectional schematic views of substrate structure 750 during different stages of a top-gate (TFT) fabrication sequence incorporating a gate dielectric layer formed using a cyclical deposition process. This transistor fabrication sequence is for a switch in an active matrix liquid crystal display, and the process depicts the formation of one of an array of switches used in an active matrix liquid crystal display. The top-gate thin film transistor (TFT) may be,

for example, a metal-oxide-semiconductor field effect transistor (MOSFET) or a junction field effect transistor (JFET).

[0061] FIG. 11 A, for example, illustrates a cross-sectional view of a substrate 700.

The substrate may comprise a material that is essentially optically transparent in the visible spectrum, such as, for example, glass or clear plastic, including soda-lime glass, borosilicate glass, or quartz. The substrate may have an underlayer 702 thereon. The underlayer 702 may be an insulating material, such as, for example, silicon dioxide (Si02) or silicon nitride (SiN).

[0062] A doped semiconductor layer 704 is deposited on the underlayer 702. The doped semiconductor layer 704 may comprise silicon. The doped semiconductor layer 704 includes n-type doped regions 704n and p-type doped regions 704p. The interfaces between n-type regions 704n and p-type regions 704p are semiconductor junctions that support the ability of the thin film transistor (TFT) to act as a switching device.

[0063] Referring to FIG. 11 B, a gate dielectric layer 708 is deposited on the n-type doped regions 704n and the p-type doped regions 704p. The gate dielectric layer 708 may comprise, for example, silicon nitride (Si3N4), silicon oxide (SiO), silicon dioxide (Si02), among others.

[0064] The gate dielectric layer 708 may be formed using an embodiment of the cyclical deposition process described above with reference to FIG. 3. The gate dielectric layer 708 may be deposited to a thickness within a range of about 20 Angstroms to about 5000 Angstroms.

[0065] A gate metal layer 710 is deposited on the gate dielectric layer 708, as shown in FIG. 11C. The gate metal layer 710 comprises an electrically conductive layer that controls the movement of charge carriers within the thin film transistor (TFT).

The gate metal layer 710 may comprise a metal such as, for example, aluminum (Al), tungsten (W), chromium (Cr), tantalum (Ta), or combinations thereof,

among others. The gate metal layer 710 may be formed using conventional deposition techniques. After deposition, the gate metal layer is patterned to define gates using conventional lithography and etching techniques.

[0066] After the gate metal layers 710 are formed, an interlayer dielectric 712 is formed thereon. The interlayer dielectric 712 may comprise, for example, silicon oxide or silicon nitride. Interlayer dielectric 712 may be formed using conventional deposition processes.

[0067] The interlayer dielectric 712 is patterned to expose the n-type doped regions 704n and the p-type doped regions 704p. The patterned regions of the interlayer dielectric 712 are filled with a conductive material to form contacts 720. The contacts 720 may comprise a metal such as, for example, aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), and combinations thereof, among others. The contacts 720 may be formed using conventional deposition techniques.

[0068] Thereafter, a passivation layer 722 may be formed thereon in order to protect and encapsulate a completed thin film transistor 725. The passivation layer 722 is generally an insulator and may comprise, for example, silicon oxide or silicon nitride.

The passivation layer 722 may be formed using conventional deposition techniques.

[0069] It is within the scope of the invention to form other devices that have configurations of semiconductor layers that are different from those described in FIGS. 10-11. For example, the switch may be any variety of bipolar or unpolar transistor devices wherein a gate dielectric layer is deposited using the plasma enhanced process described herein.

EXAMPLE [0070] Table 1 shows two sets of processing conditions for an exemplary deposition of SiO2 using the methods of the present invention. In the first set of data, the flow rate of both H2 and 02 is 500 sccm, whereas in the second set of data, the flow rate

of both the H2 and 02 is 2000 sccm. In addition, note that the period of non-pulse between the pulse of the SiC) 4 precursor and the RF pulse is 0.5 second in the first data set and 3.0 in the second data set, and the power of the RF pulse is 1000 W in the first data set and 500 in the second data set.

A D/R (film thickness divided by the number of cycles of deposition) of 1.06 was achieved in the first data set, whereas the second set of conditions resulted in a D/R of 0.69.

AGO H2 500 H2 500 H2 500 H2 500 300 Thick 1014 02500 02500 02500 02500 960 D/R 1. 06 1000W 200 1 ooow 0. 5 3 0. 5 0. 7 seconds seconds seconds seconds H2 H2 H2 H2 300 H2 977 2000 2000 2000 2000 02 02 02 02 Cycle 1420 2000 0. 69 1000 1000 1000 1000 I SiC 14 1 1600 H2-0. 87 200 mu 1 OOOW 0. 5 3 0. 5 0. 7 seconds seconds seconds seconds [0071] Figures 12A, 12B and 13 show the flatband voltage achieved for films using the methods of the present invention. FIG. 12A shows the flatband voltage before annealing, and 12B shows the flatband voltage after annealing. Figure 13 shows the flatband voltage of a film deposited at a flow rate for both H2 and Os at 500 sccm, a flow rate of SiC14 at 200 sccm, a process temperature of 300 °C, an electrode

spacing of 1100, an RF power of 1000 W, and the times of 0.5 seconds for the non- pulses between the pulse of the RF and the SiCl4 and the pulse of the RF and the SiC4 (i. e. both non-pulsing intervals), 3 seconds for the pulse of the RF, and 0.7 seconds for the pulse of the SiC) 4.

[0072] While the foregoing is directed to the preferred embodiment of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.