Title:
DATA-HOLDING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2020/079951
Kind Code:
A1
Abstract:
The purpose of the present invention is to minimize the sizes of data-holding circuits. First and second MOS transistors transmit a data signal and a reversed data signal, respectively, to input of first and second reversed gates constituting a status holding circuit when a clock signal is in a first level. Fifth and sixth MOS transistors are inserted to a feedback path from output of the second reversed gate to input of the first reversed gate and a feedback path from output of the first reversed gate to input of the second reversed gate, respectively, and transmit outputs of the second and first reversed gates, respectively when the clock signal is in a second signal level. Seventh and eighth MOS transistors are constituted in a channel of a conductive type that is different from that of the first MOS transistor and connected in parallel to the fifth and the sixth MOS transistors, respectively, and transmit the output of the second reversed gate and the output of the first reversed gate, respectively, on the basis of the reversed data signal and the data signal.
Inventors:
KAWAKAMI ATSUSHI (JP)
Application Number:
PCT/JP2019/032774
Publication Date:
April 23, 2020
Filing Date:
August 22, 2019
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H03K3/037; H03K3/356
Foreign References:
| JP2014216665A | 2014-11-17 | |||
| JPH11150458A | 1999-06-02 | |||
| JPH0282711A | 1990-03-23 |
Attorney, Agent or Firm:
MATSUO Kenichiro (JP)
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