Title:
DATA PROCESSING CIRCUIT WITH CACHE MEMORY
Document Type and Number:
WIPO Patent Application WO1999059070
Kind Code:
A3
Abstract:
The processing circuit contains a cache management unit which keeps information about a stream of addresses among addresses accessed by the processor. The cache management unit updates a current address for the stream in response to progress of execution of the program. The cache management unit makes selected storage locations in the cache memory available for reuse, a storage location in the cache memory which is in use for the data corresponding to the particular address being made available for reuse dependent on a position of the particular address relative to the current address.
More Like This:
| WO/1999/040516 | DISK CACHE CONTROL METHOD, DISK ARRAY DEVICE, AND STORAGE DEVICE |
| JP7311959 | Data storage for multiple data types |
| WO/2006/105158 | SYSTEM AND METHOD FOR TRANSFERRING WEB PAGE DATA |
Inventors:
VAN DER WOLF PIETER
STRUIK PIETER
STRUIK PIETER
Application Number:
PCT/IB1999/000785
Publication Date:
March 09, 2000
Filing Date:
April 29, 1999
Export Citation:
Assignee:
KONINKL PHILIPS ELECTRONICS NV (NL)
PHILIPS SVENSKA AB (SE)
PHILIPS SVENSKA AB (SE)
International Classes:
G06F12/121; (IPC1-7): G06F12/08
Domestic Patent References:
| WO1992020027A1 | 1992-11-12 |
Foreign References:
| US5649144A | 1997-07-15 | |||
| US5870599A | 1999-02-09 |
Download PDF: