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Patent Searching and Data


Title:
DATA-PROCESSING DEVICE AND DATA-PROCESSING METHOD
Document Type and Number:
WIPO Patent Application WO/2012/098982
Kind Code:
A1
Abstract:
This technology relates to a data-processing device and data-processing method having increased tolerance for data errors. With an LDPC code mapped to 16 signal points, said LDPC code having a block size of 16,200 bits and a code rate of 1/5, 4/15, or 1/3, a demultiplexer performs the following rearrangement, with "bi" representing the (i+1)th of 4×2 code bits and "yi" representing the (i+1)th of 4×2 symbol bits for two consecutive symbols, counting in both cases from the most significant bit: b0 to y4, b1 to y3, b2 to y2, b3 to y1, b4 to y6, b5 to y5, b6 to y7, and b7 to y0. The present invention can be applied, for example, to a transmission system for transmitting LDPC codes.

Inventors:
SHINOHARA YUJI (JP)
YAMAMOTO MAKIKO (JP)
Application Number:
PCT/JP2012/050461
Publication Date:
July 26, 2012
Filing Date:
January 12, 2012
Export Citation:
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Assignee:
SONY CORP (JP)
SHINOHARA YUJI (JP)
YAMAMOTO MAKIKO (JP)
International Classes:
H03M13/19; H04L27/00
Domestic Patent References:
WO2009116204A12009-09-24
WO2009104319A12009-08-27
WO2009107990A22009-09-03
Foreign References:
JP4224777B22009-02-18
Other References:
DVB-S.2 : ETSI EN 302 307, June 2006 (2006-06-01)
H. JIN; A. KHANDEKAR; R. J. MCELIECE: "Irregular Repeat-Accumulate Codes", PROCEEDINGS OF 2ND INTERNATIONAL SYMPOSIUM ON TURBO CODES AND RELATED TOPICS, September 2000 (2000-09-01), pages 1 - 8, XP002325752
S. Y. CHUNG; G. D. FORNEY; T. J. RICHARDSON; R. URBANKE: "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit", IEEE COMMUNICATIONS LEGGERS, vol. 5, no. 2, February 2001 (2001-02-01), XP011083973, DOI: doi:10.1109/4234.905935
See also references of EP 2667514A4
Attorney, Agent or Firm:
INAMOTO Yoshio et al. (JP)
Yoshio Inemoto (JP)
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Claims: